Measuring extremely low inductance values

[Piotr Wyderski]

Hi All,

this time this is out of pure curiosity, with no intention
or need to build a real device: many parts, particularly MOSFETs are
specified as "low parasitic inductance", but the values given
are insanely small. So, how do they measure 1nH? Or is it the
result of a FEM simulation?

Best regards, Piotr

[John Larkin]

I use TDR to measure things like that.

https://www.dropbox.com/s/v51gna10uwwfarc/Cree_TDR_Hardline.JPG?dl=0

https://www.dropbox.com/s/sgqwyhdzs90bnki/Cree_TDR_Fast.JPG?dl=0


A mosfet gate is in fact complex at the gory detail level. Pin
inductance, pin capacitance, wire bond, and finally the chip itself.

RF VNAs can measure 1 nH. 1 nH is 160 ohms at 1 GHz.




--

John Larkin Highland Technology, Inc
picosecond timing precision measurement

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

[speff]

Maybe something like a Agilent 4285A with 1pH resolution, plus a lot of thinking about custom test fixtures.

--Spehro Pefhany

[Piotr Wyderski]

John Larkin wrote:

> I use TDR to measure things like that.
>
> https://www.dropbox.com/s/v51gna10uwwfarc/Cree_TDR_Hardline.JPG?dl=0
>
> https://www.dropbox.com/s/sgqwyhdzs90bnki/Cree_TDR_Fast.JPG?dl=0

Interesting idea, thanks!

Best regards, Piotr

[Tim Williams]

"John Larkin" <jjlarkin@highland_snip_technology.com> wrote in message
news:l6d73e9nmri2469nu...@4ax.com...

> A mosfet gate is in fact complex at the gory detail level. Pin
> inductance, pin capacitance, wire bond, and finally the chip itself.
>

You say that, and yet don't realize your own waveform shows a very simple
RLC network transient response!

So, they /can/ be complex, but pole-zero cancellation can also make it
simple. Seems like power transistors tend to be simpler, while old
transistors have "drool" (a diffusion 1/sqrt(f) property, indicative of an
unoptimized gate structure, versus a fractal shape, say).

2N7002 has a dominant pole /roughly/ around 10MHz or so, but doesn't run out
of power gain until some 100s MHz. The impedance is very low up there too.
That Cree gate in particular seems to be nothing more than an RC (however
since the R adds with the 50 ohm source resistance, it's not clear what its
ultimate bandwidth is -- additional measurements are needed).

Tim

--
Seven Transistor Labs, LLC
Electrical Engineering Consultation and Design
Website: https://www.seventransistorlabs.com/

[Tim Williams]

Basically, the inductance due to the package/body length.

As mentioned, a VNA can do that. The LF equivalent may not necessarily
follow from high frequency measurements, or be very accurate if measured
directly.

It can be measured in situ by determining the switching loop time constant.

It can also be measured by following the transient amplitude around the
loop.

I did this on a recent power supply, where the switching loop was a 0612
current sense resistor, two 3x3mm DFN8 FETs, a 2512 +V-side jumper, and some
1206 bypass caps. I followed the switching transient peak around the loop,
and measured...

> Loop inductance (C540, R526, R504, R525, Q502) ~5nH
> Q502 drain to ground inductance: ~1.6nH
> Q502 source to ground inductance: ~0.5nH

I don't have any waveforms handy unfortunately.

Tim

--
Seven Transistor Labs, LLC
Electrical Engineering Consultation and Design
Website: https://www.seventransistorlabs.com/

"Piotr Wyderski" <pete...@neverland.mil> wrote in message
news:q10bip$nai$1...@node2.news.atman.pl...

[Piotr Wyderski]

Tim Williams wrote:

> As mentioned, a VNA can do that.

But how do you know what you're measuring? Is it your
pure L or some disributed parasitics? Any practical
way to disentangle them?

> It can also be measured by following the transient amplitude around the
> loop.

Doesn't the probe add so many unknowns that the result is meaningless?
How to do it properly?

Once upon a time my scope was able to make a TinySwitch flyback stutter,
and it was merely 100kHz and some hundreds of microhenries.

Best regards, Piotr

[Tim Williams]

"Piotr Wyderski" <pete...@neverland.mil> wrote in message

news:q10lgg$10a$1...@node2.news.atman.pl...

> Tim Williams wrote:
>
>> As mentioned, a VNA can do that.
>
> But how do you know what you're measuring? Is it your
> pure L or some disributed parasitics? Any practical
> way to disentangle them?

What do you want to measure? Calibrate to that standard, and there you go.

For example, you might measure the _difference_ in inductance due to the
part itself, as compared to a shorting bar in the same location.

Or you might look at the inductance due to the package and length, in which
case you need a stub that's shorted as closely as possible at *just before*
the package leads; then, subtracting that from the measurement with the
package plus its body length and the return path beneath it.

> Doesn't the probe add so many unknowns that the result is meaningless?
> How to do it properly?

Nah, probe don't mean shit. The loop impedance is tiny, ohms. My probe is,
low kohms at that frequency I think. :-)

A better question is where to ground to. In that circuit, I had multiple
layers (not that that actually matters) of ground, so comparing against
"infinite ground" is reasonable. The probe tip comes in perpendicular to
the board, away from most of the fields, which are internal to the board and
components. So, I have reasonable confidence that I can, in fact, measure
the waveform progressively along the total loop inductance, at least within
the, say, 20% ballpark I was interested in.

> Once upon a time my scope was able to make a TinySwitch flyback stutter,
> and it was merely 100kHz and some hundreds of microhenries.

Bad scope?? I don't understand.

My scope is 350MHz, and about 200MHz would be adequate for the loop I was
measuring. So, my Tek 475 would do just as well, though its trace intensity
would be awful for that particular measurement, and it also doesn't have a
MEAS menu...

[Phil Hobbs]

On 1/7/19 5:49 PM, Tim Williams wrote:
> Basically, the inductance due to the package/body length.
>
> As mentioned, a VNA can do that.  The LF equivalent may not necessarily
> follow from high frequency measurements, or be very accurate if measured
> directly.
>
> It can be measured in situ by determining the switching loop time constant.
>
> It can also be measured by following the transient amplitude around the
> loop.
>
> I did this on a recent power supply, where the switching loop was a 0612
> current sense resistor, two 3x3mm DFN8 FETs, a 2512 +V-side jumper, and
> some 1206 bypass caps.  I followed the switching transient peak around
> the loop, and measured...
>
>> Loop inductance (C540, R526, R504, R525, Q502) ~5nH
>> Q502 drain to ground inductance: ~1.6nH
>> Q502 source to ground inductance: ~0.5nH
>
> I don't have any waveforms handy unfortunately.
>
> Tim
>

I did that sort of thing measuring Uber's diode laser drivers (code name
Fuji). The total inductance of the laser + FET + 0402 storage cap was
under 400 pH--not bad going at all.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

[George Herold]

On Monday, January 7, 2019 at 3:28:54 PM UTC-5, John Larkin wrote:
> On Mon, 7 Jan 2019 21:07:50 +0100, Piotr Wyderski
> <pete...@neverland.mil> wrote:
>
> >Hi All,
> >
> >this time this is out of pure curiosity, with no intention
> >or need to build a real device: many parts, particularly MOSFETs are
> >specified as "low parasitic inductance", but the values given
> >are insanely small. So, how do they measure 1nH? Or is it the
> >result of a FEM simulation?
> >
> > Best regards, Piotr
>
> I use TDR to measure things like that.
>
> https://www.dropbox.com/s/v51gna10uwwfarc/Cree_TDR_Hardline.JPG?dl=0
>
> https://www.dropbox.com/s/sgqwyhdzs90bnki/Cree_TDR_Fast.JPG?dl=0

That is awesome, I see a long RC thing. Is the boxy thing
in front a capacitance? or something else?

George H.
(Who bought some fast gates to make a tdr, but is doing other stuff.)

[John Larkin]

On Mon, 7 Jan 2019 18:04:13 -0800 (PST), George Herold
<ghe...@teachspin.com> wrote:

>On Monday, January 7, 2019 at 3:28:54 PM UTC-5, John Larkin wrote:
>> On Mon, 7 Jan 2019 21:07:50 +0100, Piotr Wyderski
>> <pete...@neverland.mil> wrote:
>>
>> >Hi All,
>> >
>> >this time this is out of pure curiosity, with no intention
>> >or need to build a real device: many parts, particularly MOSFETs are
>> >specified as "low parasitic inductance", but the values given
>> >are insanely small. So, how do they measure 1nH? Or is it the
>> >result of a FEM simulation?
>> >
>> > Best regards, Piotr
>>
>> I use TDR to measure things like that.
>>
>> https://www.dropbox.com/s/v51gna10uwwfarc/Cree_TDR_Hardline.JPG?dl=0
>>
>> https://www.dropbox.com/s/sgqwyhdzs90bnki/Cree_TDR_Fast.JPG?dl=0
>That is awesome, I see a long RC thing. Is the boxy thing
>in front a capacitance? or something else?

The big flat part is the 50 ohm hardline cable between the sampling
head and the fet.

Then a couple of inductances, then the series resistance of the gate
and then the gate capacitance. SiC fets tend to have largish series
gate resistances.

A longer time base shows the gross gate capacitance better.

https://www.dropbox.com/s/h4sr4bp3yprcdpg/Cree_TDR_Slow.JPG?dl=0


What I sometimes do is make a Spice TDR and fiddle a fet model until
it looks like the measured TDR.

>
>George H.
>(Who bought some fast gates to make a tdr, but is doing other stuff.)
>
>
>>
>>
>> A mosfet gate is in fact complex at the gory detail level. Pin
>> inductance, pin capacitance, wire bond, and finally the chip itself.
>>
>> RF VNAs can measure 1 nH. 1 nH is 160 ohms at 1 GHz.

Actually, 6 ohms.

--

John Larkin Highland Technology, Inc

lunatic fringe electronics

[Jeroen Belleman]

I don't think that's very useful. Impedances, when closely
looked at, are always some combination of R, L, C and delays.
There is really no reasonable way to work that out with an
Agilent 4285A-like instrument, however precise.

TDR or VNA is really the the right solution here. I believe
VNAs yield better results. I get much cleaner TDR plots from
a VNA and an inverse FFT than from a straight TDR. The VNA
also makes de-embedding set-up parasitics much easier. There
is no objective reason why that couldn't be done with a TDR
as well, but it isn't common.

Jeroen Belleman

[George Herold]

On Monday, January 7, 2019 at 11:41:22 PM UTC-5, John Larkin wrote:
> On Mon, 7 Jan 2019 18:04:13 -0800 (PST), George Herold
> <ghe...@teachspin.com> wrote:
>
> >On Monday, January 7, 2019 at 3:28:54 PM UTC-5, John Larkin wrote:
> >> On Mon, 7 Jan 2019 21:07:50 +0100, Piotr Wyderski
> >> <pete...@neverland.mil> wrote:
> >>
> >> >Hi All,
> >> >
> >> >this time this is out of pure curiosity, with no intention
> >> >or need to build a real device: many parts, particularly MOSFETs are
> >> >specified as "low parasitic inductance", but the values given
> >> >are insanely small. So, how do they measure 1nH? Or is it the
> >> >result of a FEM simulation?
> >> >
> >> > Best regards, Piotr
> >>
> >> I use TDR to measure things like that.
> >>
> >> https://www.dropbox.com/s/v51gna10uwwfarc/Cree_TDR_Hardline.JPG?dl=0
> >>
> >> https://www.dropbox.com/s/sgqwyhdzs90bnki/Cree_TDR_Fast.JPG?dl=0
> >That is awesome, I see a long RC thing. Is the boxy thing
> >in front a capacitance? or something else?
>
>
> The big flat part is the 50 ohm hardline cable between the sampling
> head and the fet.

Oh sure, silly of me.

>
> Then a couple of inductances, then the series resistance of the gate
> and then the gate capacitance. SiC fets tend to have largish series
> gate resistances.
>
> A longer time base shows the gross gate capacitance better.
>
> https://www.dropbox.com/s/h4sr4bp3yprcdpg/Cree_TDR_Slow.JPG?dl=0

Some day I have to get my hands on a tdr to play with.
I don't have any great need though.

George H.

[Phil Hobbs]

On 1/7/19 5:31 PM, Tim Williams wrote:
> "John Larkin" <jjlarkin@highland_snip_technology.com> wrote in message
> news:l6d73e9nmri2469nu...@4ax.com...
>> A mosfet gate is in fact complex at the gory detail level. Pin
>> inductance, pin capacitance, wire bond, and finally the chip itself.
>>
>
> You say that, and yet don't realize your own waveform shows a very
> simple RLC network transient response!
>
> So, they /can/ be complex, but pole-zero cancellation can also make it
> simple.  Seems like power transistors tend to be simpler, while old
> transistors have "drool" (a diffusion 1/sqrt(f) property, indicative of
> an unoptimized gate structure, versus a fractal shape, say).
>
> 2N7002 has a dominant pole /roughly/ around 10MHz or so, but doesn't run
> out of power gain until some 100s MHz.  The impedance is very low up
> there too. That Cree gate in particular seems to be nothing more than an
> RC (however since the R adds with the 50 ohm source resistance, it's not
> clear what its ultimate bandwidth is -- additional measurements are
> needed).
>
> Tim
>

The SD-24 TDR head only puts out a few hundred millivolts. Fets start
doing complicated things at a few volts.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net

https://hobbs-eo.com

[Phil Hobbs]

They've been showing up on eBay for under a grand, including the
mainframe and one or more SD-24 TDR heads.

[George Herold]

OK, I can't buy one at work unless I can point to some need.
And for home... well next year I'll have two kids in college.
The LDP (local domestic product) will be negative for a couple
of years.

George H.

[John Larkin]

On Mon, 7 Jan 2019 16:31:51 -0600, "Tim Williams"
<tiw...@seventransistorlabs.com> wrote:

>"John Larkin" <jjlarkin@highland_snip_technology.com> wrote in message
>news:l6d73e9nmri2469nu...@4ax.com...
>> A mosfet gate is in fact complex at the gory detail level. Pin
>> inductance, pin capacitance, wire bond, and finally the chip itself.
>>
>
>You say that, and yet don't realize your own waveform shows a very simple
>RLC network transient response!

That's insulting. And it's not really simple, unless you plan to
design slow stuff.

>
>So, they /can/ be complex, but pole-zero cancellation can also make it
>simple. Seems like power transistors tend to be simpler, while old
>transistors have "drool" (a diffusion 1/sqrt(f) property, indicative of an
>unoptimized gate structure, versus a fractal shape, say).
>
>2N7002 has a dominant pole /roughly/ around 10MHz or so, but doesn't run out
>of power gain until some 100s MHz. The impedance is very low up there too.
>That Cree gate in particular seems to be nothing more than an RC (however
>since the R adds with the 50 ohm source resistance, it's not clear what its
>ultimate bandwidth is -- additional measurements are needed).
>
>Tim

The Cree fets have significant internal gate resistance, visible on
the TDR. The approximate C is obvious too. Rg is kinda distributed, so
the gate isn't exactly a lumped R-C, but adding a bit of external
series inductance can peak it up usefully.

--

John Larkin Highland Technology, Inc

lunatic fringe electronics

[Phil Hobbs]

Understood. I had two in college for five years out of ten. They all
graduated debt free though!

A TDR would be useful for superconducting inductance measurements. ;)

[speff]

If it would just work through a <100kHz pi filter..

[John Larkin]

On Tue, 8 Jan 2019 09:43:58 -0800 (PST), speff <spe...@gmail.com>
wrote:

People sometimes assume that TDR is a graph of impedance vs distance.
Often it sort of is. But every piece of the path affects everything
downstream, twice.

It's easy to fool TDR, and there are cases that no math can untangle.

[Tim Williams]

"John Larkin" <jjla...@highlandtechnology.com> wrote in message
news:1ag93el6cotqs1m5h...@4ax.com...

>
> That's insulting. And it's not really simple, unless you plan to
> design slow stuff.

I thought for sure you had seen this before; I guess not, in which case my
sincerest apologies.
https://www.seventransistorlabs.com/Images/C2M0280120_TDR_Fit.png

That was a curve fit to your data; it shows a simple RC.

[John Larkin]

On Tue, 8 Jan 2019 15:42:53 -0600, "Tim Williams"
<tiw...@seventransistorlabs.com> wrote:

>"John Larkin" <jjla...@highlandtechnology.com> wrote in message
>news:1ag93el6cotqs1m5h...@4ax.com...
>>
>> That's insulting. And it's not really simple, unless you plan to
>> design slow stuff.
>
>I thought for sure you had seen this before; I guess not, in which case my
>sincerest apologies.
>https://www.seventransistorlabs.com/Images/C2M0280120_TDR_Fit.png
>
>That was a curve fit to your data; it shows a simple RC.
>
>Tim

Well, there are the initial inductive bumps.

Cree has the full, nonlinear device model, with inductances, but they
got the substrate diode very wrong.

The TDR pulse is only 0.5 volts, so it doesn't excite the large-signal
nonlinearities.

[Tim Williams]

"John Larkin" <jjla...@highlandtechnology.com> wrote in message

news:jgra3el032nj3u35j...@4ax.com...

> Well, there are the initial inductive bumps.

Easily attributed to mismatch -- the component leads have a much higher TL
impedance for the 1-2cm length there. Which causes CM-diff mode conversion
so the whole thing rings a bit.

Here's a more exaggerated case, measured with a 10cm twisted pair hanging
off a BNC-binding post connector:
https://www.seventransistorlabs.com/Images/FQA9N90C_Gate_TDR.png
Same squiggles, still inconsequential to the measurement. (This case also
seems to have a dominant RC equivalent.) Tried to model it, think it's the
wrong equivalent though (R||L||C in series, R+L+C in parallel is probably
the correct equivalent).

> Cree has the full, nonlinear device model, with inductances, but they
> got the substrate diode very wrong.
>
> The TDR pulse is only 0.5 volts, so it doesn't excite the large-signal
> nonlinearities.

SiC diodes are pretty awful, but so are non-primitive SPICE models, so
often...

Y'ever seen an MOV model before? The formulas they use are a nightmare.

[John Larkin]

On Wed, 9 Jan 2019 06:49:05 -0600, "Tim Williams"
<tiw...@seventransistorlabs.com> wrote:

>"John Larkin" <jjla...@highlandtechnology.com> wrote in message
>news:jgra3el032nj3u35j...@4ax.com...
>> Well, there are the initial inductive bumps.
>
>Easily attributed to mismatch -- the component leads have a much higher TL
>impedance for the 1-2cm length there. Which causes CM-diff mode conversion
>so the whole thing rings a bit.
>
>Here's a more exaggerated case, measured with a 10cm twisted pair hanging
>off a BNC-binding post connector:
>https://www.seventransistorlabs.com/Images/FQA9N90C_Gate_TDR.png
>Same squiggles, still inconsequential to the measurement. (This case also
>seems to have a dominant RC equivalent.) Tried to model it, think it's the
>wrong equivalent though (R||L||C in series, R+L+C in parallel is probably
>the correct equivalent).
>
>
>> Cree has the full, nonlinear device model, with inductances, but they
>> got the substrate diode very wrong.
>>
>> The TDR pulse is only 0.5 volts, so it doesn't excite the large-signal
>> nonlinearities.
>
>SiC diodes are pretty awful, but so are non-primitive SPICE models, so
>often...
>
>Y'ever seen an MOV model before? The formulas they use are a nightmare.
>
>Tim

The Cree model shows 15 nH of gate inductance and 9 nH of source
inductance. In my HV pulser, I'm putting a couple of amps into the
gate with 1-2 ns edges, and I'm switching 12 amps in a few ns. Those
translate into 10s of volts of L di/dt. I'm amazed it works at all.

The limit on gate drive is blowing it up, which I have done. These
people have specified abs max gate voltages right on the eve of
destruction.

The chip itself is tiny and pretty far from the pins.

https://www.dropbox.com/s/hnu2b7qlfw98bwq/Cree_Chip.JPG?dl=0

It's actually a terrible package for fast work. Two or three smaller
parts in parallel might be better.

[Tim Williams]

"John Larkin" <jjla...@highlandtechnology.com> wrote in message

news:735c3elfbeigt3hne...@4ax.com...

> The chip itself is tiny and pretty far from the pins.
>
> https://www.dropbox.com/s/hnu2b7qlfw98bwq/Cree_Chip.JPG?dl=0
>
> It's actually a terrible package for fast work. Two or three smaller
> parts in parallel might be better.
>

That RF transistors exist, in TO-220 and 247 and other gnarly packages, is
remarkable.

I remember reading the datasheet for a a low-VHF RF final in TO-220. The
s-params go all the way around the circle at the intended operating
frequency. Yikes.

I remember seeing a Microsemi MOSFET module (half bridge) that was rated up
to _200kHz_. What's the freaking point? It cost ten times more than the
equivalent rating in TO-247s, and contained as much internal stray
inductance as two TO-247s in series. The mind boggles.

IGBTs are now fast enough that they _have_ to worry about that, and so most
new IGBT modules are, you know, actually made right, with laminated bus bar
construction.

Power GaN is almost only available in DFN and CSBGA, as it must. That
anyone even thinks they want one in TO-220... yeesh!

[George Herold]

On Wednesday, January 9, 2019 at 7:25:10 PM UTC-5, Tim Williams wrote:
> "John Larkin" <jjla...@highlandtechnology.com> wrote in message
> news:735c3elfbeigt3hne...@4ax.com...
> > The chip itself is tiny and pretty far from the pins.
> >
> > https://www.dropbox.com/s/hnu2b7qlfw98bwq/Cree_Chip.JPG?dl=0
> >
> > It's actually a terrible package for fast work. Two or three smaller
> > parts in parallel might be better.
> >
>
> That RF transistors exist, in TO-220 and 247 and other gnarly packages, is
> remarkable.

My* Rubidium lamp (~70 MHz, ~1.5W) is a coil/auto-transformer, cap
and 'gnarly package' RF power npn, AFAICT they are made in Russia.

George H.
*mostly copied from an Rb freq. standard company with their
blessing, they stopped making the lamp with no US supplier.
We were buying lamps from them, I think mostly as a favor.
(We had an old atomic physicist (oap), who knew their oap.)

[John Larkin]

On Wed, 9 Jan 2019 18:24:59 -0600, "Tim Williams"
<tiw...@seventransistorlabs.com> wrote:

>"John Larkin" <jjla...@highlandtechnology.com> wrote in message
>news:735c3elfbeigt3hne...@4ax.com...
>> The chip itself is tiny and pretty far from the pins.
>>
>> https://www.dropbox.com/s/hnu2b7qlfw98bwq/Cree_Chip.JPG?dl=0
>>
>> It's actually a terrible package for fast work. Two or three smaller
>> parts in parallel might be better.
>>
>
>That RF transistors exist, in TO-220 and 247 and other gnarly packages, is
>remarkable.

In an RF amp, you can tune out/resonate the parasitics. Some RF ldmos
fets have deliberate wire-bond inductances that optimize for some
specific RF band.

We work wideband, time domain, so we want low inductances. The tuned
RF fets are useless to us.

--

John Larkin Highland Technology, Inc

[bule...@columbus.rr.com]

2 pi f l .... 1Ghz and 1 NH cancel out.... 6.2 "ohms"

[John Larkin]

On Thu, 10 Jan 2019 11:39:53 -0800 (PST), bule...@columbus.rr.com
wrote:

>2 pi f l .... 1Ghz and 1 NH cancel out.... 6.2 "ohms"

Right. I corrected that a few days ago.

It's 1 pF that's 160 ohms at 1 GHz.

[John Miles, KE5FX]

On Monday, January 7, 2019 at 12:28:54 PM UTC-8, John Larkin wrote:
> https://www.dropbox.com/s/v51gna10uwwfarc/Cree_TDR_Hardline.JPG?dl=0
>
> https://www.dropbox.com/s/sgqwyhdzs90bnki/Cree_TDR_Fast.JPG?dl=0
>

That's such a nifty plot that I couldn't resist adding one of those
to an outgoing DigiKey order:

http://www.ke5fx.com/Cree_TDR_lg.gif
http://www.ke5fx.com/Cree_TDR_photo.jpg

Same features visible at similar detail with a 50 GHz sweeper and a
(SD-32?) sampling head. Guess ol' Joseph F. knew what he was talking
about after all.

-- john, KE5FX

[John Larkin]

On Sun, 13 Jan 2019 00:10:02 -0800 (PST), "John Miles, KE5FX"
<jmi...@gmail.com> wrote:

>On Monday, January 7, 2019 at 12:28:54 PM UTC-8, John Larkin wrote:
>> https://www.dropbox.com/s/v51gna10uwwfarc/Cree_TDR_Hardline.JPG?dl=0
>>
>> https://www.dropbox.com/s/sgqwyhdzs90bnki/Cree_TDR_Fast.JPG?dl=0
>>
>
>That's such a nifty plot that I couldn't resist adding one of those
>to an outgoing DigiKey order:
>
>http://www.ke5fx.com/Cree_TDR_lg.gif
>http://www.ke5fx.com/Cree_TDR_photo.jpg

Is that a TDR derived from a VNA frequency sweep? The right side isn't
the same RC tau that I see; what was your sweep range?

TDR is DC!

>
>Same features visible at similar detail with a 50 GHz sweeper and a
>(SD-32?) sampling head. Guess ol' Joseph F. knew what he was talking
>about after all.
>
>-- john, KE5FX

Those Cree fets are great, but they do need a lot of gate drive.

--

John Larkin Highland Technology, Inc

lunatic fringe electronics

[boB]

I know that SiC is very expensive oer area and next generations are
supposed to be even lower RdsOn and smaller die.

So, WHY even put those tiny die into a TO-247 package ? I don't think
that huge (relative) package would be any better than say, a TO-220
package ? I don't thin that the Rth J-C would be much worse if at all
different for what I saw in your picture.
We use D-Squared SiC packages and the die size is just slightly larger
(I thiink) than in your picture of the TO-247 Cree package.

Hopefully, eventually the price of the die/wafer will be low enough
where we can choose to have a larger die with super low RdsOn and Rth
J-C wihtout spending $1000 per part.

[John Larkin]

The TO247 for that tiny chip is kind of silly. It does get some modest
benefit from lateral heat spreading, with all that copper. I'm spacing
it off a water-cooled block with an aluminum nitride insulator. I'm
using a TO220 sized insulator, to keep the capacitance down, so the
package may as well be TO220 size too. They maybe went with TO247 to
get the clearances for 1200 volts.

There are some 1200 volt mosfets in dpaks and some 1500 volt d2paks.

[John Miles, KE5FX]

On Sunday, January 13, 2019 at 7:56:01 AM UTC-8, John Larkin wrote:
>
> Is that a TDR derived from a VNA frequency sweep? The right side isn't
> the same RC tau that I see; what was your sweep range?

Yes, it's an HP 8510C configured for 801 points at N x 62.4 MHz. The
vertical scale should be the same as yours, at 200 milli-rhos or whatever
per division.

One drawback with simulated TDR is that large near-end responses tend to
degrade the fidelity of later responses. The RC part of the curve might be
getting hosed by that phenomenon.

Are you using an SD-32 or SD-24 head?

> TDR is DC!

In lowpass mode the VNA has to extrapolate down to DC when it does the math,
so there's room for error there. And calibrating in SMA to 50 GHz is an
exercise in wishful thinking.

The plots I get out of this setup are probably comparable to what you'd get
from a properly calibrated 20 GHz rig plus some fine-structure details that
might or might not actually be there. That's why I thought it would be
worthwhile to compare it to a real sampler (which I don't have).

The interesting part to me was the pair of closely-spaced inductive responses
near the package boundary. Those are a pretty good match considering how
different the instruments are.

> Those Cree fets are great, but they do need a lot of gate drive.

I have a Peak Atlas pocket-size component analyzer that's pretty hard to
fool, but it only saw the body diode.

-- john, KE5FX

[John Larkin]

On Sun, 13 Jan 2019 14:52:35 -0800 (PST), "John Miles, KE5FX"
<jmi...@gmail.com> wrote:

>On Sunday, January 13, 2019 at 7:56:01 AM UTC-8, John Larkin wrote:
>>
>> Is that a TDR derived from a VNA frequency sweep? The right side isn't
>> the same RC tau that I see; what was your sweep range?
>
>Yes, it's an HP 8510C configured for 801 points at N x 62.4 MHz. The
>vertical scale should be the same as yours, at 200 milli-rhos or whatever
>per division.
>
>One drawback with simulated TDR is that large near-end responses tend to
>degrade the fidelity of later responses. The RC part of the curve might be
>getting hosed by that phenomenon.

Any TDR has that problem. Every feature distorts the step and
reflection of downstream stuff.

>
>Are you using an SD-32 or SD-24 head?

11802 and SD24.

>
>> TDR is DC!
>
>In lowpass mode the VNA has to extrapolate down to DC when it does the math,
>so there's room for error there. And calibrating in SMA to 50 GHz is an
>exercise in wishful thinking.
>
>The plots I get out of this setup are probably comparable to what you'd get
>from a properly calibrated 20 GHz rig plus some fine-structure details that
>might or might not actually be there. That's why I thought it would be
>worthwhile to compare it to a real sampler (which I don't have).
>
>The interesting part to me was the pair of closely-spaced inductive responses
>near the package boundary. Those are a pretty good match considering how
>different the instruments are.

The big difference is the slow, gross gate capacitance, because of the
limited low frequency span of the VNA. But we can measure that other
ways, so it's OK.

>
>> Those Cree fets are great, but they do need a lot of gate drive.
>
>I have a Peak Atlas pocket-size component analyzer that's pretty hard to
>fool, but it only saw the body diode.

The body diode on the Cree fets is terrible, and their Spice model
doesn't suggest how terrible.



>
>-- john, KE5FX

[Tim Williams]

"boB" <b...@K7IQ.com> wrote in message
news:apvm3edtmkllnldf2...@4ax.com...

> So, WHY even put those tiny die into a TO-247 package ? I don't think
> that huge (relative) package would be any better than say, a TO-220
> package ? I don't thin that the Rth J-C would be much worse if at all
> different for what I saw in your picture.

1. Better RthCH given typical TIMs?
2. Voltage rating (creepage). Not conclusive because there are packages
with extra molding around leads, but I also don't know how available those
are -- seems like I've only seen them from JP brands?
3. Expectation? Engineers are still human, who knows...

Doesn't make much difference in stray inductance anyway; the leads are
further apart but also thicker.


Also, why not D[N]PAK? Creepage is plenty, and with efficiency taking
priority in many applications, heat dissipation of a THT part isn't needed.

I'd like a SMA sized SiC schottky, which would only be good for a few 100
mA, but alas the closest thing that exists is $20, what a joke.

Makes miniaturizing circuitry really hard, especially when you need a small
snubber, or a high voltage output. Sigh...