<
jjla...@highlandtechnology.com> wrote:
>On Fri, 12 Aug 2022 20:28:14 -0400, legg <
le...@nospam.magma.ca> wrote:
>
>>On Fri, 12 Aug 2022 12:47:59 -0700, John Larkin
>><
jjla...@highlandtechnology.com> wrote:
>>
>>>I figured that I could bootstrap an LT Spice sample/hold to make a
>>>stairstep waveform.
>>>
>>>Without the RC, the output jumps to +10 volts at the first clock edge.
>>>And the RC has to be right to get a proper stairstep.
>>>
>>
>>So it works with the RC - suggests a linear condition is
>>permitted at the sampling time. Perhaps the internal
>>gates aren't timed to prevent signal shoot-through.
>>
>>RL
>
>I can't understand it. Even 1K and 1 fF allows it to make a staircase.
>But 1K and 0 fF doesn't.
>
>Obviously something is goofy inside the s/h model, but I wouldn't know
>how to accomplish that.
>
>I can do what I want to do, by adding an RC, but I don't understand
>it.
each side of the resistor. This shouldn't normally 'break' a S/H,