lørdag den 22. januar 2022 kl. 04.28.58 UTC+1 skrev
gnuarm.del...@gmail.com:
> On Friday, January 21, 2022 at 6:42:00 AM UTC-5,
lang...@fonz.dk wrote:
> > fredag den 21. januar 2022 kl. 03.08.06 UTC+1 skrev
jla...@highlandsniptechnology.com:
> > > On Thu, 20 Jan 2022 11:51:16 -0800 (PST), Lasse Langwadt Christensen
> > > <
lang...@fonz.dk> wrote:
> > >
> > > >torsdag den 20. januar 2022 kl. 17.31.18 UTC+1 skrev
jla...@highlandsniptechnology.com:
> > > >> This uses an FPGA LVDS input as a comparator, and one external RC, to
> > > >> make an ADC. Just need an algorithm to process the flop output.
> > > >>
> > > >> A simpler ADC should be possible.
> > > >>
> > > >
> > > >more than one way to do it, one is basically successive approximation with a pwm dac
> > > >another is delta-sigma with RC as "integrator" that might have an advantage in that the
> > > >comparator doesn't follow the input signal it is always ~1/2 Vcc
> > > That's certainly better; the FPGA LVDS receivers are mediocre
> > > comparators. But the game was to minimize the number of external
> > > parts. I'll be digitizing a thermistor on a heat sink, so it's not a
> > > precision thing.
> > >
> > > If we go with an available Lattice FPGA, it doesn't have an ADC.
> > >
> > > Some sort of delta-sigma signal processing would be interesting.
> > >
> > > I could use an LM71, SPI temp sensor, which is just not as
> > > interesting.
> > even simpler tmp05/tmp06 which is pwm output so all you need is a counter in the fpga
> >
> > or for easy mounting on a heat sink,
https://dk.farnell.com/smartec/smt172-220/temperature-sensor-1deg-c-to-220/dp/2543396
> Isn't the FPGA the place where you put arbitrarily complex logic? Why try to minimize it?
why spend time to implement a SPI, use three/four pins, or logic and extra parts to fudge an ADC and calibrate that
when you can get a calibrated part that only need a single pin and very simple logic