yeah...@gmail.com wrote:
> hello!
> I am working on DPLL,CSVCO is a part of this,i need help how to
> determine the phase noise of that VCO with LTSPICE
Simulations normally start with Leeson's equation:
http://en.wikipedia.org/wiki/Leeson%27s_equation
If you use a varactor, you need to add Rohde's extension. There are many
references, for example see page 9 of
<
https://www-docs.tu-
cottbus.de/mikrowellentechnik/public/rohde/rohde2011ulr_habil_presentatio
n.pdf>
You will find many examples of simulations that supposedly match the
actual phase noise very closely. But the simulations require major
assumptions that are not disclosed in the articles.
If you examine the operation of an oscillator carefully, you will
notice it can have large variations in performance with relatively
small changes in operating parameters.
For example, changing the ratio of the feedback capacitors in the
base-emitter-ground connection of a common collector Colpitts can
have huge effects on the output amplitude and conduction angle. But
there is no place in Leeson's equation that describes this. So I
have serious doubts about the validity of the simulations.
I would rather start with Hajimiri's article on the Theory of Phase
Noise in Electrical Oscillators, with particular reference to Figure
4 a and b in
http://authors.library.caltech.edu/4917/1/HAJieeejssc98.pdf
For an alternate view, consider Leif Asbrink's approach that gives
phase noise similar to the best oscillators by Wenzel Associates,
down to -180dBc/Hz at 20 kHz using the cheapest possible standard
crystals at 14 MHz:
http://www.sm5bsz.com/osc/newref.htm
Considering these radically different approaches can give excellent
results, but cannot be described explicitly in Leeson's equations.
For this reason, I would not waste time trying to simulate the
oscillator. You have no way to tell if the simulation is accurate or
meaningful unless you build the circuit and measure it.
To measure the phase noise, I would make a simple phase noise test
set using the balanced bridge phase detector approach in the HP
E5500 series equipment, and measure the actual performance of the
oscillator. You are going to need it anyway, so might as well start
there.
However, if you are working on a Digital Phase Locked Loop (DPLL),
it can have large phase offset errors due to the descrete timing
available in the time-to-digital converter at the input to the loop.
In this case, the oscillator phase noise may be an insignificant
part of the overall loop error, and the effort to measure or improve
the phase noise may be swamped by the effort required to reduce the
digitizing error.
You can see some of these effects in
http://www.cppsim.com/PLL_Lectures/digital_pll_cicc_tutorial_perrott.pdf
In addition, if you are using an RC oscillator, you can experience
severe limit cycle oscillations due to crosstalk from the digital
noise into the vco. The same problem can occur in the time-to-digital
converter.
These are further examples of why it is far better to spend your
time on the bench, looking at actual results rather than trying to
simulate something that has no relation to reality.