Avoiding PFD dead-zone in phase locked loop design
Matt Koepnick
In a number of app notes I've been reading, the article by Allen Hill
and Jim Surber called "The PLL Dead Zone and How to Avoid It," in the
March 1992 RF Design, is referenced. I've been unable to find a good
description/schematic of the circuit that Hill and Surber published,
which apparently combines the standard type-4 PFD with an XOR gate to
eliminate the dead zone.
I'd appreciate it if anyone has information on this circuit and/or can
point me to a good reference..
Cheers,
Matt
John Larkin
wrote:
Matt,
take a look at the Analog Devices AD9901 datasheet. It works this way.
I've used it at 77 MHz and got jitter in the 2 ps RMS range. The
output waveforms are really grotesque, but it works!
John
Phil Hobbs
Depending on what frequency you're using, you can also take a 4046-type
frequency-phase detector and put a large-value load resistor from the PD II output to
ground. This will move the operating point far enough from 0 degrees to get you out
of the dead zone.
After all, small dead zones are only a problem if that's where your loop winds up
operating.
Cheers,
Phil Hobbs
Bill Sloman
The Philips data sheet for their 74HCT9046
http://www.semiconductors.philips.com/acrobat/datasheets/74HCT9046A_3.pdf
contains a nice discussion of the dead zone in the digital phase
detector in the 4046, and describes how they eliminated it in the
9046, in a rather simpler way, by making sure that raise frequency
current source and the lower frequency current source a both on
(briefly) if the phase shift is zero. Cheaper than the AD9901, if not
as fast.
I'd be tempted to implement their approach in fast logic if I wanted
something faster than the AD9901 (which worked fine for me at 50MHz).
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Bill Sloman, Nijmegen