Advantages of negative logic?
Michael Schupbach
have a professor who is talking about reducing power surges through
the transformer and power supply and reducing magnetic fields and some
other far-fetched sounding stuff.
I was under the impression that most transistors can sink more than
they can source and that transistors spend more of their time in the
"off" state.
Any input welcome.
Thank you,
Michael Schupbach
Lord Garth
"Michael Schupbach" <gmsch...@earthlink.net> wrote in message
news:55fb3fe4.0305...@posting.google.com...
Negative logic is, at times, advantageous in minimizing the hardware
required to
perform a desired function.
Chuck Simmons
>
> What are the advantages of using negative logic in circuit design? I
> have a professor who is talking about reducing power surges through
> the transformer and power supply and reducing magnetic fields and some
> other far-fetched sounding stuff.
Not very useful information really. Take the case of CML (ECL) which was
common from the 1960s on. It has nearly constant current flow regardless
of state. CMOS, starting in the early 1970s, enjoys much the same
property. I might point out that one occasionally sees CML implemented
in CMOS chips for PECL outputs (used to drive balanced lines) and other
purposes.
The real reasons behind negative logic are several. The simplest gates
are inverting. There is a natural tendency for "and" and "or" functions
to alternate. Precharged buses in older MOS processes were negative.
Open drains can be "wire ored." There are other reasons.
> I was under the impression that most transistors can sink more than
> they can source and that transistors spend more of their time in the
> "off" state.
Much of the logic today has "totem pole" or complemetary symmetry
outputs. TTL and variants can usually sink considerably more than they
can source. CMOS outputs are more balanced normally and are sometimes
scaled so that source and sink are equal.
I can tell you that in over 35 years of using integrated logic, I have
used many many more 7400s than 7408s. Try to build a 2 to 1 mux with a
single 7408 (quad positive "and" gate) and no other chips.
Chuck
--
... The times have been,
That, when the brains were out,
the man would die. ... Macbeth
Chuck Simmons chr...@webaccess.net
Marc H.Popek
and still be right 50% of the time ;~)
Live from Las Vegas
"Michael Schupbach" <gmsch...@earthlink.net> wrote in message
news:55fb3fe4.0305...@posting.google.com...
Paul Burke
>
> What are the advantages of using negative logic in circuit design? I
> have a professor who is talking about reducing power surges through
> the transformer and power supply and reducing magnetic fields and some
> other far-fetched sounding stuff.
>
> I was under the impression that most transistors can sink more than
> they can source and that transistors spend more of their time in the
> "off" state.
>
Taters and tripe! You can't know a priori (*) what logic functions are
going to be, so you can't predict what the outputs are going to be. I
suspect that most microprcessor control functions (like chip selects,
RD/WR etc.) were selected that way because in the days of NMOS they
resulted in fewer active outputs, and that they have been kept since for
compatiblity, new designs following older ones for the sake of available
peripherals and logc functions.
In passing, why did Atmel make the resets on the little AVRs active
high, when active low would have made them pin compatible with 89C2051s?
Paul Burke
Tilmann Reh
> In passing, why did Atmel make the resets on the little AVRs active
> high, when active low would have made them pin compatible with 89C2051s?
Its vice versa.
Finally, opposed to all "standard" 8051 derivatives, finally there
are some with active-low resets (which is much more convenient).
--
Dipl.-Ing. Tilmann Reh
Autometer GmbH Siegen - Elektronik nach Maß.
http://www.autometer.de
==================================================================
In a world without walls and fences, who needs Windows and Gates ?
(Sun Microsystems)
James Meyer
>In passing, why did Atmel make the resets on the little AVRs active
>high, when active low would have made them pin compatible with 89C2051s?
>
>Paul Burke
If it were active low, it wouldn't be a reset pin any longer, it would
be a /reset or reset-bar pin.
Jim
Fred Bloggs
> What are the advantages of using negative logic in circuit design? I
> have a professor who is talking about reducing power surges through
> the transformer and power supply and reducing magnetic fields and some
> other far-fetched sounding stuff.
>
> I was under the impression that most transistors can sink more than
> they can source and that transistors spend more of their time in the
> "off" state.
>
First of all, the term "negative logic" is terminology that is
conventionally used to describe the assignment of Boolean algebraic
states to the actual hardware implementation. Boolean algebra works with
the two states of True and False and the various operators on these
states. All of this is developed independently of the particular
physical means used to realize these operations, and the assignment of
True and False to the actual physical hardware states is completely
arbitrary. In the case of modern integrated circuit " digital "
circuits, "negative logic" has come to mean that the assignment is
True-> low voltage level and False-> high voltage level, whereas
"positive logic" means True-> high voltage and False->low voltage level.
The particular assignment used is the decision of the designer, does not
have to remain constant from one part of the circuit to the other, and
is generally based on considerations of component count, speed, and type
of hardware family used, as well as possibly I/O constraints set
beforehand. Any of the digital circuit families can be used to implement
either of the negative/postive logic designs. For example, the standard
TTL AND gate like the 7408 can be considered as a positive logic AND or
a negative logic OR, and the 7432 can be considered a positive logic OR
or a negative logic AND. This is evident from the truth tables like so:
View in a fixed-width font such as Courier.
TTL 7408
____
A---| \
| |__ Y
| |
B---|____/
Physical Voltage Positive Logic Negative Logic
Function: Assignments: Assignments:
L= voltage <0.8V True=H True=L
H= voltage >2.2V False=L False=H
PHYSICAL I/O BOOLEAN AND BOOLEAN OR
FUNCTION TABLE: LOGIC FUNCTION LOGIC FUNCTION
A B | Y A B | Y A B | Y
--------+--- --------+--- --------+---
L L | L F F | F T T | T
| | |
L H | L F T | F T F | T
| | |
H L | L T F | F F T | T
| | |
H H | H T T | T F F | F
GregS
>What are the advantages of using negative logic in circuit design? I
>have a professor who is talking about reducing power surges through
Almost all external lines were always negative logic. Maybe not now,
but they were. I always thought is was for noise control, but TTL near ground
is rather iffy.
greg
Michael A. Covington
large IC that are normally off, less total power is consumed, because TTL
inputs source current when pulled low.
With CMOS this doesn't apply.
I don't understand the other stuff. With CMOS, exactly half of the
transistors are "on" and the other half are "off" regardless of state.
"Michael Schupbach" <gmsch...@earthlink.net> wrote in message
news:55fb3fe4.0305...@posting.google.com...
Tim Shoppa
> Michael Schupbach wrote:
> >
> > What are the advantages of using negative logic in circuit design? I
> > have a professor who is talking about reducing power surges through
> > the transformer and power supply and reducing magnetic fields and some
> > other far-fetched sounding stuff.
> >
> > I was under the impression that most transistors can sink more than
> > they can source and that transistors spend more of their time in the
> > "off" state.
> >
>
> Taters and tripe! You can't know a priori (*) what logic functions are
> going to be, so you can't predict what the outputs are going to be. I
> suspect that most microprcessor control functions (like chip selects,
> RD/WR etc.) were selected that way because in the days of NMOS they
> resulted in fewer active outputs, and that they have been kept since for
> compatiblity, new designs following older ones for the sake of available
> peripherals and logc functions.
On the other hand the bulk of the 4000-series CMOS chips were designed
around "positive logic", i.e. chip selects and enables are active high.
There are a few microprocessor families that followed this road from the
very beginning. (RCA 1802, Motorola MC14500B, ...)
> In passing, why did Atmel make the resets on the little AVRs active
> high, when active low would have made them pin compatible with 89C2051s?
I try to be polarity-agnostic, but for master resets I also feel that active low
makes more sense. That way your master reset can be low and stay low until
all your supplies are stable, then you raise it. Raising master reset
high when the supplies aren't up yet can be a little tricky... leading to
all those Supervisor IC's.
Maybe it's a marketing decision rather than a engineering decision. After
all, if you want to sell more Supervisor IC's, you do it by making master
reset tricky, which means you make it active high :-)
Tim.
Keith R. Williams
says...
1) TTL has a stronger negative drive, so it switches faster
'1' -> '0'. This is the primary reason TTL CS and OE signals
are negative active.
TTL negative logic is faster. ECL has a stronger drive in the
positive direction, so transitions are faster in the opposite
direction. CMOS doesn't care much, but it's more or less
a TTL replacement so kept the baggage from past evils.
2) The standard TTL gate inverts, so an "AND" gate has more delay
than a NAND. TTL inverting logic is faster. ECL is essentially
a diff-amp, so both phases are available. The negative active
output is usually slightly faster since it is on the same
side of the current switch as the input. This is offset some by #1.
CMOS is similar to TTL here.
3) Since most logic families aren't exactly symmetrical, if one
uses exclusively positive logic the delay difference between
transitions will accumulate causing pulse-shrinkage. Using
inverters in each stage causes the delays differences "come
out in the wash". Pulse-shrinkage = slower. Using negative
logic allows higher speed. This is true of all families
to differing extents.
4) Negative logic is for real engineers. It confuses the PHBs. ;-)
--
Keith
Spehro Pefhany
(Tim Shoppa) wrote:
>I try to be polarity-agnostic, but for master resets I also feel that active low
>makes more sense. That way your master reset can be low and stay low until
>all your supplies are stable, then you raise it. Raising master reset
>high when the supplies aren't up yet can be a little tricky... leading to
>all those Supervisor IC's.
>
>Maybe it's a marketing decision rather than a engineering decision. After
>all, if you want to sell more Supervisor IC's, you do it by making master
>reset tricky, which means you make it active high :-)
I don't see it as any easier or harder to make it active low vs.
active high. Unless there is some gotcha on threshold control over
p-channel vs. n-channel devices. The guarantee of the active low
devices typically extends only to about 1V Vdd, which is getting
pretty close to normal operating voltage for some chips. If the chip
being supervised (and particularly if it has persistent SRAM or
EEPROM) is not guaranteed *not* to work, with margin, below the
guaranteed voltage that the reset chip functions at, you have a
potentially serious problem.
One common use these days for negative logic is wired-OR (really
wired-AND in positive logic)- often used for /RESET and /IRQ lines.
Best regards,
Spehro Pefhany
--
"it's the network..." "The Journey is the reward"
sp...@interlog.com Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog Info for designers: http://www.speff.com
Spehro Pefhany
<k...@attglobal.net> wrote:
<snip>
> TTL negative logic is faster. ECL has a stronger drive in the
> positive direction, so transitions are faster in the opposite
> direction. CMOS doesn't care much, but it's more or less
> a TTL replacement so kept the baggage from past evils.
CMOS is also better pulling down because of higher carrier mobility in
the n-channel devices, and of course 74HC and other families inherited
the TTL functions. But the 4000 series CMOS tended to use +ve logic
anyway, and when they didn't they *named* the pins using positive
logic (inhibit rather than /enable).
>4) Negative logic is for real engineers. It confuses the PHBs. ;-)
Always a good feature.
Mario Klebsch
>In passing, why did Atmel make the resets on the little AVRs active
>high, when active low would have made them pin compatible with 89C2051s?
The 8051 parts do have a high active reset. I always wondered why,
because there are not too much reset generators, that can deliver high
active resets.
73, Mario
--
Mario Klebsch ma...@klebsch.de
PGP-Key available at http://www.klebsch.de/public.key
Fingerprint DSS: EE7C DBCC D9C8 5DC1 D4DB 1483 30CE 9FB2 A047 9CE0
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Tim Hubberstey
>
> In article <b9tf07$ru0$1...@usenet01.srv.cis.pitt.edu>, szek...@pitt.edu
> says...
> > In article <55fb3fe4.0305...@posting.google.com>, gmsch...@earthlink.net (Michael Schupbach) wrote:
> > >What are the advantages of using negative logic in circuit design? I
> > >have a professor who is talking about reducing power surges through
> >
> > Almost all external lines were always negative logic. Maybe not now,
> > but they were. I always thought is was for noise control, but TTL near ground
> > is rather iffy.
>
> 1) TTL has a stronger negative drive, so it switches faster
> '1' -> '0'. This is the primary reason TTL CS and OE signals
> are negative active.
While this is true, it doesn't explain why write enables are also almost
always active low since the slower 0->1 transition is detrimental in
this case.
I was always told that the primary reason is because active-low TTL
signals have better noise margin when inactive. If the "off" state is
low, you need less than 0.8 V of noise to kick the signal into the
undefined region whereas when "off" is high (~3.4V) you need 1.4V of
noise to move into the undefined region.
>4) Negative logic is for real engineers. It confuses the PHBs. ;-)
It also lets you confuse newbies by engaging in "bubble pushing"
(re-drawing gates using DeMorgan's Theorem) on your schematics. ;-)
Unfortunately, this practice seems to have dropped out of favor since
the advent of CAD.
5) Power dissipation is significantly lower (usually by about 3x) with
the output of a simple TTL gate high than when it's low.
--
Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com
John Eaton
: Michael Schupbach wrote:
:>
:> What are the advantages of using negative logic in circuit design? I
:> have a professor who is talking about reducing power surges through
:> the transformer and power supply and reducing magnetic fields and some
:> other far-fetched sounding stuff.
A TTL receiver had to interrpert anything above 2.0 v as a one and anything
below .8 v as a zero. A TTL transmitter had to drive .4 v or below for a
zero and 2.4 v or above for a one.
This meant that you had more noise margin when driving a one than you did
a zero. The lowest you could possibly drive a zero was only .8 v from the
switching threshold, the highest you could drive a one was 5 volts which
was 2.6 v from the high threshold.
So if you had a signal like an async write strobe to a ram then it was prudent
to make it active low and reduce the chances that a random 1 v noise glitch
would trigger a write.
John Eaton
Jem Berkes
>
> It also lets you confuse newbies by engaging in "bubble pushing"
> (re-drawing gates using DeMorgan's Theorem) on your schematics. ;-)
> Unfortunately, this practice seems to have dropped out of favor since
> the advent of CAD.
What is a PHB?
By the way, I'm a 4th year undergrad EE student and at my university we've
done plenty of that bubble pushing you're talking about. I recall that one
of the exam questions I saw recently was tweaking a logic design so that it
was possible to implement using only NANDs, NORs and the like.
--
Jem Berkes
http://www.pc-tools.net/
Windows, Linux & UNIX software
Jim Thompson
wrote:
Absolutely! All the other "answers" in this thread are BS. "Negative
logic" is just a thinking pattern which minimizes the number of
gates... you can switch back and forth as the hardware drives you ;-)
...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice:(480)460-2350 | |
| Jim-T@analog_innovations.com Fax:(480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |
For proper E-mail replies SWAP "-" and "_"
"My problem with 'old Europe' is that it's taken on the
characteristic of its capital's most famous statue: a
small boy who just stands there pissing 24 hours a day."
- Mark Steyn
Keith R. Williams
sp...@interlog.com says...
> On Wed, 14 May 2003 11:42:56 -0400, the renowned Keith R. Williams
> <k...@attglobal.net> wrote:
> <snip>
> > TTL negative logic is faster. ECL has a stronger drive in the
> > positive direction, so transitions are faster in the opposite
> > direction. CMOS doesn't care much, but it's more or less
> > a TTL replacement so kept the baggage from past evils.
> <snip>
>
> CMOS is also better pulling down because of higher carrier mobility in
> the n-channel devices, and of course 74HC and other families inherited
> the TTL functions.
I'm no device physics type, but it's my understanding that the
improved mobility of the n-devices is in the choice of the
crystalline structure. One could make the P-device (hole
mobility) better by aligning the crystal in another plane. This
is just from some lectures I half understood though.
> But the 4000 series CMOS tended to use +ve logic
> anyway, and when they didn't they *named* the pins using positive
> logic (inhibit rather than /enable).
I got bit by this with the Xilinx IOBs too. Who woulda think the
OE's were really OUTPUT ENABLE, rather than Tri-State-Enables?
Sheesh! BTW, I'm not the only one.
>
> >4) Negative logic is for real engineers. It confuses the PHBs. ;-)
>
> Always a good feature.
Keep 'em surprised.
--
Keith
Keith R. Williams
j...@users.pc9.org says...
> >>4) Negative logic is for real engineers. It confuses the PHBs. ;-)
> >
> > It also lets you confuse newbies by engaging in "bubble pushing"
> > (re-drawing gates using DeMorgan's Theorem) on your schematics. ;-)
> > Unfortunately, this practice seems to have dropped out of favor since
> > the advent of CAD.
>
> What is a PHB?
Pointy-haired-boss (think Dilbert).
> By the way, I'm a 4th year undergrad EE student and at my university we've
> done plenty of that bubble pushing you're talking about. I recall that one
> of the exam questions I saw recently was tweaking a logic design so that it
> was possible to implement using only NANDs, NORs and the like.
That's a useful exercise, once. Optomizing for speed gets much
more interesting.
--
Keith
Keith R. Williams
> "Keith R. Williams" wrote:
> >
> > In article <b9tf07$ru0$1...@usenet01.srv.cis.pitt.edu>, szek...@pitt.edu
> > says...
> > > In article <55fb3fe4.0305...@posting.google.com>, gmsch...@earthlink.net (Michael Schupbach) wrote:
> > > >What are the advantages of using negative logic in circuit design? I
> > > >have a professor who is talking about reducing power surges through
> > >
> > > Almost all external lines were always negative logic. Maybe not now,
> > > but they were. I always thought is was for noise control, but TTL near ground
> > > is rather iffy.
> >
> > 1) TTL has a stronger negative drive, so it switches faster
> > '1' -> '0'. This is the primary reason TTL CS and OE signals
> > are negative active.
>
> While this is true, it doesn't explain why write enables are also almost
> always active low since the slower 0->1 transition is detrimental in
> this case.
Almost always? I've never seen this to be the case. OTOH, bus
OE# always favor the negative.
> I was always told that the primary reason is because active-low TTL
> signals have better noise margin when inactive. If the "off" state is
> low, you need less than 0.8 V of noise to kick the signal into the
> undefined region whereas when "off" is high (~3.4V) you need 1.4V of
> noise to move into the undefined region.
I dont buy it. The nominal threshold for TTL is ~1.4V. The
minimum input high level is 2.0V and (input) low level is .8V.
This is pretty symmetrical. The fact is that TTL has a much
lower output impedance in the low level helps the noise margin in
the low level.
> >4) Negative logic is for real engineers. It confuses the PHBs. ;-)
>
> It also lets you confuse newbies by engaging in "bubble pushing"
> (re-drawing gates using DeMorgan's Theorem) on your schematics. ;-)
> Unfortunately, this practice seems to have dropped out of favor since
> the advent of CAD.
CAD? How about synthesis?
Amazing. We were going through a design trying to figure out why
some test cases weren't being hit. Well, it's pretty tough to
get a gate excited when it's input is a and /a. Synthesis.
>
> 5) Power dissipation is significantly lower (usually by about 3x) with
> the output of a simple TTL gate high than when it's low.
...don't buy it. You're going to have to show me. AFAIK this
depends on the output loading. The input and bias currents are
pretty much the same in either state.
--
Keith
Chuck Simmons
>
> In article <r1u4cv4caid3ko5u1...@4ax.com>,
> sp...@interlog.com says...
> > On Wed, 14 May 2003 11:42:56 -0400, the renowned Keith R. Williams
> > <k...@attglobal.net> wrote:
> > <snip>
> > > TTL negative logic is faster. ECL has a stronger drive in the
> > > positive direction, so transitions are faster in the opposite
> > > direction. CMOS doesn't care much, but it's more or less
> > > a TTL replacement so kept the baggage from past evils.
> > <snip>
> >
> > CMOS is also better pulling down because of higher carrier mobility in
> > the n-channel devices, and of course 74HC and other families inherited
> > the TTL functions.
>
> I'm no device physics type, but it's my understanding that the
> improved mobility of the n-devices is in the choice of the
> crystalline structure. One could make the P-device (hole
> mobility) better by aligning the crystal in another plane. This
> is just from some lectures I half understood though.
This reminds me of the time I got dragged from my servo world to look at
a chip driving a transmission line through a series termination. I
concluded that the CMOS up driver was weak and that they should try a 2X
for that transistor. There was great nervousness about that and they
finally scaled up both the up driver and the down driver. I sort of
mouthed "oh sh*t." The parts from the fab were better but I stand by the
"oh sh*t." There was still a glitch.
Chuck Simmons
>
> > 5) Power dissipation is significantly lower (usually by about 3x) with
> > the output of a simple TTL gate high than when it's low.
>
> ...don't buy it. You're going to have to show me. AFAIK this
> depends on the output loading. The input and bias currents are
> pretty much the same in either state.
I don't buy it either but in any complicated logic system doing anything
worth while, the internal states are all over the map. It makes no
difference whether negative or positive logic. Since there is generally
a mix of both, it is hard to see that favoring negative over positive
logic will make much difference to power even if gates have some
unlikely property.
Paul Burke
>
> Paul Burke schrieb:
>
> > In passing, why did Atmel make the resets on the little AVRs active
> > high, when active low would have made them pin compatible with 89C2051s?
>
> Its vice versa.
>
Yes, of course it is. But why sacrifice the drop-in compatibility?
Paul Burke
Tim Hubberstey
>
> In article <3EC2C544...@no.spam>, sen...@no.spam says...
> > "Keith R. Williams" wrote:
> > >
> > > In article <b9tf07$ru0$1...@usenet01.srv.cis.pitt.edu>, szek...@pitt.edu
> > > says...
> > > > In article <55fb3fe4.0305...@posting.google.com>, gmsch...@earthlink.net (Michael Schupbach) wrote:
> > > > >What are the advantages of using negative logic in circuit design? I
> > > > >have a professor who is talking about reducing power surges through
> > > >
> > > > Almost all external lines were always negative logic. Maybe not now,
> > > > but they were. I always thought is was for noise control, but TTL near ground
> > > > is rather iffy.
> > >
> > > 1) TTL has a stronger negative drive, so it switches faster
> > > '1' -> '0'. This is the primary reason TTL CS and OE signals
> > > are negative active.
> >
> > While this is true, it doesn't explain why write enables are also almost
> > always active low since the slower 0->1 transition is detrimental in
> > this case.
>
> Almost always? I've never seen this to be the case. OTOH, bus
> OE# always favor the negative.
Show me ANY RAM from the TTL era that uses an active high write enable.
For that matter, try to find a RAM even now that uses active high write
enables.
> > I was always told that the primary reason is because active-low TTL
> > signals have better noise margin when inactive. If the "off" state is
> > low, you need less than 0.8 V of noise to kick the signal into the
> > undefined region whereas when "off" is high (~3.4V) you need 1.4V of
> > noise to move into the undefined region.
>
> I dont buy it. The nominal threshold for TTL is ~1.4V. The
> minimum input high level is 2.0V and (input) low level is .8V.
> This is pretty symmetrical. The fact is that TTL has a much
> lower output impedance in the low level helps the noise margin in
> the low level.
Even if you use a 1.4 V switching threshold, you still get 2.0 V margin
on a high (3.4 V typical high output) vs a 1.2 V margin on low (0.2 V
typical low output). Numbers are from the 7400 data sheet. Yes, the
output impedance is higher in '1' state but is it enough higher to
offset the almost 2:1 difference in noise margin? I don't know for sure
but I suspect the margin is still higher in the 1 state.
> > 5) Power dissipation is significantly lower (usually by about 3x) with
> > the output of a simple TTL gate high than when it's low.
>
> ...don't buy it. You're going to have to show me. AFAIK this
> depends on the output loading. The input and bias currents are
> pretty much the same in either state.
Look at the data sheet for a 7400. Current consumption is listed as 8
mA/gate with inputs low (output high) and 22 mA/gate with inputs high.
Also, input currents are very definitely not the same. All TTL families
require more current to drive an input low than to drive it high.
Usually several times more (1.6 mA low, 40 uA high for 7400).
Notice that we're talking about the original 7400 series gates here, not
recent TTL-compatible CMOS versions. The active low decisions were made
for this family and all follow-ons simply complied with the established
standard. The 7400 series may even have been following standards
established by DTL or RTL but since I haven't used those families, I
don't really know much about them.
Fred Bloggs
Keith R. Williams wrote:
>
>
> 1) TTL has a stronger negative drive, so it switches faster
> '1' -> '0'.
Hmmm...I am not so sure that the "stronger" drive level is responsible
for this so much as the L->H transition is impaired by the storage delay
of the saturated totem pole pull down transistor, which is not the case
in the H->L transition. The pullup drive was strong enough because of
the 40:1 reduction in loading which resulted from the fundamental
multi-emitter common base inputs.
>This is the primary reason TTL CS and OE signals
> are negative active.
Hmmm...I wonder about that assertion. It would seem to me that this
accident of polarity is more the result of the fact that the fundamental
subcircuit structure of the logic family is the buffered inverter, the
IC enable/select type inputs were routed to a multitude of internal chip
gates, and smart logic family design would require that all inputs be
buffered- present a unit load to the external world.
None of this has anything to do with the fundamental misunderstanding of
what exactly negative/positive logic actually means.
Keith R. Williams
>
>
> Keith R. Williams wrote:
>
> >
> >
> > 1) TTL has a stronger negative drive, so it switches faster
> > '1' -> '0'.
>
> Hmmm...I am not so sure that the "stronger" drive level is responsible
> for this so much as the L->H transition is impaired by the storage delay
> of the saturated totem pole pull down transistor, which is not the case
> in the H->L transition. The pullup drive was strong enough because of
> the 40:1 reduction in loading which resulted from the fundamental
> multi-emitter common base inputs.
Sure, the original TTL driver could sink 16mA (ten 1.6mA inputs), but
only source a few (1.6mA comes to mind). The saturated NPN in the low
level is much stronger than the current limited (TTL was designed not
to self-destruct if the outputs were tied together) emitter follower-
diode pullup.
> >This is the primary reason TTL CS and OE signals
> > are negative active.
> Hmmm...I wonder about that assertion. It would seem to me that this
> accident of polarity is more the result of the fact that the fundamental
> subcircuit structure of the logic family is the buffered inverter, the
> IC enable/select type inputs were routed to a multitude of internal chip
> gates, and smart logic family design would require that all inputs be
> buffered- present a unit load to the external world.
Nope. Negative active enables (and data on some) made switching
heavily loaded/capacitive busses faster.
> None of this has anything to do with the fundamental misunderstanding of
> what exactly negative/positive logic actually means.
Not directly, no. However, one tends to use what the technology is good
at doing and avoid what it's not.
--
Keith
Fred Bloggs
Keith R. Williams wrote:
> In article <3EC3872F...@nospam.com>, nos...@nospam.com says...
>
>>
>>Keith R. Williams wrote:
>>
>>
>>>
>>>1) TTL has a stronger negative drive, so it switches faster
>>> '1' -> '0'.
>>
>>Hmmm...I am not so sure that the "stronger" drive level is responsible
>>for this so much as the L->H transition is impaired by the storage delay
>>of the saturated totem pole pull down transistor, which is not the case
>>in the H->L transition. The pullup drive was strong enough because of
>>the 40:1 reduction in loading which resulted from the fundamental
>>multi-emitter common base inputs.
>
>
> Sure, the original TTL driver could sink 16mA (ten 1.6mA inputs), but
> only source a few (1.6mA comes to mind).
That was 400uA IOH.
> The saturated NPN in the low
> level is much stronger than the current limited (TTL was designed not
> to self-destruct if the outputs were tied together) emitter follower-
> diode pullup.
Also about 130 ohms in the pullup collector- to limit current into the
saturated pulldown among other things- diode included to ensure pullup off.
>
>
>> >This is the primary reason TTL CS and OE signals
>> > are negative active.
>
>
>
>>Hmmm...I wonder about that assertion. It would seem to me that this
>>accident of polarity is more the result of the fact that the fundamental
>>subcircuit structure of the logic family is the buffered inverter, the
>>IC enable/select type inputs were routed to a multitude of internal chip
>>gates, and smart logic family design would require that all inputs be
>>buffered- present a unit load to the external world.
>
>
> Nope. Negative active enables (and data on some) made switching
> heavily loaded/capacitive busses faster.
This doesn't make any sense to me, fast on and slow off from a bus means
contention and surge currents if you don't wait for the slowest Tpd anyway.
Keith R. Williams
> "Keith R. Williams" wrote:
> >
> > In article <3EC2C544...@no.spam>, sen...@no.spam says...
> > > "Keith R. Williams" wrote:
> > > >
> > > > In article <b9tf07$ru0$1...@usenet01.srv.cis.pitt.edu>, szek...@pitt.edu
> > > > says...
> > > > > In article <55fb3fe4.0305...@posting.google.com>, gmsch...@earthlink.net (Michael Schupbach) wrote:
> > > > > >What are the advantages of using negative logic in circuit design? I
> > > > > >have a professor who is talking about reducing power surges through
> > > > >
> > > > > Almost all external lines were always negative logic. Maybe not now,
> > > > > but they were. I always thought is was for noise control, but TTL near ground
> > > > > is rather iffy.
> > > >
> > > > 1) TTL has a stronger negative drive, so it switches faster
> > > > '1' -> '0'. This is the primary reason TTL CS and OE signals
> > > > are negative active.
> > >
> > > While this is true, it doesn't explain why write enables are also almost
> > > always active low since the slower 0->1 transition is detrimental in
> > > this case.
> >
> > Almost always? I've never seen this to be the case. OTOH, bus
> > OE# always favor the negative.
>
> Show me ANY RAM from the TTL era that uses an active high write enable.
> For that matter, try to find a RAM even now that uses active high write
> enables.
You're misunderstanding my issue. I'm saying that the faster 1->0
transition makes the operation faster. You say the slower 0->1 slows
the circuit down. I haven't seen this to be the case. Certinaly I
know that most, if not all, RAM enables are negative active, precisely
because it *is* faster (in TTL anyway).
> > > I was always told that the primary reason is because active-low TTL
> > > signals have better noise margin when inactive. If the "off" state is
> > > low, you need less than 0.8 V of noise to kick the signal into the
> > > undefined region whereas when "off" is high (~3.4V) you need 1.4V of
> > > noise to move into the undefined region.
> >
> > I dont buy it. The nominal threshold for TTL is ~1.4V. The
> > minimum input high level is 2.0V and (input) low level is .8V.
> > This is pretty symmetrical. The fact is that TTL has a much
> > lower output impedance in the low level helps the noise margin in
> > the low level.
>
> Even if you use a 1.4 V switching threshold, you still get 2.0 V margin
> on a high (3.4 V typical high output) vs a 1.2 V margin on low (0.2 V
> typical low output). Numbers are from the 7400 data sheet. Yes, the
> output impedance is higher in '1' state but is it enough higher to
> offset the almost 2:1 difference in noise margin? I don't know for sure
> but I suspect the margin is still higher in the 1 state.
No, the input specification calls for a >2.0V LPUL. Outputs of the
driver *may* be higher than this (actually they must be >2.4V) but not
necessarily 3.1V (.9*5V-2*Vbe). The noise margin in the specification
is the same for the up and down levels.
> > > 5) Power dissipation is significantly lower (usually by about 3x) with
> > > the output of a simple TTL gate high than when it's low.
> >
> > ...don't buy it. You're going to have to show me. AFAIK this
> > depends on the output loading. The input and bias currents are
> > pretty much the same in either state.
>
> Look at the data sheet for a 7400. Current consumption is listed as 8
> mA/gate with inputs low (output high) and 22 mA/gate with inputs high.
Oops! You're right here. After drawing the circuit (it's been a while
since real TTL was interesting ;-) I was thinking about the base
current of Q1 going either out the input or as the base current of Q2.
Clearly though with the input high there is current flowing in the
collector of Q2, which there isn't with the input low.
7400 Clasic: Vcc Vcc Vcc
| | |
.-. .-. |
| | | | |
| | | | |
'-' '-' |
| | |
| | |/
| o----| Q3
| | |>
| | |
| | V
--- |/ -
In1 -----v \---------| Q2 |
In2 -----V |> o---------o Out
Q1 | |
| |
| |/
o----| Q4
| |>
| |
| |
.-. |
| | |
| | |
'-' Gnd
|
Gnd
created by Andy´s ASCII-Circuit v1.22.310103 Beta www.tech-chat.de
> Also, input currents are very definitely not the same. All TTL families
> require more current to drive an input low than to drive it high.
> Usually several times more (1.6 mA low, 40 uA high for 7400).
The input low currents are very small. It's the base current of Q1.
Of course there is only leakage current with the input high. There is
a difference but it's minuscule.
> Notice that we're talking about the original 7400 series gates here, not
> recent TTL-compatible CMOS versions. The active low decisions were made
> for this family and all follow-ons simply complied with the established
> standard.
I agree completely. That's certainly been my position here. Active
low enables were made with the full understanding of TTL asymmetry.
> The 7400 series may even have been following standards
> established by DTL or RTL but since I haven't used those families, I
> don't really know much about them.
No, the original 7400 TTL broke the mold of RTL. Note that "STTL" is
really SDTL.
--
Keith
Nico Coesel
>> But the 4000 series CMOS tended to use +ve logic
>> anyway, and when they didn't they *named* the pins using positive
>> logic (inhibit rather than /enable).
>
>I got bit by this with the Xilinx IOBs too. Who woulda think the
>OE's were really OUTPUT ENABLE, rather than Tri-State-Enables?
>Sheesh! BTW, I'm not the only one.
It gets even worse. The synthesis tool I'm using (which can show a
schematic of the compiled VHDL sources) shows a tri-state buffer as a
regular tri-state buffer with an inverter between the T input and the
OE of the tri-state buffer.
--
Reply to nico@nctdevpuntnl (punt=.)
Bedrijven en winkels vind U op www.adresboekje.nl
Tim Hubberstey
The slower 0->1 transition on a write enable increases the hold time
requirement on the write data and thereby forces the write data to be
asserted further into the next bus cycle. This slows down the overall
throughput of the bus since I have found that the dominant setup time
for a RAM write cycle is usually defined by the required address setup
time, not by the data setup time. Also, the faster 1->0 write enable
transition cuts into the available address decoding time and may
actually require that the write enable be delayed, in some cases. The
intent may have been to make things faster but this is not the result I
have seen.
> > > > I was always told that the primary reason is because active-low TTL
> > > > signals have better noise margin when inactive. If the "off" state is
> > > > low, you need less than 0.8 V of noise to kick the signal into the
> > > > undefined region whereas when "off" is high (~3.4V) you need 1.4V of
> > > > noise to move into the undefined region.
> > >
> > > I dont buy it. The nominal threshold for TTL is ~1.4V. The
> > > minimum input high level is 2.0V and (input) low level is .8V.
> > > This is pretty symmetrical. The fact is that TTL has a much
> > > lower output impedance in the low level helps the noise margin in
> > > the low level.
> >
> > Even if you use a 1.4 V switching threshold, you still get 2.0 V margin
> > on a high (3.4 V typical high output) vs a 1.2 V margin on low (0.2 V
> > typical low output). Numbers are from the 7400 data sheet. Yes, the
> > output impedance is higher in '1' state but is it enough higher to
> > offset the almost 2:1 difference in noise margin? I don't know for sure
> > but I suspect the margin is still higher in the 1 state.
>
> No, the input specification calls for a >2.0V LPUL. Outputs of the
> driver *may* be higher than this (actually they must be >2.4V) but not
> necessarily 3.1V (.9*5V-2*Vbe). The noise margin in the specification
> is the same for the up and down levels.
"Real world" noise margin are determined by the typical output values
and (as you pointed out) switching thresholds of the inputs, not by the
minimum requirements of the specification. The typical values that I
quoted are taken directly from the TTL data book. However, there is
enough uncertainty here that I'm willing to concede that better noise
margin may not have been the primary reason for using active low control
signals.
1.6 mA vs 40 uA is hardly a minuscule difference. These numbers are from
the TI TTL data book and contesting them simply makes no sense.
> > Notice that we're talking about the original 7400 series gates here, not
> > recent TTL-compatible CMOS versions. The active low decisions were made
> > for this family and all follow-ons simply complied with the established
> > standard.
>
> I agree completely. That's certainly been my position here. Active
> low enables were made with the full understanding of TTL asymmetry.
>
> > The 7400 series may even have been following standards
> > established by DTL or RTL but since I haven't used those families, I
> > don't really know much about them.
>
> No, the original 7400 TTL broke the mold of RTL. Note that "STTL" is
> really SDTL.
--
Keith R. Williams
Latency is measured from when you finally figure out you need the
data to when it's available. On a heavily loaded bus it makes a
difference how fast one can drive the selects active. A strong
driver works wonders driving huge capacitances (one reason the PC
I/O channel sucked bilge-water, BTW).
Latency <> bandwidth.
--
Keith
Keith R. Williams
says...
> Keith R. Williams <k...@attglobal.net> wrote:
>
> >> But the 4000 series CMOS tended to use +ve logic
> >> anyway, and when they didn't they *named* the pins using positive
> >> logic (inhibit rather than /enable).
> >
> >I got bit by this with the Xilinx IOBs too. Who woulda think the
> >OE's were really OUTPUT ENABLE, rather than Tri-State-Enables?
> >Sheesh! BTW, I'm not the only one.
>
> It gets even worse. The synthesis tool I'm using (which can show a
> schematic of the compiled VHDL sources) shows a tri-state buffer as a
> regular tri-state buffer with an inverter between the T input and the
> OE of the tri-state buffer.
Synplify by chance?
Actually I believe it's right (there was some discussion about this in
comp.arch.fpga some time back). 'T' (tri-state enable) is the inverse
of 'OE' (output enable).
...and then there's the problem of forcing registers into the IOBs.
--
Keith
John Larkin
Schupbach) wrote:
>What are the advantages of using negative logic in circuit design? I
>have a professor who is talking about reducing power surges through
>the transformer and power supply and reducing magnetic fields and some
>other far-fetched sounding stuff.
>
>I was under the impression that most transistors can sink more than
>they can source and that transistors spend more of their time in the
>"off" state.
>
>Any input welcome.
>
>Thank you,
>Michael Schupbach
Interesting issue. The earliest IC logic gates were 2-input NORs (in
RTL) and NANDs (in DTL), probably because they were the easiest to
make (one transistor!) and were "universal": you can make anything if
you have only a 2-NOR or a 2-NAND to work with. This is important in
selling a product line, when you have to get users interested as soon
as the first part hits the streets. Later on, the wider gates tended
to be NANDs, so most decoding became active-low. Then the convention
became to have chip selects correspondingly active low.
It's probably an emotional issue among older engineers to treat
chip-select things as active low, even when it's between FPGAs where
it doesn't matter. Similarly, people tend to use pullups for stuff
like undriven busses and dipswitches, when pulldowns are actually more
"logical." I recently started pulling busses and switches down, and it
feels a little weird. Old hobbits die hard.
I wonder why clocks standardized on active rising edges? I think a
very few TTL ICs had falling-edge clocks. Are clocks mostly
falling-edge in Australia?
Oh, your professor is a twit.
John
Rene Tschaggelar
> Similarly, people tend to use pullups for stuff
> like undriven busses and dipswitches, when pulldowns are actually more
> "logical." I recently started pulling busses and switches down, and it
> feels a little weird. Old hobbits die hard.
It depends on the logic. A TTL pullup is drawing less current than
a pulldown. This comes from the output stage of a TTL which basically
is a open collector. With CMOS, or the newer HCMOS it shouldn't matter.
>
> I wonder why clocks standardized on active rising edges? I think a
> very few TTL ICs had falling-edge clocks. Are clocks mostly
> falling-edge in Australia?
That is a good one. They never got used to having maps with
south-up, which would have been the first move to disconnect
from the north. Then on the other hand, they disconnected from
the queen only recently.
Rene
--
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net
Spehro Pefhany
<tscha...@dplanet.ch> wrote:
>That is a good one. They never got used to having maps with
>south-up, which would have been the first move to disconnect
>from the north.
Something I've long advocated for the Antipodes.
>Then on the other hand, they disconnected from
>the queen only recently.
Who's the old gal on the AUD5 bill then?
Keith R. Williams
jjla...@highSNIPlandTHIStechPLEASEnology.com says...
Indeed. I used active low on my first FPGA design. After a couple of
weeks doing (and learning) VHDL, I finally realized "this is dumb" and
went to everything "positive active".
>
> I wonder why clocks standardized on active rising edges? I think a
> very few TTL ICs had falling-edge clocks. Are clocks mostly
> falling-edge in Australia?
74xx73A is negative active. The 74xx73 is too, sorta. These are the
antiques of the TTL line though.
>
>
--
Keith
Nico Coesel
>In article <3ec3f6c2....@news.planet.nl>, ni...@puntnl.niks
>says...
>> Keith R. Williams <k...@attglobal.net> wrote:
>>
>> >> But the 4000 series CMOS tended to use +ve logic
>> >> anyway, and when they didn't they *named* the pins using positive
>> >> logic (inhibit rather than /enable).
>> >
>> >I got bit by this with the Xilinx IOBs too. Who woulda think the
>> >OE's were really OUTPUT ENABLE, rather than Tri-State-Enables?
>> >Sheesh! BTW, I'm not the only one.
>>
>> It gets even worse. The synthesis tool I'm using (which can show a
>> schematic of the compiled VHDL sources) shows a tri-state buffer as a
>> regular tri-state buffer with an inverter between the T input and the
>> OE of the tri-state buffer.
>
>Synplify by chance?
No, FPGA Express. It's the Synopsis package as distributed along with
Xilinx's ISE4.x
>Actually I believe it's right (there was some discussion about this in
>comp.arch.fpga some time back). 'T' (tri-state enable) is the inverse
>of 'OE' (output enable).
I'm finding OE more intuitive to use. But it's something I'll have to
learn to live with.
>...and then there's the problem of forcing registers into the IOBs.
Fortunately I don't have to tune designs _that_ far :-) I sometimes
use some options with the routing software to use the IOB flipflops as
well in order to cram a big design in a -relative to the design- small
Xilinx. Anyway, it still amazes me what you can cram into a 100k gates
device.
doh.....
margin on the low than on the high. Signals that spend most of their time
inactive are better assigned active low. For example, write enables,
resets, etc.
TTL inputs consume more power in the low state, so power is saved by
assigning
the prevelant logic condition to the high state.
Passive pullup networks consume less power when high, so again, power is
saved
by assigning the most common state to high (if it is logically feasable)
In modern CMOS designs, use of active low (for example on standard cell flip
flops) is
driven only by the area saved. If it took less area to design a flip flop
with active high
reset, then, trust me, the reset would be active high. (unless you are
thinking drive
capability, where nmos devices are lower resistance for given area)
For designs that use HDL's (like verilog) it makes no sense to use negative
logic
other than when connecting to cells with negative logic inputs.
The compiler will use positive/negative logic as it determines to meet
speed/area
constraints. I always name things according to their high state. (I hate
names like
"input_mode" as opposed to "input_enabled"). There is no advantage to
calling it "input_disabled_n" unless you need a port with negative logic for
some reason.
Bruce
"Michael Schupbach" <gmsch...@earthlink.net> wrote in message
news:55fb3fe4.0305...@posting.google.com...
Alan
> On 13 May 2003 20:26:34 -0700, gmsch...@earthlink.net (Michael
> Schupbach) wrote:
>
> >What are the advantages of using negative logic in circuit design? I
> >have a professor who is talking about reducing power surges through
> >the transformer and power supply and reducing magnetic fields and some
> >other far-fetched sounding stuff.
If high is your active state, then you have to have enough of a
supply to drive the line high as fast as you need for a switching
time. If low is the active state, and time to high isn't as critical
you can have a very weak supply, and just switch low. You still get
fast switch times for active without having as high a current +
supply.
> >I was under the impression that most transistors can sink more than
> >they can source and that transistors spend more of their time in the
> >"off" state.
Active low comes from this sinking better than sourcing, it was
cheaper to do this and let an inactive resistor pull it high. There
was transistor to have to pull it high, only a cheap one to pull low.
> It's probably an emotional issue among older engineers to treat
> chip-select things as active low, even when it's between FPGAs where
> it doesn't matter. Similarly, people tend to use pullups for stuff
> like undriven busses and dipswitches, when pulldowns are actually more
> "logical."
Hmm being simply a change in reference, I think it's actually just
as 'logical' regardless of which way is used. It may be more
practical to think from 0 on a bus or use high to trace the signals
against a common ground, but I think it's logically the same..
>I recently started pulling busses and switches down, and it
> feels a little weird. Old hobbits die hard.
It's also easier to hunt a line if it's active low and high
normally. Every ground makes for a test point against the line, and
breaks show up easily. If it's normally low, did the line break or is
it off? Doesn't make much difference on a single board but much
easier to hunt around a building or other large area for breaks etc.
> I wonder why clocks standardized on active rising edges? I think a
> very few TTL ICs had falling-edge clocks. Are clocks mostly
> falling-edge in Australia?
I believe if you go through a text on digital logic the simplest
adders/counters made from XOR gates work out to generating and needing
rising edge clocking. Not that you can't invert the whole system for
the logical opposite, but then your logical high is 0V and logical low
is 5V etc. Been a while since I looked at that text, but I believe
that was the case. Find one to check out at least for kicks, the
simplest binary adders and counters from XOR gates are actually neat
to follow.
Alan
Fred Bloggs
Keith R. Williams wrote:
>>I wonder why clocks standardized on active rising edges? I think a
>>very few TTL ICs had falling-edge clocks. Are clocks mostly
>>falling-edge in Australia?
>
>
> 74xx73A is negative active. The 74xx73 is too, sorta. These are the
> antiques of the TTL line though.
>
I recently reviewed the old TI text on designing with TTL logic. Unlike
my first reading many years ago which took a week of detailed study,
this time around was maybe 30 minutes. There was absolutely no mention
anywhere of a technological reason for favoring active low over active
high. The original designers considered both transitions to be equally
low impedance and fast. Plots of tpd's as a function of load capacitance
showed the skew to track. TTL may be ancient, but as a logic circuit
family, it was a stellar beauty. I particularly like the older clocked
circuits requiring that any control input state changes occur while
clock is high- LOL- try doing that with modern high speed clocks. Fast
edge rates were considered a plague on the family at the time, hence the
chapter on transmission line reflection diagrams. The old Fairchild 9000
series TTL databook contained transistor level circuit diagrams for each
part and there you will find more tangible reasons for most of the input
polarities- highest speed performance with least circuitry. Sheesh-
someone has some *real* old catalog pages here:
http://www.wps.com/archives/solid-state-datasheets/Datasheets/Fairchild-TTL-9000-9007/
RP Henry
"Alan" <alan...@yahoo.com> wrote in message
news:dfee2f9c.03052...@posting.google.com...
>
> I believe if you go through a text on digital logic the simplest
> adders/counters made from XOR gates work out to generating and needing
> rising edge clocking. Not that you can't invert the whole system for
> the logical opposite, but then your logical high is 0V and logical low
> is 5V etc. Been a while since I looked at that text, but I believe
> that was the case. Find one to check out at least for kicks, the
> simplest binary adders and counters from XOR gates are actually neat
> to follow.
What has always made sense to me is that the simplest transistor circuit
(common-emitter, emitter connected to ground, signal in on base, signal out
on collector connected through load resistor to +V) inverts the signal
between base and collector. Extrapolating to TTL structures, nands are
better (simpler, faster and consume less power) than ands, nors are better
than ors, et cetera, ad nauseam, caveat lector.
Brooke Clarke
There are a couple of things to take into account:
(1) If there is an external input and you are using Normal (high is true) logic, then a broken input wire will produce a true indication. If negative logic is used then it takes a short on the input and will only work when there are no broken wires. Sort of like a burglar alarm that uses normally closed switches so that a break in the wire sounds the alarm.
(2) For internal logic there is a process called state minimization where you are going to use standard gates like and, nand, or, nor. By changing the polarity of the logic back and forth you can end up using fewer gates.
Have Fun,
Brooke Clarke, N6GCE