Soldering - thermal vias under D-PAK

[dagmarg...@yahoo.com]

A board house just griped about half a dozen or so thermal vias under
a D-PAK regulator, used to heatsink the device to a groundplane
beneath.

Their gripe is the vias wick the solder paste out from under
the device.

The PCB guy had said the vias were standard practice, which is
certainly what I thought too.

What say yee?

Cheers,
James Arthur

[Lasse Langwadt Christensen]

wicking the solder pasta does happen but it is probably not a huge issue
with a big pad like a dpak

https://i.screamingcircuits.com/docs/Via_In_Pad_Guidelines.pdf

-Lasse

[k...@attt.bizz]

On Wed, 25 Jun 2014 15:26:31 -0700 (PDT), dagmarg...@yahoo.com
wrote:

It's certainly recommended by the manufacturer of pretty much every
part with a thermal pad (they keep telling me I need more). I haven't
seen your problem in years but if they're having a problem with it,
they're likely not getting enough paste on the board or perhaps the
vias are too big. There really shouldn't be that much wicking,
particularly on something as big as a D-PAK.

[Joe Chisolm]

We use them all the time (but not D-PAK). There is some wicking but
you can compensate with the paste opening.

--
Chisolm
Republic of Texas

[dagmarg...@yahoo.com]

On Wednesday, June 25, 2014 7:07:25 PM UTC-4, Joe Chisolm wrote:
> On Wed, 25 Jun 2014 15:26:31 -0700, dagmargoodboat wrote:
>
> > A board house just griped about half a dozen or so thermal vias under a
> > D-PAK regulator, used to heatsink the device to a groundplane beneath.
> >
> > Their gripe is the vias wick the solder paste out from under the device.
> >
> > The PCB guy had said the vias were standard practice, which is certainly
> > what I thought too.
> >
> > What say yee?
>

> We use them all the time (but not D-PAK). There is some wicking but
> you can compensate with the paste opening.

Paste opening? You mean leave a clearance around the vias in the paste
mask?

They asked we do that, but it seems the solder would just flow,
wet, and wick, with less solder to do it all with. Their alternate "ask"
was filled vias.

I pulled the artwork. There are actually two dozen x .020" thermals.
More than I remembered, but the holes are small.

All the heatsinking's on the bottom, so tightly-coupled is good.

Thanks for the feedback,
James Arthur

[Lasse Langwadt Christensen]

if you intend the pcb to bolt a heatsink on the back the wicking
may cause another problem, you sometimes get little solder
"dimples" where solder wicked through the vias so back side is not flat

-Lasse

[dagmarg...@yahoo.com]

Thanks for that document Lasse, quite helpful.

It looks like the please-everyone solution is plugging the tops of
the thermals with copper.

I'm not sure exactly how to spec that...scratch, scratch.

Cheers,
James Arthur

[dagmarg...@yahoo.com]

On Wednesday, June 25, 2014 8:08:08 PM UTC-4, Lasse Langwadt Christensen wrote:
> Den torsdag den 26. juni 2014 02.01.51 UTC+2 skrev dagmarg...@yahoo.com:
> > On Wednesday, June 25, 2014 7:07:25 PM UTC-4, Joe Chisolm wrote:
> > > On Wed, 25 Jun 2014 15:26:31 -0700, dagmargoodboat wrote:
> > >
> > > > A board house just griped about half a dozen or so thermal vias under a
> > > > D-PAK regulator, used to heatsink the device to a groundplane beneath.
> > > >
> > > > Their gripe is the vias wick the solder paste out from under the device.
> > > >
> > > > The PCB guy had said the vias were standard practice, which is certainly
> > > > what I thought too.
> > > >
> > > > What say yee?
> > >
> > > We use them all the time (but not D-PAK). There is some wicking but
> > > you can compensate with the paste opening.
> >
> > Paste opening? You mean leave a clearance around the vias in the paste
> > mask?
> >
> > They asked we do that, but it seems the solder would just flow,
> > wet, and wick, with less solder to do it all with. Their alternate "ask"
> > was filled vias.
> >
> > I pulled the artwork. There are actually two dozen x .020" thermals.
> >
> > More than I remembered, but the holes are small.

I calculated the thermal array gives 5oC/W to the bottom layer. The voids
occupy 3.5% of the surface area under the pad.

> > All the heatsinking's on the bottom, so tightly-coupled is good.
> >
>
> if you intend the pcb to bolt a heatsink on the back the wicking
> may cause another problem, you sometimes get little solder
> "dimples" where solder wicked through the vias so back side is not flat

That's not a problem--I've got enough backside copper to handle things.
If we cap the vias and the caps bulge up, holding the part off the board,
that's a problem.

Cheers,
James Arthur

[John Larkin]

That's a lot of vias. How much power is the dpak dissipating? Is there a real
heat sink bonded to the bottom of the board, or just a copper pour?

A 20 mil via through an 0.062 thick 1 oz board will be ballpark 70 K/watt. So 20
of them will be roughly 4 K/W.

The alternative is to move most of the thermal vias a bit outside the part
footprint, with a little solder mask zone to keep the vias from slurping the
solder.

Or add more paste.


--

John Larkin Highland Technology Inc
www.highlandtechnology.com jlarkin at highlandtechnology dot com

Precision electronic instrumentation

[John Larkin]

On Wed, 25 Jun 2014 18:19:39 -0700 (PDT), dagmarg...@yahoo.com wrote:

>On Wednesday, June 25, 2014 8:08:08 PM UTC-4, Lasse Langwadt Christensen wrote:
>> Den torsdag den 26. juni 2014 02.01.51 UTC+2 skrev dagmarg...@yahoo.com:
>> > On Wednesday, June 25, 2014 7:07:25 PM UTC-4, Joe Chisolm wrote:
>> > > On Wed, 25 Jun 2014 15:26:31 -0700, dagmargoodboat wrote:
>> > >
>> > > > A board house just griped about half a dozen or so thermal vias under a
>> > > > D-PAK regulator, used to heatsink the device to a groundplane beneath.
>> > > >
>> > > > Their gripe is the vias wick the solder paste out from under the device.
>> > > >
>> > > > The PCB guy had said the vias were standard practice, which is certainly
>> > > > what I thought too.
>> > > >
>> > > > What say yee?
>> > >
>> > > We use them all the time (but not D-PAK). There is some wicking but
>> > > you can compensate with the paste opening.
>> >
>> > Paste opening? You mean leave a clearance around the vias in the paste
>> > mask?
>> >
>> > They asked we do that, but it seems the solder would just flow,
>> > wet, and wick, with less solder to do it all with. Their alternate "ask"
>> > was filled vias.
>> >
>> > I pulled the artwork. There are actually two dozen x .020" thermals.
>> >
>> > More than I remembered, but the holes are small.
>
>I calculated the thermal array gives 5oC/W to the bottom layer. The voids
>occupy 3.5% of the surface area under the pad.

I calculated a lot less, about 70 K/W per hole, assuming 1 oz plating in the
holes. Of course, if they steal the solder and fill themselves, it will be even
less.

[dagmarg...@yahoo.com]

On Wednesday, June 25, 2014 6:59:18 PM UTC-4, k...@attt.bizz wrote:
> On Wed, 25 Jun 2014 15:26:31 -0700 (PDT), dagmargoo...@yahoo.com

They may have a point. I calculate the fill volume of the vias at
nearly 8mm^3. If we cut the hole size in half and double the
holes, we'd save 1/2 of that, and gain copper cross section.

But that's a lot of holes. Small ones.

I can move about a third of the holes off-pad.

It's yucky.

Cheers,
James Arthur

[dagmarg...@yahoo.com]

On Wednesday, June 25, 2014 10:21:06 PM UTC-4, John Larkin wrote:

> On Wed, 25 Jun 2014 18:19:39 -0700 (PDT), dagmargoo...@yahoo.com wrote:
> >On Wednesday, June 25, 2014 8:08:08 PM UTC-4, Lasse Langwadt Christensen wrote:
> >> Den torsdag den 26. juni 2014 02.01.51 UTC+2 skrev dagmarg...@yahoo.com:
> >> > On Wednesday, June 25, 2014 7:07:25 PM UTC-4, Joe Chisolm wrote:
> >> > > On Wed, 25 Jun 2014 15:26:31 -0700, dagmargoodboat wrote:
> >> > >
> >> > > > A board house just griped about half a dozen or so thermal vias under a
> >> > > > D-PAK regulator, used to heatsink the device to a groundplane beneath.
> >> > > >
> >> > > > Their gripe is the vias wick the solder paste out from under the device.
> >> > > >
> >> > > > The PCB guy had said the vias were standard practice, which is certainly
> >> > > > what I thought too.
> >> > > >
> >> > > > What say yee?
> >> > >
> >> > > We use them all the time (but not D-PAK). There is some wicking but
> >> > > you can compensate with the paste opening.
> >> >
> >> > Paste opening? You mean leave a clearance around the vias in the paste
> >> > mask?
> >> >
> >> > They asked we do that, but it seems the solder would just flow,
> >> > wet, and wick, with less solder to do it all with. Their alternate "ask"
> >> > was filled vias.
> >> >
> >> > I pulled the artwork. There are actually two dozen x .020" thermals.
> >> >
> >> > More than I remembered, but the holes are small.
> >
> >I calculated the thermal array gives 5oC/W to the bottom layer. The voids
> >occupy 3.5% of the surface area under the pad.
>
> I calculated a lot less, about 70 K/W per hole, assuming 1 oz plating in the
> holes.

I got five, you got four--you're only 20% less than my calculation.

I wrote a spreadsheet that does the math from basic principles &
constants--should be pretty reliable.

> Of course, if they steal the solder and fill themselves, it will be even
> less.

An excellent point. If I could count on that, I could chop out most of
the vias. I'm afraid to--after all, the board house's complaint is that
they don't want to fill 'em.

I might add that scenario to my spreadsheet.

Cheers,
James

[dagmarg...@yahoo.com]

On Wednesday, June 25, 2014 10:18:32 PM UTC-4, John Larkin wrote:

> On Wed, 25 Jun 2014 17:01:51 -0700 (PDT), dagmargoo...@yahoo.com wrote:
> >On Wednesday, June 25, 2014 7:07:25 PM UTC-4, Joe Chisolm wrote:
> >> On Wed, 25 Jun 2014 15:26:31 -0700, dagmargoodboat wrote:

> >> > A board house just griped about half a dozen or so thermal vias under a
> >> > D-PAK regulator, used to heatsink the device to a groundplane beneath.
> >> >
> >> > Their gripe is the vias wick the solder paste out from under the device.
> >> >
> >> > The PCB guy had said the vias were standard practice, which is certainly
> >> > what I thought too.
> >> >
> >> > What say yee?
> >>
> >> We use them all the time (but not D-PAK). There is some wicking but
> >> you can compensate with the paste opening.
> >
> >Paste opening? You mean leave a clearance around the vias in the paste
> >mask?
> >
> >They asked we do that, but it seems the solder would just flow,
> >wet, and wick, with less solder to do it all with. Their alternate "ask"
> >was filled vias.
> >
> >I pulled the artwork. There are actually two dozen x .020" thermals.
> >More than I remembered, but the holes are small.
> >
> >All the heatsinking's on the bottom, so tightly-coupled is good.
> >
> >Thanks for the feedback,
>

> That's a lot of vias. How much power is the dpak dissipating? Is there a real
> heat sink bonded to the bottom of the board, or just a copper pour?

Just a copper pour. I don't know the dissipation--originally it was
trivial, but the customer has changed the topology and the load. I'm
assuming it could be considerable.

> A 20 mil via through an 0.062 thick 1 oz board will be ballpark 70 K/watt. So 20
> of them will be roughly 4 K/W.
>
> The alternative is to move most of the thermal vias a bit outside the part
> footprint, with a little solder mask zone to keep the vias from slurping the
> solder.

Can't. I have room to move about 1/3rd of them, which we certainly will.

> Or add more paste.

Yes.

As usual most of the problem is in the constraints, which are mostly
artificial.

Cheers,
James

[rickman]

My understanding is that thermal pads get a divided solder paste mask to
reduce the solder load by some amount approaching 50% anyway. I believe
an unbroken slug of paste has problems with both gasses escaping and the
part floating on the big ball of solder. I can't imagine the vias will
wick very much in comparison.

You said the vias are 0.020, can you make them smaller and use more?
When I was having a board made with 0.013 vias (drill size) I was told
they nearly plate shut anyway.

--

Rick

[John Larkin]

If it's just a pour on the bottom, the theta of the vias is not too important.

The big issue will be thermal spreading. The vias in the interior of the array
are doing almost no good, because they are in the middle of a hot spot. Vias
outside the dpak footprint would likely be better than vias inside, because they
"reach out" farther into the bottom pour.

I like to use a modest number of thermals inside the footprint, four maybe, plus
some outside, 8 or 12 maybe, not too close in. But also use an inner layer pour
as a heat spreader, to move heat from the inner to the outer vias.

Here's a vaguely similar case. A hot spot on the top of the board:

https://dl.dropboxusercontent.com/u/53724080/Thermal/T750_t1.JPG

https://dl.dropboxusercontent.com/u/53724080/Thermal/T750_t3.jpg

Now what's interesting is the bottom of the board:

https://dl.dropboxusercontent.com/u/53724080/Thermal/T750_t5.jpg

Note the small hot spot (the strip is kapton tape, to raise the emissivity for
the thermal imager.) That's terrible thermally. When the heat sink is a copper
pour, spreading out the heat, using out-there vias on multiple layers, really
helps.

>> A 20 mil via through an 0.062 thick 1 oz board will be ballpark 70 K/watt. So 20
>> of them will be roughly 4 K/W.
>>
>> The alternative is to move most of the thermal vias a bit outside the part
>> footprint, with a little solder mask zone to keep the vias from slurping the
>> solder.
>
>Can't. I have room to move about 1/3rd of them, which we certainly will.

Dump most of the central ones. They slurp solder but don't help much thermally.

[Tom Miller]

"John Larkin" <jjla...@highNOTlandTHIStechnologyPART.com> wrote in message
news:pb0nq9dirrsv5avuj...@4ax.com...

Or solder the heat sink on.

[rickman]

The data you post does not really support your conclusion. You are
looking at a picture and drawing a conclusion without even considering
the full design. The question is *not* what does the heat spreader do,
the question is what do the vias do. The fact that the spreader has a 5
degree temperature drop says nothing about the temperature drop across
the vias if you use more or less or where you put them.

I believe your test case does not have vias from what I can see, right?
I see a temperature drop through the board of 10�C or more. But since
that is without vias at all, I can't see how it is very relevant. Do
you have any idea of the temperature drop through the board with vias?

--

Rick

[dagmarg...@yahoo.com]

On Wednesday, June 25, 2014 10:56:35 PM UTC-4, dagmarg...@yahoo.com wrote:
> On Wednesday, June 25, 2014 10:21:06 PM UTC-4, John Larkin wrote:
> > On Wed, 25 Jun 2014 18:19:39 -0700 (PDT), dagmargoo...@yahoo.com wrote:
> > >On Wednesday, June 25, 2014 8:08:08 PM UTC-4, Lasse Langwadt Christensen wrote:
> > >> Den torsdag den 26. juni 2014 02.01.51 UTC+2 skrev dagmarg...@yahoo.com:
> > >> > On Wednesday, June 25, 2014 7:07:25 PM UTC-4, Joe Chisolm wrote:
> > >> > > On Wed, 25 Jun 2014 15:26:31 -0700, dagmargoodboat wrote:
> > >> > >
> > >> > > > A board house just griped about half a dozen or so thermal vias under a
> > >> > > > D-PAK regulator, used to heatsink the device to a groundplane beneath.
> > >> > > >
> > >> > > > Their gripe is the vias wick the solder paste out from under the device.
> > >> > > >
> > >> > > > The PCB guy had said the vias were standard practice, which is certainly
> > >> > > > what I thought too.
> > >> > > >

> > >> > > > What say ye?

> > >> > >
> > >> > > We use them all the time (but not D-PAK). There is some wicking but
> > >> > > you can compensate with the paste opening.
> > >> >
> > >> > Paste opening? You mean leave a clearance around the vias in the paste
> > >> > mask?
>
> > >> >
>
> > >> > They asked we do that, but it seems the solder would just flow,
> > >> > wet, and wick, with less solder to do it all with. Their alternate "ask"
> > >> > was filled vias.
> > >> >
> > >> > I pulled the artwork. There are actually two dozen x .020" thermals.
> > >> >
> > >> > More than I remembered, but the holes are small.
> > >
> > >I calculated the thermal array gives 5oC/W to the bottom layer. The voids
> > >occupy 3.5% of the surface area under the pad.
> >
> > I calculated a lot less, about 70 K/W per hole, assuming 1 oz plating in the
> > holes.
>
> I got five, you got four--you're only 20% less than my calculation.
>
> I wrote a spreadsheet that does the math from basic principles &
> constants--should be pretty reliable.
>
> > Of course, if they steal the solder and fill themselves, it will be even
> > less.
>

> An excellent point. If I could count on that I could chop out most of

> the vias. I'm afraid to--after all, the board house's complaint is that
> they don't want to fill 'em.
>
> I might add that scenario to my spreadsheet.

Okay, found and fixed a bug. I get 99 K/W for a 0.020" hole, 3/4 oz.
plating, 0.062" board. 4.3 K/W for my array. Filled with lead-free
solder, 57 K/W each, 2.5 K/W for the array.

You're right, it's spreading-limited.

This thing's marginal, but I'm not allowed to change anything important.

Annoying.

James

[dagmarg...@yahoo.com]

On Wednesday, June 25, 2014 11:28:30 PM UTC-4, rickman wrote:

> On 6/25/2014 11:04 PM, dagmargoo...@yahoo.com wrote:
> > On Wednesday, June 25, 2014 10:18:32 PM UTC-4, John Larkin wrote:
> >> On Wed, 25 Jun 2014 17:01:51 -0700 (PDT), dagmargoo...@yahoo.com wrote:
> >>> On Wednesday, June 25, 2014 7:07:25 PM UTC-4, Joe Chisolm wrote:
> >>>> On Wed, 25 Jun 2014 15:26:31 -0700, dagmargoodboat wrote:
> >
> >>>>> A board house just griped about half a dozen or so thermal vias under a
> >>>>> D-PAK regulator, used to heatsink the device to a groundplane beneath.
> >>>>>
> >>>>> Their gripe is the vias wick the solder paste out from under the device.
> >>>>>
> >>>>> The PCB guy had said the vias were standard practice, which is certainly
> >>>>> what I thought too.
> >>>>>

> >>>>> What say ye?

It's hard to imagine a slug of paste sitting on via-Swiss-cheese will
have a venting problem.

> You said the vias are 0.020, can you make them smaller and use more?

My handy spreadsheet says doubling the holes and cutting the size is a net
small loss thermally if the vias are solder-filled, but cuts the hole-fill
volume in half. The copper path is better, but the via-fill path (solder)
is worse.

> When I was having a board made with 0.013 vias (drill size) I was told
> they nearly plate shut anyway.

I hope they don't! We're spec'ing finished hole size. But, maybe we
could change that for those holes, if desired.

Cheers,
James Arthur

[dagmarg...@yahoo.com]

On Thursday, June 26, 2014 12:34:40 AM UTC-4, rickman wrote:
> On 6/25/2014 11:47 PM, John Larkin wrote:

> > On Wed, 25 Jun 2014 20:04:33 -0700 (PDT), dagmargoo...@yahoo.com wrote:
> >> On Wednesday, June 25, 2014 10:18:32 PM UTC-4, John Larkin wrote:
> >>
> >> Can't. I have room to move about 1/3rd of them, which we certainly will.
> >
> > Dump most of the central ones. They slurp solder but don't help much thermally.
>
> The data you post does not really support your conclusion. You are
> looking at a picture and drawing a conclusion without even considering
> the full design. The question is *not* what does the heat spreader do,
> the question is what do the vias do. The fact that the spreader has a 5
> degree temperature drop says nothing about the temperature drop across
> the vias if you use more or less or where you put them.

That picture doesn't show it, but John's point is that the board's spreading resistance limits the heat launched into the bottom-side copper pour.

It's not nearly as useful to launch heat into the center under the pad,
because there's extra resistance to the larger pour.

R2
| center edge bottom copper pour
| to of pad .-------------
.-----. Via | edge to fill |
| pad |---\/\/\--*--/\/\/---*--/\/\/----*---/\/\/\/\/...
'-----' R1 | of pad R3 |
| '-------------

By connecting directly to the edge you get rid of R2.

Cheers,
James Arthur

[John Larkin]

On Thu, 26 Jun 2014 00:34:40 -0400, rickman <gnu...@gmail.com> wrote:

>On 6/25/2014 11:47 PM, John Larkin wrote:
>> On Wed, 25 Jun 2014 20:04:33 -0700 (PDT), dagmarg...@yahoo.com wrote:
>>
>>> On Wednesday, June 25, 2014 10:18:32 PM UTC-4, John Larkin wrote:
>>>
>>> Can't. I have room to move about 1/3rd of them, which we certainly will.
>>
>> Dump most of the central ones. They slurp solder but don't help much thermally.
>
>The data you post does not really support your conclusion. You are
>looking at a picture and drawing a conclusion without even considering
>the full design. The question is *not* what does the heat spreader do,
>the question is what do the vias do. The fact that the spreader has a 5
>degree temperature drop says nothing about the temperature drop across
>the vias if you use more or less or where you put them.

The vias aren't the dominant thermal resistance; the lateral, spreading thermal
resistance on the bottom side is. A tight cluster of thermal vias, down to a
local hot spot, isn't very effective. The thermals inside the array do almost
nothing but slurp solder.

>
>I believe your test case does not have vias from what I can see, right?

I said (and you snipped) that it was "a vaguely similar case."

But it illustrates how bad the lateral heat spreading is on a bottomside copper
pour.

> I see a temperature drop through the board of 10�C or more. But since
>that is without vias at all, I can't see how it is very relevant.

Gosh, you don't see it!

Do
>you have any idea of the temperature drop through the board with vias?

I calculated about 4 K/W for James's via array. Dumping into a hot spot that
probably has 10 K/W spreading resistance.

That wasn't my point. My point is that, to better cool the dpak, the vias need
to be spread out, not clustered under the chip. And that fixes the solder
scavenging problem, too.

[John Larkin]

On Thu, 26 Jun 2014 00:06:55 -0400, "Tom Miller" <tmille...@verizon.net>
wrote:

We sometimes use some surface-mount heat sinks that straddle a dpak, on the
parts side.

https://dl.dropboxusercontent.com/u/53724080/PCBs/D100_1.jpg

[John Larkin]

The amount of copper in the walls of a via goes linearly on diameter, but the
solder slurp volume goes as d^2. So more small holes helps the solder scavenging
situation.

A 20 mil via, in an 0.062 board, is just about one square, if you unroll it and
hammer it flat. 1 oz copper is about 70 K/W per square.

Most metals run around 140,000 K/W per ohm!

[Tom Miller]

"John Larkin" <jjla...@highNOTlandTHIStechnologyPART.com> wrote in message

news:0ianq95ebll6gtu9c...@4ax.com...

Nice board.

[Joe Chisolm]

On Wed, 25 Jun 2014 17:01:51 -0700, dagmargoodboat wrote:

> On Wednesday, June 25, 2014 7:07:25 PM UTC-4, Joe Chisolm wrote:
>> On Wed, 25 Jun 2014 15:26:31 -0700, dagmargoodboat wrote:
>>
>> > A board house just griped about half a dozen or so thermal vias under
>> > a D-PAK regulator, used to heatsink the device to a groundplane
>> > beneath.
>> >
>> > Their gripe is the vias wick the solder paste out from under the
>> > device.
>> >
>> > The PCB guy had said the vias were standard practice, which is
>> > certainly what I thought too.
>> >
>> > What say yee?
>>
>> We use them all the time (but not D-PAK). There is some wicking but
>> you can compensate with the paste opening.
>
> Paste opening? You mean leave a clearance around the vias in the paste
> mask?
>

The large pad on the D-PAK will normally be windowed, probably
4 "panes". The idea is to make the paste opening (the window panes)
a few mils larger to allow more paste to accommodate the wicking.

As other post have pointed out, you can sometimes get solder
dimples coming out the back side holes. If you need to mount a
heat sink, this will cause problems.

In the grand scheme of things, stencils are not that expensive.
Your board guy can adjust the stencil openings to find the sweet
spot and generate a new paste layer for a new stencil.

> They asked we do that, but it seems the solder would just flow, wet, and
> wick, with less solder to do it all with. Their alternate "ask" was
> filled vias.
>
> I pulled the artwork. There are actually two dozen x .020" thermals.
> More than I remembered, but the holes are small.
>

That's a lot of vias. That pad must look like swiss cheese. What is
your top layer cu thickness? 1/2 oz? Any good planes below the pad
other than the bottom layer?

> All the heatsinking's on the bottom, so tightly-coupled is good.
>
> Thanks for the feedback,
> James Arthur

[rickman]

On 6/26/2014 12:50 AM, dagmarg...@yahoo.com wrote:
> On Wednesday, June 25, 2014 11:28:30 PM UTC-4, rickman wrote:
>>
>> My understanding is that thermal pads get a divided solder paste mask to
>> reduce the solder load by some amount approaching 50% anyway. I believe
>> an unbroken slug of paste has problems with both gasses escaping and the
>> part floating on the big ball of solder. I can't imagine the vias will
>> wick very much in comparison.
>
> It's hard to imagine a slug of paste sitting on via-Swiss-cheese will
> have a venting problem.

I'm not sure what you are saying. The manufacturing people see problems
with thermal pads because the solder paste will splatter on occasion.
The fix is to break the solder paste applied into a grid. I believe
this is a design without thermal vias. Have you not seen this
recommendation? I'm pretty sure the fab house takes my design files and
uses the Gerbers for the board, but tosses the paste layer and makes
their own. Heck, I have a hard time getting them to print the silk
screen without clipping.

>> You said the vias are 0.020, can you make them smaller and use more?
>
> My handy spreadsheet says doubling the holes and cutting the size is a net
> small loss thermally if the vias are solder-filled, but cuts the hole-fill
> volume in half. The copper path is better, but the via-fill path (solder)
> is worse.

So it might make the thermal a bit worse, but it will largely mitigate
the wicking problem? What numbers are you using for the plating inner
and outer diameters?

I'm not sure why your copper would be better. The copper cross section
is essentially the circumference times the plating thickness which would
be the same for twice the number of half sized holes, no?

>> When I was having a board made with 0.013 vias (drill size) I was told
>> they nearly plate shut anyway.
>
> I hope they don't! We're spec'ing finished hole size. But, maybe we
> could change that for those holes, if desired.

Yes, I believe I said I was specing the drill size, not the finished
hole size. Why do you spec the finished hole size rather than the drill
size? Or are you saying you are specing both?

Actually I specified a 0.010" hole size, but both fabs that have made my
boards apply their +-0.003" tolerance spec and drill with a 0.013"
drill. I have no reason to argue with them.

I'm curious, what do you expect your temperature drop through the board
to be? Do you have an expected temperature drop across the spreader?
What is your temperature difference between the spreader and the air?

--

Rick

[rickman]

I can't say I understand what you are drawing. What is "fill"? Doesn't
the via connect directly to the copper pour?

The point being made by John is that there is little use to having
*more* vias in the center. Unless I misunderstood no one is suggesting
there should be no vias around the outside of the pad. The question is
do you just use vias outside the pad where there is no wicking problem
or do you also use vias in the pad where wicking can be a problem.

Did I not read John's post correctly?

--

Rick

[rickman]

On 6/26/2014 1:05 AM, John Larkin wrote:
> On Thu, 26 Jun 2014 00:34:40 -0400, rickman <gnu...@gmail.com> wrote:
>
>> On 6/25/2014 11:47 PM, John Larkin wrote:
>>> On Wed, 25 Jun 2014 20:04:33 -0700 (PDT), dagmarg...@yahoo.com wrote:
>>>
>>>> On Wednesday, June 25, 2014 10:18:32 PM UTC-4, John Larkin wrote:
>>>>
>>>> Can't. I have room to move about 1/3rd of them, which we certainly will.
>>>
>>> Dump most of the central ones. They slurp solder but don't help much thermally.
>>
>> The data you post does not really support your conclusion. You are
>> looking at a picture and drawing a conclusion without even considering
>> the full design. The question is *not* what does the heat spreader do,
>> the question is what do the vias do. The fact that the spreader has a 5
>> degree temperature drop says nothing about the temperature drop across
>> the vias if you use more or less or where you put them.
>
> The vias aren't the dominant thermal resistance; the lateral, spreading thermal
> resistance on the bottom side is. A tight cluster of thermal vias, down to a
> local hot spot, isn't very effective. The thermals inside the array do almost
> nothing but slurp solder.

My point is that analyzing this design by looking for a "dominate"
thermal resistance is not useful. The temperature of the die is the sum
of all the thermal drops and the sink temperature. The final die
temperature depends on them all. If you can lower the die temperature a
few degrees by adding more vias under the pad, that is not a bad thing.

>> I believe your test case does not have vias from what I can see, right?
>
> I said (and you snipped) that it was "a vaguely similar case."
>
> But it illustrates how bad the lateral heat spreading is on a bottomside copper
> pour.

Ok, but that does not indicate anything about what the vias will do.

>> I see a temperature drop through the board of 10�C or more. But since
>> that is without vias at all, I can't see how it is very relevant.
>
> Gosh, you don't see it!
>
> Do
>> you have any idea of the temperature drop through the board with vias?
>
> I calculated about 4 K/W for James's via array. Dumping into a hot spot that
> probably has 10 K/W spreading resistance.

"Probably" means you are guessing, right? But assuming you are right, I
would say the 4 K/W is a pretty important number still since it will
create a temperature drop that is about half the drop across the
temperature drop of the "hot spot".

> That wasn't my point. My point is that, to better cool the dpak, the vias need
> to be spread out, not clustered under the chip. And that fixes the solder
> scavenging problem, too.

How do you get the heat into the vias from the chip....? Oh, I know,
use a heat spreader on the top side!!! Wait, isn't that going to give
you the same result?

In the real world, the vias can be under the chip and work fine. I have
done this myself before. The details you are trying to optimize are
largely irrelevant and end up having little impact on the die temperature.

I know guys who think like you and build fast cars. In the end they get
stuff to work, but only after doing it wrong a few times.

--

Rick

[Tim Williams]

<dagmarg...@yahoo.com> wrote in message
news:a71d13df-94f4-499b...@googlegroups.com...

> They may have a point. I calculate the fill volume of the vias at
> nearly 8mm^3. If we cut the hole size in half and double the
> holes, we'd save 1/2 of that, and gain copper cross section.
>
> But that's a lot of holes. Small ones.
>
> I can move about a third of the holes off-pad.
>
> It's yucky.

Holy hell, how big are these vias?

I normally pepper something like that with, oh, twenty vias in the 10-20
mil diameter range. Around the periphery if possible -- avoids the
problem altogether, but that's really only effective for passive cooling
(copper pours, no heatsinking otherwise really).

Backside heatsinking, you'll need in-pad vias, preferably with enough
solder paste to help out conductivity. But not so much that there's an
excess that bumps out the other side. By capillary action in small enough
vias, you should be able to get enough that the top side fillet looks good
while the vias are filled, more or less just level with the bottom.

I always place vias in exposed pads (DFN/QFN, etc...), using just enough
of them (diameter and count) to account for the extra solder of full paste
coverage (normally, partial coverage is suggested). EPs of course are
much more sensitive to float or starvation than DPAKs, of course.

Haven't had any complaints from manufacturing yet, but... you know how it
is, they'll complain if there's no vias, if there's too many, if they're
tented / capped / plugged, if they're not...

Tim

--
Seven Transistor Labs
Electrical Engineering Consultation
Website: http://seventransistorlabs.com

[dagmarg...@yahoo.com]

On Thursday, June 26, 2014 2:48:25 AM UTC-4, Joe Chisolm wrote:
> On Wed, 25 Jun 2014 17:01:51 -0700, dagmargoodboat wrote:
> > On Wednesday, June 25, 2014 7:07:25 PM UTC-4, Joe Chisolm wrote:
> >> On Wed, 25 Jun 2014 15:26:31 -0700, dagmargoodboat wrote:
> >>
> >> > A board house just griped about half a dozen or so thermal vias under
> >> > a D-PAK regulator, used to heatsink the device to a groundplane
> >> > beneath.
> >> >
> >> > Their gripe is the vias wick the solder paste out from under the
> >> > device.
> >> >
> >> > The PCB guy had said the vias were standard practice, which is
> >> > certainly what I thought too.
> >> >

> >> > What say ye?

> >>
> >> We use them all the time (but not D-PAK). There is some wicking but
> >> you can compensate with the paste opening.
> >
> > Paste opening? You mean leave a clearance around the vias in the paste
> > mask?
>
> The large pad on the D-PAK will normally be windowed, probably
> 4 "panes". The idea is to make the paste opening (the window panes)
> a few mils larger to allow more paste to accommodate the wicking.

I could oversize the paste mask for the D-PAK tab too. That would deposit
more paste. ISTM the "bars" needed to separate the "window" into "panes"
simply reduce the total paste delivered.
.----.----.
|____|____|
| | |
'----'----'

> As other post have pointed out, you can sometimes get solder
> dimples coming out the back side holes. If you need to mount a
> heat sink, this will cause problems.

Makes sense. No heatsink here, though I think, frankly, it could really
use one topside. I've got to query the customer.

> In the grand scheme of things, stencils are not that expensive.
>
> Your board guy can adjust the stencil openings to find the sweet
> spot and generate a new paste layer for a new stencil.

That, and moving some of the thermals out from under the pad are likely the
soldering solution.

> > They asked we do that, but it seems the solder would just flow, wet, and
> > wick, with less solder to do it all with. Their alternate "ask" was
> > filled vias.
> >
> > I pulled the artwork. There are actually two dozen x .020" thermals.
> > More than I remembered, but the holes are small.
>
> That's a lot of vias.

The layout guy's a bit of a character. But on review, it's a pretty
good trade-off thermally, and for total solder-wicking volume.

I wanted fewer and bigger vias; that would've been worse.

> That pad must look like swiss cheese.

You'd think so, but the holes only occupy ~4% of the surface area.

> What is
> your top layer cu thickness? 1/2 oz?

2 oz.

> Any good planes below the pad
> other than the bottom layer?

No.

> > All the heatsinking's on the bottom, so tightly-coupled is good.

Thanks.

Cheers,
James Arthur

[John Larkin]

Don't feel bad. Very few people understand these thermal things.

[dagmarg...@yahoo.com]

On Thursday, June 26, 2014 3:48:13 AM UTC-4, rickman wrote:

> On 6/26/2014 12:50 AM, dagmargoo...@yahoo.com wrote:
> > On Wednesday, June 25, 2014 11:28:30 PM UTC-4, rickman wrote:
> >>
> >> My understanding is that thermal pads get a divided solder paste mask to
> >> reduce the solder load by some amount approaching 50% anyway. I believe
> >> an unbroken slug of paste has problems with both gasses escaping and the
> >> part floating on the big ball of solder. I can't imagine the vias will
> >> wick very much in comparison.
> >
> > It's hard to imagine a slug of paste sitting on via-Swiss-cheese will
> > have a venting problem.
>
> I'm not sure what you are saying. The manufacturing people see problems
> with thermal pads because the solder paste will splatter on occasion.
> The fix is to break the solder paste applied into a grid. I believe
> this is a design without thermal vias. Have you not seen this
> recommendation?

No, I haven't. I've been designing circuits since I was a kid, but
not a whole bunch of SMD power stuff since the dawn of high-power SMD.
Getting rid of the heat is a different matter than the old days, when
heatsinks were de rigueur.

> I'm pretty sure the fab house takes my design files and
> uses the Gerbers for the board, but tosses the paste layer and makes
> their own. Heck, I have a hard time getting them to print the silk
> screen without clipping.
>
> >> You said the vias are 0.020, can you make them smaller and use more?
> >
> > My handy spreadsheet says doubling the holes and cutting the size is a net
> > small loss thermally if the vias are solder-filled, but cuts the hole-fill
> > volume in half. The copper path is better, but the via-fill path (solder)
> > is worse.

>
> So it might make the thermal a bit worse, but it will largely mitigate
> the wicking problem?

I don't know if it solves the hole-fill problem--I don't know what the
board house's process will tolerate. I don't even know who the board house
is.

> What numbers are you using for the plating inner
> and outer diameters?

We don't plate the outer diameters. :-)

0.020" finished hole, 25um Cu walls.

> I'm not sure why your copper would be better. The copper cross section
> is essentially the circumference times the plating thickness which would
> be the same for twice the number of half sized holes, no?

To a first approximation, yes. A more accurate calculation is
pi * (r(outer)^2 - r.(inner)^2), which gives
pi * 2r(outer)*plating + plating^2, which accounts for the difference.

> >> When I was having a board made with 0.013 vias (drill size) I was told
> >> they nearly plate shut anyway.
> >
> > I hope they don't! We're spec'ing finished hole size. But, maybe we
> > could change that for those holes, if desired.
>
> Yes, I believe I said I was specing the drill size, not the finished
> hole size. Why do you spec the finished hole size rather than the drill
> size?

So that the leaded components will fit into their through holes.

> Or are you saying you are specing both?
>
> Actually I specified a 0.010" hole size, but both fabs that have made my
> boards apply their +-0.003" tolerance spec and drill with a 0.013"
> drill. I have no reason to argue with them.
>
> I'm curious, what do you expect your temperature drop through the board
> to be? Do you have an expected temperature drop across the spreader?
>
> What is your temperature difference between the spreader and the air?

I don't have a spreader--that's the bottom layer.

Cheers,
James Arthur

[dagmarg...@yahoo.com]

On Thursday, June 26, 2014 3:55:52 AM UTC-4, rickman wrote:

> On 6/26/2014 1:02 AM, dagmargoo...@yahoo.com wrote:
> > On Thursday, June 26, 2014 12:34:40 AM UTC-4, rickman wrote:
> >> On 6/25/2014 11:47 PM, John Larkin wrote:
> >>> On Wed, 25 Jun 2014 20:04:33 -0700 (PDT), dagmargoo...@yahoo.com wrote:
> >>>> On Wednesday, June 25, 2014 10:18:32 PM UTC-4, John Larkin wrote:
> >>>>
> >>>> Can't. I have room to move about 1/3rd of them, which we certainly will.
> >>>
> >>> Dump most of the central ones. They slurp solder but don't help much thermally.
> >>
> >> The data you post does not really support your conclusion. You are
> >> looking at a picture and drawing a conclusion without even considering
> >> the full design. The question is *not* what does the heat spreader do,
> >> the question is what do the vias do. The fact that the spreader has a 5
> >> degree temperature drop says nothing about the temperature drop across
> >> the vias if you use more or less or where you put them.
> >
> > That picture doesn't show it, but John's point is that the board's spreading resistance limits the heat launched into the bottom-side copper pour.
> >
> > It's not nearly as useful to launch heat into the center under the pad,
> > because there's extra resistance to the larger pour.
> >
> > R2
> > | center edge bottom copper pour
> > | to of pad .-------------

> > .-----. Via | edge to pour |

> > | pad |---\/\/\--*--/\/\/---*--/\/\/----*---/\/\/\/\/...
> > '-----' R1 | of pad R3 |
> > | '-------------
> >
> > By connecting directly to the edge you get rid of R2.
>
> I can't say I understand what you are drawing.

Standard over-simplified thermal resistance "circuit" diagram. Approximates
the resistances to heat flow, broken down by segment.

> What is "fill"?

Same as "pour". Sloppy labeling -- corrected.

> Doesn't the via connect directly to the copper pour?

Yes, but no, that's John's point. It connects to the big pour, but
through a piece of unnecessary copper, namely, on the bottom of the board,
the heat has to traverse from centered under the D-PAK to the edge
of the D-PAK's outline before it gets to the rest of the pour. That adds
thermal resistance, and unnecessarily.

> The point being made by John is that there is little use to having
> *more* vias in the center. Unless I misunderstood no one is suggesting
> there should be no vias around the outside of the pad. The question is
> do you just use vias outside the pad where there is no wicking problem
> or do you also use vias in the pad where wicking can be a problem.
>
> Did I not read John's post correctly?

John was saying I might as well move as many thermals as possible outside
the pad outline. Topside, the device itself has a massive slug of copper
that makes sure heat is evenly spread underneath it. Might as well take
advantage of that.

Cheers,
James Arthur

[dagmarg...@yahoo.com]

On Thursday, June 26, 2014 4:42:44 AM UTC-4, Tim Williams wrote:

> <dagmargoo...@yahoo.com> wrote:
>
> > They may have a point. I calculate the fill volume of the vias at
> > nearly 8mm^3. If we cut the hole size in half and double the
> > holes, we'd save 1/2 of that, and gain copper cross section.
> >
> > But that's a lot of holes. Small ones.
> >
> > I can move about a third of the holes off-pad.
> >
> > It's yucky.
>
> Holy hell, how big are these vias?

.020"

> I normally pepper something like that with, oh, twenty vias in the 10-20
> mil diameter range. Around the periphery if possible -- avoids the
> problem altogether, but that's really only effective for passive cooling
> (copper pours, no heatsinking otherwise really).

That's the case here, and that's roughly the number of holes too.

>
>
>
> Backside heatsinking, you'll need in-pad vias, preferably with enough
> solder paste to help out conductivity. But not so much that there's an
> excess that bumps out the other side. By capillary action in small enough
> vias, you should be able to get enough that the top side fillet looks good
> while the vias are filled, more or less just level with the bottom.

Yep. All of that already discussed & calculated.

Cheers,
James Arthur

[John Larkin]

When making contact to a sheet resistor, the contact resistance trends towards
infinite as the contact diameter trends to zero. So we don't want a spot contact
to the bottom ground pour, we want the biggest circle or square we can get.

I wish I had some friendly software to do sheet resistance calcs. But even that
would be a simplification, because the heat is continuously dissipated to air
across all the surfaces, and significant heat travels from the bottom pour
through the FR4 to the top, where it also dumps into air.

There is serious 3D thermal software that takes everything into account, but
that's $$$ overkill and I suspect the learning curve and setup is extreme. Has
anybody used this sort of program?

I hack thermal breadboards and measure them, with an IR imager and with
thermocouples. And after I make a real board, I measure it, too, for learning
feedback.

This is pretty inexact. We generally don't know the actual copper thickness [1]
and especially the via plating. Part thermal models are often fuzzy. And we
don't often know the exact environment of the board, like convection and
conduction to the enclosure and such, or air flow paths if there is venting or
fans. This stuff is messy.

[1] I like to include test traces, so I can measure resistance and see how much
copper the board house actually provided. I can TDR them, too, to see if I got
trace impedances right. Via resistances can sort of be measured, too, and that
translates to theta.

[Sergey Kubushyn]

dagmarg...@yahoo.com wrote:
> On Thursday, June 26, 2014 4:42:44 AM UTC-4, Tim Williams wrote:
>> <dagmargoo...@yahoo.com> wrote:
>>
>> > They may have a point. I calculate the fill volume of the vias at
>> > nearly 8mm^3. If we cut the hole size in half and double the
>> > holes, we'd save 1/2 of that, and gain copper cross section.
>> >
>> > But that's a lot of holes. Small ones.
>> >
>> > I can move about a third of the holes off-pad.
>> >
>> > It's yucky.
>>
>> Holy hell, how big are these vias?
>
> .020"

This is too big. Every appnote on the subject clearly states that vias can
not be bigger than 12 mils or so (it is 13 mil in TI appnotes if my dementia
serves me right.) It is clearly stated that this is because of solder
wicking problems if bigger vias were used.

Use 12 mils vias. No plugging necessary, just use full solder paste opening
in your stencils (not spot pasting or whatever.) And do NOT tent those vias.
The excessive solder will fill them nicely and surface tension in 12 mil via
is sufficient to hold all solder inside without bleeding to other side.

15 mil vias are on the edge -- there is almost no bleed-through but you'll
get bumps of solder on underside. Most of the time -- sometimes it WILL leak
through. 12 mils is perfect size.

And do NOT tent those vias on the opposite side. It will not plug them to
prevent solder wicking, won't allow proper filling with solder, and those
will give out some gas/vapors/whatever that will force your chip to float
and leave you with numerous voids when solder solidified.

---
******************************************************************
* KSI@home KOI8 Net < > The impossible we do immediately. *
* Las Vegas NV, USA < > Miracles require 24-hour notice. *
******************************************************************

[Jon Elson]

dagmarg...@yahoo.com wrote:



> If we cap the vias and the caps bulge up, holding the part off the board,
> that's a problem.
Once the part has reflowed completely down on the board surface, the
surface tension should pull the solder BACK UP the holes to some extent,
and give good wetting of the part to the pad. You may have to unsolder
a few parts to assure you are getting broad wetting of the part's underside.
Tinkering with the solder stencil aperture is pretty much required the
first time you do something like this.

Jon

[Joe Chisolm]

We had a real pain with a QFN. There was just a little too much
paste and it would float just high enough that 1 or 2 of the pads
would sometimes not solder correctly. The others would, so the chip
would align correctly. Sometimes the board would just not work,
other times intermittent. Making the windows smaller fixed that
issue.

>> In the grand scheme of things, stencils are not that expensive.
>>
>> Your board guy can adjust the stencil openings to find the sweet spot
>> and generate a new paste layer for a new stencil.
>
> That, and moving some of the thermals out from under the pad are likely
> the soldering solution.
>

That 2oz Cu on the top should also help with this. Like others have
mentioned, spread the heat out and then down to the bottom. Once
you get out of the paste zone you could use larger vias if the real
estate will allow.

>> > They asked we do that, but it seems the solder would just flow, wet,
>> > and wick, with less solder to do it all with. Their alternate "ask"
>> > was filled vias.
>> >
>> > I pulled the artwork. There are actually two dozen x .020" thermals.
>> > More than I remembered, but the holes are small.
>>
>> That's a lot of vias.
>
> The layout guy's a bit of a character. But on review, it's a pretty
> good trade-off thermally, and for total solder-wicking volume.
>
> I wanted fewer and bigger vias; that would've been worse.
>
>> That pad must look like swiss cheese.
>
> You'd think so, but the holes only occupy ~4% of the surface area.
>
>> What is
>> your top layer cu thickness? 1/2 oz?
>
> 2 oz.
>
>> Any good planes below the pad
>> other than the bottom layer?
>
> No.
>
>> > All the heatsinking's on the bottom, so tightly-coupled is good.
>
> Thanks.
>
> Cheers,
> James Arthur

[rickman]

On 6/26/2014 10:53 AM, dagmarg...@yahoo.com wrote:
> On Thursday, June 26, 2014 3:48:13 AM UTC-4, rickman wrote:
>> What numbers are you using for the plating inner
>> and outer diameters?
>
> We don't plate the outer diameters. :-)
>
> 0.020" finished hole, 25um Cu walls.

It's been a while since I've worked with copper thicknesses. I had
forgotten how thin it often is. I see now that with solder in the holes
the thermal resistance will be much lower.

>> I'm not sure why your copper would be better. The copper cross section
>> is essentially the circumference times the plating thickness which would
>> be the same for twice the number of half sized holes, no?
>
> To a first approximation, yes. A more accurate calculation is
> pi * (r(outer)^2 - r.(inner)^2), which gives
> pi * 2r(outer)*plating + plating^2, which accounts for the difference.

Do you mean
pi * 2r(inner)*plating + plating^2

Even at an inner diameter of 10 mil and a plating thickness of 1 mil,
your difference in copper cross section is *very* small, less than 5%.
Isn't that rather in the noise?

>> Yes, I believe I said I was specing the drill size, not the finished
>> hole size. Why do you spec the finished hole size rather than the drill
>> size?
>
> So that the leaded components will fit into their through holes.

Ok. I suppose there are always some through hold parts somewhere on a
board. I can't think of anything I typically use that isn't a connector
where the holes have enough slack that this isn't a problem. Different
strokes...

>> Or are you saying you are specing both?
>>
>> Actually I specified a 0.010" hole size, but both fabs that have made my
>> boards apply their +-0.003" tolerance spec and drill with a 0.013"
>> drill. I have no reason to argue with them.
>>
>> I'm curious, what do you expect your temperature drop through the board
>> to be? Do you have an expected temperature drop across the spreader?
>>
>> What is your temperature difference between the spreader and the air?
>
> I don't have a spreader--that's the bottom layer.

Yes, the bottom layer is your spreader. Do you know what to expect for
all the temperature drops? Not much point in optimizing one portion of
the design if you don't know what the rest will do. Do you have target
temperature drops?

--

Rick

[rickman]

That much I understand. The question is what are the segments you have
drawn.

>> What is "fill"?
>
> Same as "pour". Sloppy labeling -- corrected.

Ok, I would have understood if it was "copper pour" except that the
entire R2 through R4 is the same copper pour. Seems to me the value of
R3 is zero. What is the nature of R3?

>> Doesn't the via connect directly to the copper pour?
>
> Yes, but no, that's John's point. It connects to the big pour, but
> through a piece of unnecessary copper, namely, on the bottom of the board,
> the heat has to traverse from centered under the D-PAK to the edge
> of the D-PAK's outline before it gets to the rest of the pour. That adds
> thermal resistance, and unnecessarily.

That is the crux of the issue. The heat has to be spread by something.
If R2 is not in the bottom copper pour, it is in the top layer copper
pour. It doesn't go away by moving the vias, the order is just changed.
R1-R2-R3... or R2-R1-R3...

>> The point being made by John is that there is little use to having
>> *more* vias in the center. Unless I misunderstood no one is suggesting
>> there should be no vias around the outside of the pad. The question is
>> do you just use vias outside the pad where there is no wicking problem
>> or do you also use vias in the pad where wicking can be a problem.
>>
>> Did I not read John's post correctly?
>
> John was saying I might as well move as many thermals as possible outside
> the pad outline. Topside, the device itself has a massive slug of copper
> that makes sure heat is evenly spread underneath it. Might as well take
> advantage of that.

That is not what I read. I thought he was saying just don't use vias
inside the pad outline. Certainly it helps to add vias outside, but
getting rid of the vias inside does not improve your situation unless
you just can't figure out how to deal with the wicking. I think John is
very mistaken to suggest there is no value to them. All the vias are in
parallel and the spreading has to be done on one side of the board or
the other.

Look at it this way. Do the chip makers provide a ring for the thermal
pad? If the spreading was of no value in the middle I expect they
wouldn't use a full pad.

Until you figure out your temperature drops you won't really know what
is useful and what isn't.

--

Rick

[rickman]

That part I am very aware of. At least I know one person who doesn't
get it.

--

Rick

[dagmarg...@yahoo.com]

On Thursday, June 26, 2014 3:10:03 PM UTC-4, Jon Elson wrote:

I've got no control or even access to the boards.

It's nuts, but that's how it is.

Cheers,
James Arthur

[dagmarg...@yahoo.com]

On Thursday, June 26, 2014 3:11:23 PM UTC-4, Joe Chisolm wrote:

> Once you get out of the paste zone you could use larger vias if the real
> estate will allow.

Good idea. Thanks.

[rickman]

Are you using the same thickness on the bottom? I thought I read you
had 1 oz there.

--

Rick

[dagmarg...@yahoo.com]

On Thursday, June 26, 2014 11:11:12 PM UTC-4, rickman wrote:

> On 6/26/2014 10:53 AM, dagmargood...@yahoo.com wrote:
> > On Thursday, June 26, 2014 3:48:13 AM UTC-4, rickman wrote:
> >> What numbers are you using for the plating inner
> >> and outer diameters?
> >
> > We don't plate the outer diameters. :-)
> >
> > 0.020" finished hole, 25um Cu walls.
>
> It's been a while since I've worked with copper thicknesses. I had
> forgotten how thin it often is. I see now that with solder in the holes
> the thermal resistance will be much lower.
>
> >> I'm not sure why your copper would be better. The copper cross section
> >> is essentially the circumference times the plating thickness which would
> >> be the same for twice the number of half sized holes, no?
> >
> > To a first approximation, yes. A more accurate calculation is
> > pi * (r(outer)^2 - r.(inner)^2), which gives
> > pi * 2r(outer)*plating + plating^2, which accounts for the difference.
>
> Do you mean
>
> pi * 2r(inner)*plating + plating^2

Yep. Transcription error. Thanks.

> Even at an inner diameter of 10 mil and a plating thickness of 1 mil,
> your difference in copper cross section is *very* small, less than 5%.
> Isn't that rather in the noise?

It's not terribly significant. Two dozen filled 0.020" vias in parallel
yield 2.4 K/W; four dozen filled 0.010 vias gives 2.9 K/W, plus a bunch
of holes to drill.

The 0.010" array has lower copper K/W, but much higher fill K/W due to
the halved fill volume.

> >> Yes, I believe I said I was specing the drill size, not the finished
> >> hole size. Why do you spec the finished hole size rather than the drill
> >> size?
> >
> > So that the leaded components will fit into their through holes.
>
>
> Ok. I suppose there are always some through hold parts somewhere on a
> board. I can't think of anything I typically use that isn't a connector
> where the holes have enough slack that this isn't a problem. Different
> strokes...
>
>
> >> Or are you saying you are specing both?
> >>
> >> Actually I specified a 0.010" hole size, but both fabs that have made my
> >> boards apply their +-0.003" tolerance spec and drill with a 0.013"
> >> drill. I have no reason to argue with them.
> >>
> >> I'm curious, what do you expect your temperature drop through the board
> >> to be? Do you have an expected temperature drop across the spreader?
> >>
> >> What is your temperature difference between the spreader and the air?
> >
> > I don't have a spreader--that's the bottom layer.
>
> Yes, the bottom layer is your spreader. Do you know what to expect for
> all the temperature drops? Not much point in optimizing one portion of
> the design if you don't know what the rest will do. Do you have target
> temperature drops?

The immediate problem isn't re-doing the thermal design, simply solving
the soldering problem.

The original design was mine, and mass-produced. Now the customer has
changed the usage and inserted a modification. I'm not privy to the
requirements, I'm just solving the new soldering problem relative to the
new mod.

Cheers,
James Arthur

[dagmarg...@yahoo.com]

On Thursday, June 26, 2014 11:29:02 PM UTC-4, rickman wrote:

> On 6/26/2014 10:33 AM, dagmargoo...@yahoo.com wrote:
> > On Thursday, June 26, 2014 2:48:25 AM UTC-4, Joe Chisolm wrote:
> >
> >> What is
> >> your top layer cu thickness? 1/2 oz?
> >
> > 2 oz.
>
> Are you using the same thickness on the bottom? I thought I read you
> had 1 oz there.

2 oz., top and bottom.

Cheers,
James Arthur

[dagmarg...@yahoo.com]

FYI, John's no hacker. He's one of the most disciplined, knowledgeable,
proficient engineers on the planet, and specifically expert in thermal
design, from long years of practice and rigorous investigation(s).

You might want to drag up his FAQ "Notes on Cooling Electronics", posted
here in SED a few years ago.

Cheers,
James Arthur

[Phil Hobbs]

July 1998, and bitter chill it was. ;)

Cheers

Phil Hobbs


--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

[John Larkin]

On Fri, 27 Jun 2014 06:31:22 -0700 (PDT), dagmarg...@yahoo.com wrote:

>On Thursday, June 26, 2014 4:05:33 AM UTC-4, rickman wrote:
>> On 6/26/2014 1:05 AM, John Larkin wrote:
>
>> > That wasn't my point. My point is that, to better cool the dpak, the vias need
>> > to be spread out, not clustered under the chip. And that fixes the solder
>> > scavenging problem, too.
>>
>> How do you get the heat into the vias from the chip....? Oh, I know,
>> use a heat spreader on the top side!!! Wait, isn't that going to give
>> you the same result?
>>
>> In the real world, the vias can be under the chip and work fine. I have
>> done this myself before. The details you are trying to optimize are
>> largely irrelevant and end up having little impact on the die temperature.
>>
>> I know guys who think like you and build fast cars. In the end they get
>> stuff to work, but only after doing it wrong a few times.
>
>FYI, John's no hacker. He's one of the most disciplined, knowledgeable,
>proficient engineers on the planet, and specifically expert in thermal
>design, from long years of practice and rigorous investigation(s).

My thermal designs are a lot of guesswork and experimenting, but they all work.
"Work" is sort of arbitrary, because they don't often blow things up; my thermal
design errors at most result in higher than preferred junction temperatures,
which degrades analog accuracy and MTBF, which are sort of fuzzy criteria
anyhow.

I don't have the tools to do hard analytical thermal design, and all the
required inputs aren't often available anyhow. The sorts of simple calculations
that we are doing here, like calculating the theta of a PTH, are good enough.
Simple experiments, and measurements on existing products, add some confidence.

Forced-air cooling is the hardest thing to predict, because air flow is peverse.
We build cardboard mockups, with power resistors on heat sinks, if we think
cooling is going to be critical. Hey, I'm an engineer, I'm not writing a thesus.

My last major thermal adventure was bringing down the temperature of an FPGA and
a 250 MHz ADC on a small data acquisition box. I didn't want to do it (I figured
and measured that junction temps were fine) but the customer insisted, something
silly about the MTBF of a bunch of $1.2e8 machines. The "fix" was vias and
copper pours on the PCB, and a Bergquist non-silicone therma-pad under the PCB,
which dropped the board temp about 14C. I did learn some things, so it wasn't a
wasted effort.

One fun thing was to program a ring oscillator inside the FPGA and calibrate
that as an on-chip temperature sensor. I posted about that here and in the fpga
newsgroup. Here's the board:

https://dl.dropboxusercontent.com/u/53724080/PCBs/ESM_rev_B.jpg


We make a couple of boxes that measure heatsink temp and mosfet current and
voltages, and run a realtime simulation of junction temperature, shutting down
if it looks too high. That lets us push the fets harder than a foldback current
limit would. We've generally done that in a uP, but I recently did the same with
an analog computer, also posted here. The analog was more fun... no code to
grind out.

It's impressive how much effort we put into thermal design and testing.

>
>You might want to drag up his FAQ "Notes on Cooling Electronics", posted
>here in SED a few years ago.

I should expand that into a pretty PDF some day. Actually, I should hire a scut
bunny, put up a good rant-filled web site, and maybe write a book. Too much to
design just now.

[Jasen Betts]

On 2014-06-26, John Larkin <jjla...@highNOTlandTHIStechnologyPART.com> wrote:
> On Thu, 26 Jun 2014 08:03:47 -0700 (PDT), dagmarg...@yahoo.com wrote:
>
>
> When making contact to a sheet resistor, the contact resistance trends towards
> infinite as the contact diameter trends to zero. So we don't want a spot contact
> to the bottom ground pour, we want the biggest circle or square we can get.

that seems good, but you have the same problem on the top side of the
PCB btweeen the hot part of the device and the vias.

but putting some viae under the hot tab takes some of the heat through
to the back side which will reduce some of the resistance


A B
/ /
[TAB]/ /
-----------------
)###||####||#||####||###)
(####||####||#||####||##(
-----------------------
\ \
\ \
C D

So some heat goes through C and some through B
Ok I've convinced myself that'll help.









--
umop apisdn


--- news://freenews.netfront.net/ - complaints: ne...@netfront.net ---

[rickman]

Finally a rational voice. :)

--

Rick

[rickman]

Most of the design issues I have discussed with John have been exactly
about hacking rather than designing. This one is a great example. Here
he is drawing a picture and trying to understand the working and getting
a wrong answer. His original statement that I am trying to get him to
discuss was,

"The vias in the interior of the array are doing almost no good, because
they are in the middle of a hot spot."

He continues to insist that moving the vias outside the footprint of the
part is an advantage because they are outside the hot spot and the heat
will spread better. But he ignores that there is still the same hot
spot on the top side of the board and posts photos of an example which
doesn't even have vias and can't be considered without more info.

I'm sure John is no slouch, but he is guilty of doing a cursory
examination of this design issue and I can't see where his conclusions
are valid. I see no evidence of "rigorous investigation" in this case.

--

Rick

[Lasse Langwadt Christensen]

I think the point is the that top side isn't the same sheet resistance
it is "shorted" by the tap which is thick copper and much lower thermal
resistance

+-rtab-+-rtab-+
------------+-rpcb-+-rpcb-+-------------
| | |
rvia rvia rvia
| | |
------------+-rpcb-+-rpcb-+-------------



-Lasse

[k...@attt.bizz]

==========================================================

(####||####||#||####||##(
-----------------------
\ \
\ \
C D

A heavy ground plane works, too. Of course it's sandwiched between
more FR4 but it does spread the heat around the board. This, of
course, requires that the tab be grounded (it usually is for ICs). The
really high power ICs have the slug up, meant to have some serious
heat sinking. These also tend to be grounded, so heat sinking is
relatively easy.

[John Larkin]

On Sun, 29 Jun 2014 11:11:41 -0400, rickman <gnu...@gmail.com> wrote:

>On 6/28/2014 8:45 AM, Jasen Betts wrote:
>> On 2014-06-26, John Larkin <jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>>> On Thu, 26 Jun 2014 08:03:47 -0700 (PDT), dagmarg...@yahoo.com wrote:
>>>
>>>
>>> When making contact to a sheet resistor, the contact resistance trends towards
>>> infinite as the contact diameter trends to zero. So we don't want a spot contact
>>> to the bottom ground pour, we want the biggest circle or square we can get.
>>
>> that seems good, but you have the same problem on the top side of the
>> PCB btweeen the hot part of the device and the vias.

That's not bad. Lots of vias down to cool spots on the bottom plane, fairly low
thermal resistances from the chip to those many topside vias. Add an inner-layer
spreader patch if you can.

>>
>> but putting some viae under the hot tab takes some of the heat through
>> to the back side which will reduce some of the resistance
>>
>>
>> A B
>> / /
>> [TAB]/ /
>> -----------------
>> )###||####||#||####||###)
>> (####||####||#||####||##(
>> -----------------------
>> \ \
>> \ \
>> C D
>>
>> So some heat goes through C and some through B
>> Ok I've convinced myself that'll help.
>
>Finally a rational voice. :)

It's what I said some days ago: a few vias under the part, and a topside copper
pour to more vias surrounding the part. That enlarges the thermal footprint on
the bottomside copper pour, and reduces the spreading resistance, which
dominated the original design.

The topside copper pour will be efficient in moving heat to the outer vias,
mostly because the copper run is short and those vias will not be concentrated
into a hot spot. Like this:

https://dl.dropboxusercontent.com/u/53724080/Thermal/ESM_Thermal_Vias.jpg

https://dl.dropboxusercontent.com/u/53724080/Thermal/ESM_Thermal_IR.jpg

(regulator is lower-right in the IR image)

This worked.

This is a dpak with all its thermal vias outside the pad

https://dl.dropboxusercontent.com/u/53724080/Thermal/T165_Dpak_Vias.jpg

where the grey is the topside pour. There's a biggish pour on the bottom, layer
4, too. The upper and lower pours also conduct heat, through the insulating FR4,
into the inner-layer ground (L2) and power (L3) planes, which help spread it out
to the entire surface of the board.

It's better thermally for hot chips to be inboard, but other considerations tend
to push regulators towards the edges of the board.

[John Larkin]

A bunch of vias outside the chip pad works well, assuming there are many of them
and that they are close to the pad. The thermal resistance of the copper from
the pad to each such via will be similar to the theta of the via itself, and
there can be lots of them, each dumping into a relatively cool part of the pour
on the opposite side. On a small part like a dpak, that works a lot better than
having a cluster of vias under the pad and a corresponding hot spot on the
bottomside pour.

Try it.

Lowering thermal resistance is just like lowering electrical resistance: the
more conductive paths in parallel, the lower the net resistance. The lower the
temperature, the better the MTBF of the chips.

>
>I'm sure John is no slouch, but he is guilty of doing a cursory
>examination of this design issue and I can't see where his conclusions
>are valid. I see no evidence of "rigorous investigation" in this case.

I've done hundreds of board designs where part cooling matters. I do math, I
build prototypes, I instrument the real PCBs, I measure and learn. It's been a
really long time since I let a part on a PCB get too hot.

As an engineer, I just need things to work. I'm not writing a thesus that I have
to defend, and I don't have the tools or the time to do a full 3D thermal
conduction/convection/radiation analysis of every chip on every PC board. What I
do works, and things get about as hot as I expected them to get.

[John Larkin]

On Sun, 29 Jun 2014 08:55:06 -0700 (PDT), Lasse Langwadt Christensen
<lang...@fonz.dk> wrote:

Right. The thermal pad on the dpak is thick, and will be nearly isothermal. So,
on a topside pour, each of the many thermal vias, close to but not under the
pad, can be tightly coupled to the chip.

[rickman]

On 6/29/2014 1:58 PM, John Larkin wrote:
>
> It's what I said some days ago: a few vias under the part, and a topside copper
> pour to more vias surrounding the part. That enlarges the thermal footprint on
> the bottomside copper pour, and reduces the spreading resistance, which
> dominated the original design.

You have said a lot of things. The part of your earlier post I was
disagreeing on was, "The vias in the interior of the array are doing

almost no good, because they are in the middle of a hot spot."

I suppose "almost no good" is very similar to "some good" which is the
reality. The images you posted actually make my point. The hot spot
shown in your last image of the underside of the board from your earlier
post show about a 10�C drop through the board. The vias mitigate this
drop *even if they are in the middle of the hot spot*. The temperature
drop across the copper in the hot spot is perhaps 1 or 2�C as shown in
your own images. Regardless, each extra via in the hot spot will help
to reduce the die temperature.

--

Rick

[John Larkin]

On Sun, 29 Jun 2014 15:23:04 -0400, rickman <gnu...@gmail.com> wrote:

>On 6/29/2014 1:58 PM, John Larkin wrote:
>>
>> It's what I said some days ago: a few vias under the part, and a topside copper
>> pour to more vias surrounding the part. That enlarges the thermal footprint on
>> the bottomside copper pour, and reduces the spreading resistance, which
>> dominated the original design.
>
>You have said a lot of things. The part of your earlier post I was
>disagreeing on was, "The vias in the interior of the array are doing
>almost no good, because they are in the middle of a hot spot."

I think that's true. The array in question was a *lot* of vias interior to a
dpak pad. The via zone on the bottom will be a nearly isothermal hot spot, so
the vias interior to that array won't conduct much heat.

>
>I suppose "almost no good" is very similar to "some good" which is the
>reality.

Maybe we can agree on "not much good" ?

The images you posted actually make my point. The hot spot
>shown in your last image of the underside of the board from your earlier
>post show about a 10�C drop through the board. The vias mitigate this
>drop *even if they are in the middle of the hot spot*.

Sure, but the dominant thermal resistance won't be the vias, it will be the
spreading resistance of the bottomside copper. Adding vias outside the dpak
footpring will halp a lot, and they're free, if you think about them up-front.

The temperature
>drop across the copper in the hot spot is perhaps 1 or 2�C as shown in
>your own images. Regardless, each extra via in the hot spot will help
>to reduce the die temperature.

Look again:

https://dl.dropboxusercontent.com/u/53724080/Thermal/T750_t5.jpg

The hot spot is 38C, and half an inch away, the yellow stuff is about 32.

[rickman]

On 6/29/2014 3:49 PM, John Larkin wrote:
> On Sun, 29 Jun 2014 15:23:04 -0400, rickman <gnu...@gmail.com> wrote:
>
>> On 6/29/2014 1:58 PM, John Larkin wrote:
>>>
>>> It's what I said some days ago: a few vias under the part, and a topside copper
>>> pour to more vias surrounding the part. That enlarges the thermal footprint on
>>> the bottomside copper pour, and reduces the spreading resistance, which
>>> dominated the original design.
>>
>> You have said a lot of things. The part of your earlier post I was
>> disagreeing on was, "The vias in the interior of the array are doing
>> almost no good, because they are in the middle of a hot spot."
>
> I think that's true. The array in question was a *lot* of vias interior to a
> dpak pad. The via zone on the bottom will be a nearly isothermal hot spot, so
> the vias interior to that array won't conduct much heat.

You can't really substantiate that claim about the hot spot being
isothermal. It shows as the highest temperature on your imager, but
that simply means it is the max temp *or hotter*. Maybe the thermal
imager automatically sets the range appropriately, but the resolution is
poor so I seriously doubt the spot is isothermal enough to show no
useful heat flow.

>> I suppose "almost no good" is very similar to "some good" which is the
>> reality.
>
> Maybe we can agree on "not much good" ?

?

> The images you posted actually make my point. The hot spot
>> shown in your last image of the underside of the board from your earlier
>> post show about a 10�C drop through the board. The vias mitigate this
>> drop *even if they are in the middle of the hot spot*.
>
> Sure, but the dominant thermal resistance won't be the vias, it will be the
> spreading resistance of the bottomside copper. Adding vias outside the dpak
> footpring will halp a lot, and they're free, if you think about them up-front.

You have not shown that at all. If you want to make a claim about the
"dominant" thermal resistance you need to show this somehow, by
measurement or analysis. So far your analysis has been far too thin to
be useful.

> The temperature
>> drop across the copper in the hot spot is perhaps 1 or 2�C as shown in
>> your own images. Regardless, each extra via in the hot spot will help
>> to reduce the die temperature.
>
> Look again:
>
> https://dl.dropboxusercontent.com/u/53724080/Thermal/T750_t5.jpg
>
> The hot spot is 38C, and half an inch away, the yellow stuff is about 32.

Yes? So the heat flow is due to a 6�C change across a low thermal
resistance. I'd say there is significant heat flow. But in reality
this is not a useful image because there are no vias and no copper on top.

--

Rick

[John Larkin]

On Sun, 29 Jun 2014 20:37:05 -0400, rickman <gnu...@gmail.com> wrote:

>On 6/29/2014 3:49 PM, John Larkin wrote:
>> On Sun, 29 Jun 2014 15:23:04 -0400, rickman <gnu...@gmail.com> wrote:
>>
>>> On 6/29/2014 1:58 PM, John Larkin wrote:
>>>>
>>>> It's what I said some days ago: a few vias under the part, and a topside copper
>>>> pour to more vias surrounding the part. That enlarges the thermal footprint on
>>>> the bottomside copper pour, and reduces the spreading resistance, which
>>>> dominated the original design.
>>>
>>> You have said a lot of things. The part of your earlier post I was
>>> disagreeing on was, "The vias in the interior of the array are doing
>>> almost no good, because they are in the middle of a hot spot."
>>
>> I think that's true. The array in question was a *lot* of vias interior to a
>> dpak pad. The via zone on the bottom will be a nearly isothermal hot spot, so
>> the vias interior to that array won't conduct much heat.
>
>You can't really substantiate that claim about the hot spot being
>isothermal. It shows as the highest temperature on your imager, but
>that simply means it is the max temp *or hotter*.

Of course the hot spot is the hottest temperature! That deserves a big DUH!

Maybe the thermal
>imager automatically sets the range appropriately,

There's that bar graph thingie on the side.

but the resolution is
>poor so I seriously doubt the spot is isothermal enough to show no
>useful heat flow.

6 degs C gradient from hot spot to nearby copper, with 1 watt dissipated on the
opposite side.

>
>
>>> I suppose "almost no good" is very similar to "some good" which is the
>>> reality.
>>
>> Maybe we can agree on "not much good" ?
>
>?
>
>> The images you posted actually make my point. The hot spot
>>> shown in your last image of the underside of the board from your earlier
>>> post show about a 10�C drop through the board. The vias mitigate this
>>> drop *even if they are in the middle of the hot spot*.
>>
>> Sure, but the dominant thermal resistance won't be the vias, it will be the
>> spreading resistance of the bottomside copper. Adding vias outside the dpak
>> footpring will halp a lot, and they're free, if you think about them up-front.
>
>You have not shown that at all. If you want to make a claim about the
>"dominant" thermal resistance you need to show this somehow, by
>measurement or analysis. So far your analysis has been far too thin to
>be useful.

It's useful because all of my designs work.

>
>
>> The temperature
>>> drop across the copper in the hot spot is perhaps 1 or 2�C as shown in
>>> your own images. Regardless, each extra via in the hot spot will help
>>> to reduce the die temperature.
>>
>> Look again:
>>
>> https://dl.dropboxusercontent.com/u/53724080/Thermal/T750_t5.jpg
>>
>> The hot spot is 38C, and half an inch away, the yellow stuff is about 32.
>
>Yes? So the heat flow is due to a 6�C change across a low thermal
>resistance. I'd say there is significant heat flow.

Well, it's a bit under 1 watt, since the resistors on top are dissipating 1
watt. So the theta of that hot spot is at least 6 K/W, probably more. James and
I estimated that his via field was about 4 K/W. So the spreading resistance is
more than the via resistance.

But in reality
>this is not a useful image because there are no vias and no copper on top.

It demonstrates typical thermal spreading resistance in a copper plane. That
sounds like useful info to me.

Do you do much electronic thermal design? Show us some.

[George Herold]

On Friday, June 27, 2014 11:35:55 AM UTC-4, John Larkin wrote:
> On Fri, 27 Jun 2014 06:31:22 -0700 (PDT), dagmarg...@yahoo.com wrote:
>

<snip>

>
> It's impressive how much effort we put into thermal design and testing.
>
> >
> >You might want to drag up his FAQ "Notes on Cooling Electronics", posted
> >here in SED a few years ago.
>
> I should expand that into a pretty PDF some day. Actually, I should hire a scut

Nice, I found it.
(Notes on cooling...)

I would add that surface contact resistance can be a pain.
And dominate the total thermal resistance.
A standard hex 1/4 inch stand off (nickel plated brass) 4-40 hole,
screwed into a copper plate has a junction resistance of ~5 (Thermal) ohms
thermal ohms=deg K/ watt. (or worse if not tightened "properly")
(that's with no goop in the gap.)

Re: electrical-thermal modleling
Charge = Joule and so,
Capacitance (Farad) = Q/V = Joule/deg. K (the heat capacity)

The 1 gram of Aluminum is a nice number, but obscures the correspondence.

(Oh and everything has a heat capacity of about 3 J/cm^3... heat capacity scales with volume not with the mass (density) of stuff.)

George H.

[rickman]

On 6/29/2014 9:48 PM, John Larkin wrote:
> On Sun, 29 Jun 2014 20:37:05 -0400, rickman <gnu...@gmail.com> wrote:
>
>> On 6/29/2014 3:49 PM, John Larkin wrote:
>>> On Sun, 29 Jun 2014 15:23:04 -0400, rickman <gnu...@gmail.com> wrote:
>>>
>>>> On 6/29/2014 1:58 PM, John Larkin wrote:
>>>>>
>>>>> It's what I said some days ago: a few vias under the part, and a topside copper
>>>>> pour to more vias surrounding the part. That enlarges the thermal footprint on
>>>>> the bottomside copper pour, and reduces the spreading resistance, which
>>>>> dominated the original design.
>>>>
>>>> You have said a lot of things. The part of your earlier post I was
>>>> disagreeing on was, "The vias in the interior of the array are doing
>>>> almost no good, because they are in the middle of a hot spot."
>>>
>>> I think that's true. The array in question was a *lot* of vias interior to a
>>> dpak pad. The via zone on the bottom will be a nearly isothermal hot spot, so
>>> the vias interior to that array won't conduct much heat.
>>
>> You can't really substantiate that claim about the hot spot being
>> isothermal. It shows as the highest temperature on your imager, but
>> that simply means it is the max temp *or hotter*.
>
> Of course the hot spot is the hottest temperature! That deserves a big DUH!

There is the big problem. You don't listen! Max temperature meaning
max of the camera range. Saturation. No distinction about temperature
within the hot spot.

> Maybe the thermal
>> imager automatically sets the range appropriately,
>
> There's that bar graph thingie on the side.

You mean the display? Do you set the range or does the camera?

> but the resolution is
>> poor so I seriously doubt the spot is isothermal enough to show no
>> useful heat flow.
>
> 6 degs C gradient from hot spot to nearby copper, with 1 watt dissipated on the
> opposite side.

And I believe over 10 degrees between the two sides. But what is the
range of temperature *within* the hot spot. Your camera shows it as
isothermal, but that can be due to saturation. You have to use the
device properly to get useful info.

>>>> I suppose "almost no good" is very similar to "some good" which is the
>>>> reality.
>>>
>>> Maybe we can agree on "not much good" ?
>>
>> ?
>>
>>> The images you posted actually make my point. The hot spot
>>>> shown in your last image of the underside of the board from your earlier
>>>> post show about a 10�C drop through the board. The vias mitigate this
>>>> drop *even if they are in the middle of the hot spot*.
>>>
>>> Sure, but the dominant thermal resistance won't be the vias, it will be the
>>> spreading resistance of the bottomside copper. Adding vias outside the dpak
>>> footpring will halp a lot, and they're free, if you think about them up-front.
>>
>> You have not shown that at all. If you want to make a claim about the
>> "dominant" thermal resistance you need to show this somehow, by
>> measurement or analysis. So far your analysis has been far too thin to
>> be useful.
>
> It's useful because all of my designs work.

You said this was a test board. So that point is moot.

>>> The temperature
>>>> drop across the copper in the hot spot is perhaps 1 or 2�C as shown in
>>>> your own images. Regardless, each extra via in the hot spot will help
>>>> to reduce the die temperature.
>>>
>>> Look again:
>>>
>>> https://dl.dropboxusercontent.com/u/53724080/Thermal/T750_t5.jpg
>>>
>>> The hot spot is 38C, and half an inch away, the yellow stuff is about 32.
>>
>> Yes? So the heat flow is due to a 6�C change across a low thermal
>> resistance. I'd say there is significant heat flow.
>
> Well, it's a bit under 1 watt, since the resistors on top are dissipating 1
> watt. So the theta of that hot spot is at least 6 K/W, probably more. James and
> I estimated that his via field was about 4 K/W. So the spreading resistance is
> more than the via resistance.

Which actually means they are in the same ballpark and so even a
moderate change in either one will impact the overall result.

> But in reality
>> this is not a useful image because there are no vias and no copper on top.
>
> It demonstrates typical thermal spreading resistance in a copper plane. That
> sounds like useful info to me.
>
> Do you do much electronic thermal design? Show us some.

So your work can't stand on its own? You make claims that are *not*
substantiated by the info you post and in fact so far everything you
have provided shows the vias under the pad *will* have a useful impact
on the result.

--

Rick

[John Larkin]

On Mon, 30 Jun 2014 22:32:27 -0400, rickman <gnu...@gmail.com> wrote:

>On 6/29/2014 9:48 PM, John Larkin wrote:
>> On Sun, 29 Jun 2014 20:37:05 -0400, rickman <gnu...@gmail.com> wrote:
>>
>>> On 6/29/2014 3:49 PM, John Larkin wrote:
>>>> On Sun, 29 Jun 2014 15:23:04 -0400, rickman <gnu...@gmail.com> wrote:
>>>>
>>>>> On 6/29/2014 1:58 PM, John Larkin wrote:
>>>>>>
>>>>>> It's what I said some days ago: a few vias under the part, and a topside copper
>>>>>> pour to more vias surrounding the part. That enlarges the thermal footprint on
>>>>>> the bottomside copper pour, and reduces the spreading resistance, which
>>>>>> dominated the original design.
>>>>>
>>>>> You have said a lot of things. The part of your earlier post I was
>>>>> disagreeing on was, "The vias in the interior of the array are doing
>>>>> almost no good, because they are in the middle of a hot spot."
>>>>
>>>> I think that's true. The array in question was a *lot* of vias interior to a
>>>> dpak pad. The via zone on the bottom will be a nearly isothermal hot spot, so
>>>> the vias interior to that array won't conduct much heat.
>>>
>>> You can't really substantiate that claim about the hot spot being
>>> isothermal. It shows as the highest temperature on your imager, but
>>> that simply means it is the max temp *or hotter*.
>>
>> Of course the hot spot is the hottest temperature! That deserves a big DUH!
>
>There is the big problem. You don't listen! Max temperature meaning
>max of the camera range. Saturation. No distinction about temperature
>within the hot spot.

The FLIR can measure up to 250C or some such. In the mode that I used it, it
automatically scales the temperature bar to the min and max temps in the field
of view. It's not saturated. Why would any thermal imager saturate at 38C?

The heat source on the top has dimensions greater than the PCB thickness, and
that creates a hot spot on the bottom that is pretty much isothermal near its
center, sort of an inverted parabola or something, kinda flat on top. That's all
logical.

>
>
>> Maybe the thermal
>>> imager automatically sets the range appropriately,
>>
>> There's that bar graph thingie on the side.
>
>You mean the display? Do you set the range or does the camera?

In that mode, it does. Nothing's saturated. I guess I could zoom in on the spot,
to see its temperature profile in more detail... if I can find the board.

>
>
>> but the resolution is
>>> poor so I seriously doubt the spot is isothermal enough to show no
>>> useful heat flow.
>>
>> 6 degs C gradient from hot spot to nearby copper, with 1 watt dissipated on the
>> opposite side.
>
>And I believe over 10 degrees between the two sides. But what is the
>range of temperature *within* the hot spot. Your camera shows it as
>isothermal, but that can be due to saturation. You have to use the
>device properly to get useful info.

The Flir ain't saturated. The spot is pretty isothermal, in that the lateral
gradient is low near the center. The real point is that the copper is hot, and
half an inch away it's down near ambient. It doesn't conduct heat very well.

>
>
>>>>> I suppose "almost no good" is very similar to "some good" which is the
>>>>> reality.
>>>>
>>>> Maybe we can agree on "not much good" ?
>>>
>>> ?
>>>
>>>> The images you posted actually make my point. The hot spot
>>>>> shown in your last image of the underside of the board from your earlier
>>>>> post show about a 10�C drop through the board. The vias mitigate this
>>>>> drop *even if they are in the middle of the hot spot*.
>>>>
>>>> Sure, but the dominant thermal resistance won't be the vias, it will be the
>>>> spreading resistance of the bottomside copper. Adding vias outside the dpak
>>>> footpring will halp a lot, and they're free, if you think about them up-front.
>>>
>>> You have not shown that at all. If you want to make a claim about the
>>> "dominant" thermal resistance you need to show this somehow, by
>>> measurement or analysis. So far your analysis has been far too thin to
>>> be useful.
>>
>> It's useful because all of my designs work.
>
>You said this was a test board. So that point is moot.

I do calculations and experiments and learn. Then I design stuff that works.
What do you have against that?

>
>
>>>> The temperature
>>>>> drop across the copper in the hot spot is perhaps 1 or 2�C as shown in
>>>>> your own images. Regardless, each extra via in the hot spot will help
>>>>> to reduce the die temperature.
>>>>
>>>> Look again:
>>>>
>>>> https://dl.dropboxusercontent.com/u/53724080/Thermal/T750_t5.jpg
>>>>
>>>> The hot spot is 38C, and half an inch away, the yellow stuff is about 32.
>>>
>>> Yes? So the heat flow is due to a 6�C change across a low thermal
>>> resistance. I'd say there is significant heat flow.
>>
>> Well, it's a bit under 1 watt, since the resistors on top are dissipating 1
>> watt. So the theta of that hot spot is at least 6 K/W, probably more. James and
>> I estimated that his via field was about 4 K/W. So the spreading resistance is
>> more than the via resistance.
>
>Which actually means they are in the same ballpark and so even a
>moderate change in either one will impact the overall result.
>
>
>> But in reality
>>> this is not a useful image because there are no vias and no copper on top.
>>
>> It demonstrates typical thermal spreading resistance in a copper plane. That
>> sounds like useful info to me.
>>
>> Do you do much electronic thermal design? Show us some.
>
>So your work can't stand on its own? You make claims that are *not*
>substantiated by the info you post and in fact so far everything you
>have provided shows the vias under the pad *will* have a useful impact
>on the result.

So, you don't do thermal design. Thought as much. Do you design electronics at
all?

Here's a TO220 Caddock resistor bolted to a big sheet of 0.062 thick aluminum.

https://dl.dropboxusercontent.com/u/53724080/Thermal/Infinite_Sheet.jpg

Note that even 1/16 thick aluminum has substantial thermal spreading resistance.
Just an inch away, the temperature rise has dropped in half. That has
implications to sinking things like voltage regulators to a chassis.

1.4 mil (1 oz) copper is way worse. So the trick is to maximize the area that
the heat is initially dumped into. The tighter the via field, the higher theta.

I'm surprised that I have to explain stuff this simple.

[Phil Hobbs]

2D thermal conduction is like that, though. In equilibrium, for a
uniform insulated plate, the temperature flux through any annular ring
is constant, so the temperature gradient goes as -1/r and the
temperature profile goes like -log r.

As you say, if the copper slug in the package is wider than the board is
thick, vias round the edge (but still just under the slug) do more than
those in the middle.

In fact, if the slug is perfectly isothermal, the board is well
insulated, and the aggregate thermal resistance of the edge vias is very
low, the region inside the via ring will be at exactly the same
temperature as the slug, i.e. the inside vias will do nothing
whatsoever. Reality isn't quite this neat, of course, but it's clearly
true that given the same number of vias of a given size, it's better to
distribute them around the edges of the slug rather than put them in the
centre.

Cheers

Phil Hobbs

>
> 1.4 mil (1 oz) copper is way worse. So the trick is to maximize the area that
> the heat is initially dumped into. The tighter the via field, the higher theta.
>
> I'm surprised that I have to explain stuff this simple.
>
>
>


--

[John Larkin]

Mitigated a bit by convection. This stuff is complicated!

>
>As you say, if the copper slug in the package is wider than the board is
>thick, vias round the edge (but still just under the slug) do more than
>those in the middle.
>
>In fact, if the slug is perfectly isothermal, the board is well
>insulated, and the aggregate thermal resistance of the edge vias is very
>low, the region inside the via ring will be at exactly the same
>temperature as the slug, i.e. the inside vias will do nothing
>whatsoever.

Right! Move them outside the slug a bit.

Reality isn't quite this neat, of course, but it's clearly
>true that given the same number of vias of a given size, it's better to
>distribute them around the edges of the slug rather than put them in the
>centre.

One fix for James' problem would be to glue a metal disk to the bottom of the
board, to effectively increase the diameter of the via array.

I was recently doing some studies to bring down the temperature of an FPGA (the
ring oscillator experiment and such, wound up being a 16 page report). Gluing a
pin-fin heat sink to the top of the FPGA dropped the silicon temp by 4K. The
fins didn't do any good; the benefit was from the thermal spreading of the base
of the sink. A flat aluminum square did just as well.

[Tim Williams]

"Phil Hobbs" <ho...@electrooptical.net> wrote in message
news:53B2A36C...@electrooptical.net...

> 2D thermal conduction is like that, though. In equilibrium, for a
> uniform insulated plate, the temperature flux through any annular ring
> is constant, so the temperature gradient goes as -1/r and the
> temperature profile goes like -log r.

Which is unrealistic, of course. A perhaps more useful (but likely
equally unrealistic* :) ) formulation, where all points on the surface
have constant thermal resistance to an infinite sink, yields a dependency
something like J_0(r). Which emphasizes the notion of a lateral spreading
distance: the temperature is highest in the center, near the peak of the
Bessel function, and dropping off to zero away from there. More material
thickness or conductivity gets you more distance and thus more total
dissipation; more distance without any meat behind it results in wasted
space.

*Problems concerning heat dissipation and convection being notoriously
anti-analytic, of course. That said, power laws are usually a good fit,
and who knows, maybe a T^(3/2) or T^2 power is easier to integrate than
that silly Bessel function.

Tim

--
Seven Transistor Labs
Electrical Engineering Consultation
Website: http://seventransistorlabs.com

[rickman]

On 7/1/2014 12:06 AM, John Larkin wrote:

"Kinda" flat? It would be spherical through the relatively insulating
PCB and then relatively higher conductivity of the copper would spread
it making it look more even.

The point of the device is that it isn't very good at showing what the
temperature difference is in what you call a hot spot. But that is
mostly irrelevant since this is not a board with vias which completely
change the picture.

>>> but the resolution is
>>>> poor so I seriously doubt the spot is isothermal enough to show no
>>>> useful heat flow.
>>>
>>> 6 degs C gradient from hot spot to nearby copper, with 1 watt dissipated on the
>>> opposite side.
>>
>> And I believe over 10 degrees between the two sides. But what is the
>> range of temperature *within* the hot spot. Your camera shows it as
>> isothermal, but that can be due to saturation. You have to use the
>> device properly to get useful info.
>
> The Flir ain't saturated. The spot is pretty isothermal, in that the lateral
> gradient is low near the center. The real point is that the copper is hot, and
> half an inch away it's down near ambient. It doesn't conduct heat very well.

Your ambient is 31�C? Looks to me like it *is* conducting very well.
You have already given numbers that disprove your case. I believe you
said the vias result in a 4�C drop and the copper layer 6�C. Clearly
these two numbers are close enough that a change in either one
significantly impacts the sum.

>>>>> The images you posted actually make my point. The hot spot
>>>>>> shown in your last image of the underside of the board from your earlier
>>>>>> post show about a 10�C drop through the board. The vias mitigate this
>>>>>> drop *even if they are in the middle of the hot spot*.
>>>>>
>>>>> Sure, but the dominant thermal resistance won't be the vias, it will be the
>>>>> spreading resistance of the bottomside copper. Adding vias outside the dpak
>>>>> footpring will halp a lot, and they're free, if you think about them up-front.
>>>>
>>>> You have not shown that at all. If you want to make a claim about the
>>>> "dominant" thermal resistance you need to show this somehow, by
>>>> measurement or analysis. So far your analysis has been far too thin to
>>>> be useful.
>>>
>>> It's useful because all of my designs work.
>>
>> You said this was a test board. So that point is moot.
>
> I do calculations and experiments and learn. Then I design stuff that works.
> What do you have against that?

I don't appreciate your faulty logic.

>>>>> The temperature
>>>>>> drop across the copper in the hot spot is perhaps 1 or 2�C as shown in
>>>>>> your own images. Regardless, each extra via in the hot spot will help
>>>>>> to reduce the die temperature.
>>>>>
>>>>> Look again:
>>>>>
>>>>> https://dl.dropboxusercontent.com/u/53724080/Thermal/T750_t5.jpg
>>>>>
>>>>> The hot spot is 38C, and half an inch away, the yellow stuff is about 32.
>>>>
>>>> Yes? So the heat flow is due to a 6�C change across a low thermal
>>>> resistance. I'd say there is significant heat flow.
>>>
>>> Well, it's a bit under 1 watt, since the resistors on top are dissipating 1
>>> watt. So the theta of that hot spot is at least 6 K/W, probably more. James and
>>> I estimated that his via field was about 4 K/W. So the spreading resistance is
>>> more than the via resistance.
>>
>> Which actually means they are in the same ballpark and so even a
>> moderate change in either one will impact the overall result.

Now that you provided real data you don't seem to want to discuss it.

>>> But in reality
>>>> this is not a useful image because there are no vias and no copper on top.
>>>
>>> It demonstrates typical thermal spreading resistance in a copper plane. That
>>> sounds like useful info to me.
>>>
>>> Do you do much electronic thermal design? Show us some.
>>
>> So your work can't stand on its own? You make claims that are *not*
>> substantiated by the info you post and in fact so far everything you
>> have provided shows the vias under the pad *will* have a useful impact
>> on the result.
>
> So, you don't do thermal design. Thought as much. Do you design electronics at
> all?

We are discussing the claims you made which I say are not supported by
your data. In fact, now that you have provided hard data your claims
are clearly wrong. Do you wish to discuss your numbers?

--

Rick

[John Larkin]

All you do is whine. Design something; you'll feel better.




--

John Larkin Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

[Phil Hobbs]

My first choice would be right round the edge of the slug, some inside
and some outside, and then stitching the top pour to the heatsink layer
for some reasonable but poorly specified additional radius to reduce the
net thermal resistance.
>
Cheers

Phil Hobbs

[Phil Hobbs]

On 7/1/2014 5:06 PM, Tim Williams wrote:
> "Phil Hobbs" <ho...@electrooptical.net> wrote in message
> news:53B2A36C...@electrooptical.net...
>> 2D thermal conduction is like that, though. In equilibrium, for a
>> uniform insulated plate, the temperature flux through any annular ring
>> is constant, so the temperature gradient goes as -1/r and the
>> temperature profile goes like -log r.
>
> Which is unrealistic, of course. A perhaps more useful (but likely
> equally unrealistic* :) ) formulation, where all points on the surface
> have constant thermal resistance to an infinite sink, yields a dependency
> something like J_0(r).

Can't be an oscillatory Bessel function, because the heat equation is
first order. I_0 and K_0, possibly, if your cows are cylinders instead
of spheres. ;)

Which emphasizes the notion of a lateral spreading
> distance: the temperature is highest in the center, near the peak of the
> Bessel function, and dropping off to zero away from there. More material
> thickness or conductivity gets you more distance and thus more total
> dissipation; more distance without any meat behind it results in wasted
> space.
>
> *Problems concerning heat dissipation and convection being notoriously
> anti-analytic, of course. That said, power laws are usually a good fit,
> and who knows, maybe a T^(3/2) or T^2 power is easier to integrate than
> that silly Bessel function.
>
> Tim

You just need a copy of Gradshteyn & Ryzhik. ;)
Cheers

Phil Hobbs

[dagmarg...@yahoo.com]

On Tuesday, July 1, 2014 9:01:03 PM UTC-4, Phil Hobbs wrote:
> On 7/1/2014 11:50 AM, John Larkin wrote:

> > On Tue, 01 Jul 2014 08:02:52 -0400, Phil Hobbs wrote:

> >> As you say, if the copper slug in the package is wider than the board is
> >> thick, vias round the edge (but still just under the slug) do more than
> >> those in the middle.
> >>
> >> In fact, if the slug is perfectly isothermal, the board is well
> >> insulated, and the aggregate thermal resistance of the edge vias is very
> >> low, the region inside the via ring will be at exactly the same
> >> temperature as the slug, i.e. the inside vias will do nothing
> >> whatsoever.
> >
> > Right! Move them outside the slug a bit.
>
> My first choice would be right round the edge of the slug, some inside
> and some outside, and then stitching the top pour to the heatsink layer
> for some reasonable but poorly specified additional radius to reduce the
> net thermal resistance.

That's my qualitative take. Qualitatively, the goal is to launch as
much heat into the bottom pour, over as wide an area as possible.

The area under the tab is going to be, by definition, the hot spot,
since it's where the heat originates, and it's so small compared to
the total dissipating surface. So, spreading that wider is better.

I was quasi-tempted to LT-Spice it for fun, but wound up helping roof
a house instead!


>> .-----------------.
>> | | <~~ tab [1]
>> '-----------------'
>> ==========================
>> )####||####||#||####||###) <~~FR-4
>> (#####||####||#||####||##(
>> =========================== <~~ copper [2]
via-> A B C D


.-/\/\/\/\/\/\/\/\/\-. <~~r(tab) [1]
| | | |
(air) -\/\/-+-/\/\-+-/\/\-+-/\/\-+-/\/\-- <~~r(pad) [2]
A| B| C| D|
.-. .-. .-. .-.
| | | | | | | | <~~ vias 57 K/W [3]
'-' '-' '-' '-'
| | | |
rsXA | rsAB | rsBC | rsCD | rsDX1 rsDXn
.---\/\/-+-/\/\-+-/\/\-+-/\/\-+-/\/\-...-/\/\-.
| | | | | |
.-. .-. .-. .-. .-. .-.
| | | | | | | | | | | | <~~ path to air
'-' '-' '-' '-' '-' '-'
| | | | | |
- - - - - -
air air air air air air

[1] .050" (1,27 mm) 10.4 x 10.8mm, (spreading: 2.6 K/W per square)
[2] 2oz. (0,068mm) copper (spreading: 38 K/W per square)
[3] .020", .0625" board thickness,
25um (3/4 oz) plated walls, solder-filled

Cheers,
James Arthur

[John Larkin]

On Tue, 01 Jul 2014 21:01:03 -0400, Phil Hobbs

YOU can say that. If I say that, rickman will whine at me.

[Phil Hobbs]

You do seem to collect groupies of that sort. Must be your air guitar
skills. ;)

[rickman]

On 7/1/2014 6:46 PM, John Larkin wrote:
>
> All you do is whine. Design something; you'll feel better.

Ok, I take it you just can't figure out how to justify your poor logic.
That's all I was trying to do, point out that you could do a better
job of understanding the issues instead of declaring the interior vias
to be of no value without supporting evidence.

--

Rick

[John Larkin]

It's just a newsgroup. It's not, like, life or anything.

Hey, lots of web sites swipe our posts and repost them as "forums", with ads. If
I say

copyright (c) John Larkin 2014

can I sue them?

[John Larkin]

You've done nothing but content-free sniveling. Suggest a better via arrangement
to cool James' DPAK.

[John Devereux]

John Larkin <jjla...@highNOTlandTHIStechnologyPART.com> writes:

[... Copyrighted content elided ...]

Makes it hard to have a conversation though.... :)


--

John Devereux

[John Devereux]

He supported it fine. Yes, of course in the real world "everything
depends on everything else", but most of the contributions are
insignificant - which is what makes design at all
possible. "Understanding the issues" includes the ability to see where
these contributions are going to be insignificant, so that attention can
be concentrated where it is useful. Otherwise every time you consider
heat you will end up needing some monstrous 3D FEA thermal modelling
program just to place a DPAK. And even when you modelled it, you still
won't know what to do, you won't *understand* anything.


--

John Devereux

[Phil Hobbs]

I actually use one of those to read SED from my phone when I'm stuck
someplace. It's dramatically better than GGroups.

[rickman]

On 7/2/2014 12:51 AM, John Larkin wrote:
> On Tue, 01 Jul 2014 22:50:49 -0400, rickman <gnu...@gmail.com> wrote:
>
>> On 7/1/2014 6:46 PM, John Larkin wrote:
>>>
>>> All you do is whine. Design something; you'll feel better.
>>
>> Ok, I take it you just can't figure out how to justify your poor logic.
>> That's all I was trying to do, point out that you could do a better
>> job of understanding the issues instead of declaring the interior vias
>> to be of no value without supporting evidence.
>
> You've done nothing but content-free sniveling. Suggest a better via arrangement
> to cool James' DPAK.

I'm discussing the problem with your statement which you seem to want to
avoid now that there are hard facts to show your statement is not accurate.

--

Rick

[rickman]

And that is my point. John took a small amount of info, from an example
that wasn't even like the design being discussed and extrapolated
claiming that there was no point in having vias under the part. That is
not "understanding". Too little info, too much extrapolation and
misunderstanding.

Yes, vias close to the edge of the part will do better at cooling than
the vias in the center of the part. But to say they do next to nothing
is not accurate or useful. If you can add vias under the part they will
help cool the part and will be useful. The little info provided by John
clearly shows this.

--

Rick

[John Larkin]

Quit babbling and say something specific, maybe even on-topic.

[John Larkin]

On Wed, 02 Jul 2014 12:06:12 -0400, rickman <gnu...@gmail.com> wrote:

>On 7/2/2014 3:11 AM, John Devereux wrote:
>> rickman <gnu...@gmail.com> writes:
>>
>>> On 7/1/2014 6:46 PM, John Larkin wrote:
>>>>
>>>> All you do is whine. Design something; you'll feel better.
>>>
>>> Ok, I take it you just can't figure out how to justify your poor
>>> logic. That's all I was trying to do, point out that you could do a
>>> better job of understanding the issues instead of declaring the
>>> interior vias to be of no value without supporting evidence.
>>
>> He supported it fine. Yes, of course in the real world "everything
>> depends on everything else", but most of the contributions are
>> insignificant - which is what makes design at all
>> possible. "Understanding the issues" includes the ability to see where
>> these contributions are going to be insignificant, so that attention can
>> be concentrated where it is useful. Otherwise every time you consider
>> heat you will end up needing some monstrous 3D FEA thermal modelling
>> program just to place a DPAK. And even when you modelled it, you still
>> won't know what to do, you won't *understand* anything.
>
>
>And that is my point. John took a small amount of info, from an example
>that wasn't even like the design being discussed and extrapolated
>claiming that there was no point in having vias under the part. That is
>not "understanding". Too little info, too much extrapolation and
>misunderstanding.

All wrong. I suggested a few vias under the dpak and a number, 8 or 12 maybe,
outside the pad footprint, on a topside heat-spreading pour, with enough solder
mask to prevent the outer vias from stealing solder paste.

>
>Yes, vias close to the edge of the part will do better at cooling than
>the vias in the center of the part. But to say they do next to nothing
>is not accurate or useful.

I said that, in James' dense via array, the inner vias conduct very little heat
and could be eliminated.

If you can add vias under the part they will
>help cool the part and will be useful.

Except that they steal solder, which was the original issue. Since they are
almost worthless thermally, eliminate most of them and add vias outside the pad
area.

Once you add the outside vias, the inner ones are thermally shielded, within the
hot spot, and the inner-inner ones are double shielded.

Spreading thermal resistance in the bottom pour is important.

If you disagree, present a better design.

[rickman]

On 7/2/2014 12:30 PM, John Larkin wrote:
> On Wed, 02 Jul 2014 11:59:09 -0400, rickman <gnu...@gmail.com> wrote:
>
>> On 7/2/2014 12:51 AM, John Larkin wrote:
>>> On Tue, 01 Jul 2014 22:50:49 -0400, rickman <gnu...@gmail.com> wrote:
>>>
>>>> On 7/1/2014 6:46 PM, John Larkin wrote:
>>>>>
>>>>> All you do is whine. Design something; you'll feel better.
>>>>
>>>> Ok, I take it you just can't figure out how to justify your poor logic.
>>>> That's all I was trying to do, point out that you could do a better
>>>> job of understanding the issues instead of declaring the interior vias
>>>> to be of no value without supporting evidence.
>>>
>>> You've done nothing but content-free sniveling. Suggest a better via arrangement
>>> to cool James' DPAK.
>>
>> I'm discussing the problem with your statement which you seem to want to
>> avoid now that there are hard facts to show your statement is not accurate.
>
> Quit babbling and say something specific, maybe even on-topic.

I have said plenty and you seem to want to no longer discuss that. I
used your numbers to show that inner vias will continue to provide
useful improvement to cooling the chip and you never responded.

--

Rick

[rickman]

On 7/2/2014 12:37 PM, John Larkin wrote:
> On Wed, 02 Jul 2014 12:06:12 -0400, rickman <gnu...@gmail.com> wrote:
>
>> Yes, vias close to the edge of the part will do better at cooling than
>> the vias in the center of the part. But to say they do next to nothing
>> is not accurate or useful.
>
> I said that, in James' dense via array, the inner vias conduct very little heat
> and could be eliminated.

Yes, and that is the statement that is wrong as proven by your own data.
The inner vias may not conduct as much heat as the outer vias, but
they are in the same range of scale and will improve the temperature of
the chip. Your own data shows this. Unless you mean a factor around 2
or 3 is "very little" that statement is wrong.

Removing the vias from the center means the temperature will rise unless
you replace them with vias elsewhere.

> If you can add vias under the part they will
>> help cool the part and will be useful.
>
> Except that they steal solder, which was the original issue. Since they are
> almost worthless thermally, eliminate most of them and add vias outside the pad
> area.

Yes, I don't dispute that if you design the vias as large solder sucking
voids they will create a problem.

> Once you add the outside vias, the inner ones are thermally shielded, within the
> hot spot, and the inner-inner ones are double shielded.
>
> Spreading thermal resistance in the bottom pour is important.

Your data shows this is not accurate. Every via is a path for heat to
escape and your "thermal shield" may cause a factor of 2 or so decrease
in heat flow in these inner vias, but it is inaccurate to say the inner
vias have no value.

--

Rick

[dagmarg...@yahoo.com]

On Sunday, June 29, 2014 11:27:52 AM UTC-4, rickman wrote:
> On 6/27/2014 9:31 AM, dagmargoo...@yahoo.com wrote:
> > On Thursday, June 26, 2014 4:05:33 AM UTC-4, rickman wrote:
> >> On 6/26/2014 1:05 AM, John Larkin wrote:
> >
> >>> That wasn't my point. My point is that, to better cool the dpak, the vias need
> >>> to be spread out, not clustered under the chip. And that fixes the solder
> >>> scavenging problem, too.
> >>
> >> How do you get the heat into the vias from the chip....? Oh, I know,
> >> use a heat spreader on the top side!!! Wait, isn't that going to give
> >> you the same result?
> >>
> >> In the real world, the vias can be under the chip and work fine. I have
> >> done this myself before. The details you are trying to optimize are
> >> largely irrelevant and end up having little impact on the die temperature.
> >>
>
> >> I know guys who think like you and build fast cars. In the end they get
> >> stuff to work, but only after doing it wrong a few times.
> >
> > FYI, John's no hacker. He's one of the most disciplined, knowledgeable,
> > proficient engineers on the planet, and specifically expert in thermal
> > design, from long years of practice and rigorous investigation(s).

> >
> > You might want to drag up his FAQ "Notes on Cooling Electronics", posted
> > here in SED a few years ago.
>

> Most of the design issues I have discussed with John have been exactly
> about hacking rather than designing. This one is a great example. Here
> he is drawing a picture and trying to understand the working and getting
> a wrong answer. His original statement that I am trying to get him to
> discuss was,

>
>
> "The vias in the interior of the array are doing almost no good, because
> they are in the middle of a hot spot."

That's true. If there's no temperature differential across a via, it's
not going to carry much heat.

In electrical analogy, paralleling a high-value resistor (the via) across
a lower-value resistor (the D-PAK slug) does little to lower the total
path resistance (die to the environment).


In pictures, vias-under-tab...


FIG. 1
------
D-PAK tab
2.6K/W

.-/\/\/\/\/\/\/\/\/\-. <~~r(tab) [1]

/ \
| |
-------------------|------|----------------------------------
| |
.-. .-.
| | | | (12) vias, 4.75 K/W, 2 places [3]
'-' '-'
| |
-------------------|------|----------------------------------
rsAB | rsBC | rsCD rsDX <~~ spreading resistances
rsXA | 38K/W| 38K/W| 38K/W | 38K/W [2]
|--\/\/--+--/\/\-+-/\/\-+-/\/\--+--/\/\--| (air)
A B C D


Does not get the heat to the ends of the bottom pour (and hence
not was well to the environment) as well as spreading the thermal
vias to the tab's edges:


FIG.2
-----
D-PAK
2.6K/W
.--/\/\/\/\/\/\/\/\/\--. <~~r(tab) [1]
| |
------------|----------------------|--------------
| |
.-. .-.
| | | | <~~ (12) vias, 4.75 K/W, 2 places [3]
'-' '-'
------------|----------------------|--------------
| |
| rsAB | rsBC | rsDC | rsDX
rsXA | 38K/W| 38K/W| 38K/W | 38K/W [2]
|--\/\/--+--/\/\-+-/\/\-+-/\/\--+--/\/\--| (air)
A B C D

[1] .050" (1,27 mm), 10.4 x 10.8mm, (spreading: ~2.6 K/W per square)

[2] 2oz. (0,068mm) copper (spreading: 38 K/W per square)

[3] .020", .0625" board thickness, 25um (3/4 oz) plated walls, solder-filled, 57K/W

> He continues to insist that moving the vias outside the footprint of the
> part is an advantage because they are outside the hot spot and the heat
> will spread better.

Yes.

> But he ignores that there is still the same hot
> spot on the top side of the board

That doesn't really matter to the via-placement question.
The D-PAK tab is a virtual thermal short. To a first order,
it doesn't care where the vias are under it.

But, the bottom copper pour has ~15x the spreading resistance.
If we can cut out some of that by distributing the thermal vias
to the D-PAK edge, that's a clear benefit.

> and posts photos of an example which
> doesn't even have vias and can't be considered without more info.

Those photos don't directly address the via question because they weren't
meant to--those photos were from a series of investigations into the
power capability of SMD resistors, IIRC.

But they underscored for me the horrible thermal spreading resistance
of the copper pour. I'm using 2oz. copper, which is better, but
still awful compared to the other thermal paths in play. Bridging over
and bypassing part of that by spreading the thermal vias is a definite plus.


> I'm sure John is no slouch, but he is guilty of doing a cursory
> examination of this design issue and I can't see where his conclusions
> are valid.


> I see no evidence of "rigorous investigation" in this case.

He showed us images he had handy of a prototype made to test thermal
stuff, with FLIR images. An actual, documented prototype? I'd call
that pretty rigorous.

Which would you trust more, a calculation, or an actual measurement?
Which is more rigorous? And, that was just what he had handy from
another task--I'm quite sure he's looked at lots of other actual
products with that fancy FLIR of his. He does that.

Cheers,
James Arthur

[dagmarg...@yahoo.com]

On Sunday, June 29, 2014 2:15:40 PM UTC-4, John Larkin wrote:

> A bunch of vias outside the chip pad works well, assuming there are many of them
> and that they are close to the pad. The thermal resistance of the copper from
> the pad to each such via will be similar to the theta of the via itself, and
> there can be lots of them, each dumping into a relatively cool part of the pour
> on the opposite side. On a small part like a dpak, that works a lot better than
> having a cluster of vias under the pad and a corresponding hot spot on the
> bottomside pour.

Yep. The main thermal advantage to under-tab vias is that they solder-fill,
which the assy house hates, and is what got us here to start with...

Cheers,
James Arthur

[rickman]

Where did you get your resistance numbers? They don't match the data
John provided. His numbers were 6�C drop from the center of the hot
spot to a point well outside the hot spot which indicates a similar
thermal conductivity to a group of vias which he or someone else
calculated at 4�C per Watt aggregate. Clearly nothing in this example
can have a resistance of 38�K/W as you show it and 4.7 K/W seems
abnormal for an individual via. If you fudge the numbers the
calculations won't show reality.

--

Rick

[josephkk]

On Wed, 02 Jul 2014 10:26:54 -0400, Phil Hobbs
<pcdhSpamM...@electrooptical.net> wrote:

>
>> It's just a newsgroup. It's not, like, life or anything.
>>
>> Hey, lots of web sites swipe our posts and repost them as "forums", with ads. If
>> I say
>>
>> copyright (c) John Larkin 2014
>>
>> can I sue them?
>>
>>
>I actually use one of those to read SED from my phone when I'm stuck
>someplace. It's dramatically better than GGroups.
>
>Cheers
>
>Phil Hobbs

I keep hearing about G2 which is supposed to be a newsreader for a schmart
phone. You might try that.

?-)

[dagmarg...@yahoo.com]

On Wednesday, July 2, 2014 8:57:59 PM UTC-4, rickman wrote:

I calculated the numbers from the copper cross sections, all listed
in the footnotes above.

The drawing rather plainly shows the individual vias are 57K/W
filled with solder, and therefore 4.75 K/W for a group of 12.

From basic principles, 2 oz. copper has a spreading resistance of
38 K/W per square. (If I miscalculated, please correct me.)

But if you're focusing on all that you're missing the boat.

The D-PAK tab is nearly 19x thicker than the PCB copper. It will quite
obviously conduct heat from under its center to its edges far better--
19x better--than any copper pour can.

Channeling the D-PAK's heat to the center of the pour underneath it
simply adds the thermal resistance of that part of the copper pour
to the total thermal path.

.---------------.
| .-----. |
| 1 2 |
A | 1 X 2 | B
| 1 2 |
| '-----' |
'---------------'

If the goal is to get heat to A and B, it's better to
start at 1 & 2 rather than X.

So, within the D-PAK's "shadow" on the bottom, it's better to use the
1,27 mm thick D-PAK tab to carry the heat to the D-PAK's edges than
the wimpy 0.068 mm-thick copper pours.

Cheers,
James Arthur

[rickman]

I don't dispute that 1 and 2 are better places to add vias than at X. I
dispute the statement from John that a via at X has no value in cooling.
Also John is promoting adding the vias at A and B which suffer the
same top side copper layer resistance as the underside does.

Your numbers may have been calculated correctly, but they are a far way
from showing the temperature drops across the board and the relative
benefits of adding vias at X as opposed to not having vias at X which is
the point being discussed. You lump the thermal resistance of all the
vias into a single number 4.7 K/W but each one is 57 K/W. Then you show
the sheet resistance of the copper as 38 K/W per square without
factoring in the area and the shape. So apples and oranges.

John looked at a thermal image and decided that because on a board with
no vias the temperature in a small area *appeared* to have little
temperature difference there could be no heat flow if vias were added to
the board under the package. Sure it is better to have vias at the edge
of the chip, but adding vias at the center will still provide additional
cooling in a significant manner. It is exactly the same as parallel
resistors. Two 10 ohm resistors in series, the pair in parallel with a
single 10 ohm resistor lowers the circuit impedance significantly and
also the voltage drop for a constant current which is the analog to the
thermal issue we are discussing.

--

Rick

[Phil Hobbs]

I don't think it runs on my Blackberry 9900, to which I am very
attached, for two features:

1. An excellent pointing device (like a miniature track pad) that is far
more precise than the touchscreen; and

2. Unequalled data security.

I also like the keyboard, but you can get physical keyboards for some
other brands as well.

Droids are worse than Windows for security, and Apples aren't very much
better.

[dagmarg...@yahoo.com]

On Thursday, July 3, 2014 12:48:27 AM UTC-4, rickman wrote:

> I don't dispute that 1 and 2 are better places to add vias than at X. I
> dispute the statement from John that a via at X has no value in cooling.
>
> Also John is promoting adding the vias at A and B which suffer the
> same top side copper layer resistance as the underside does.

A and B are the ends of the pour. John's been saying to move most of the
vias from X to 1 & 2, the edges of the D-PAK's tab.

> Your numbers may have been calculated correctly, but they are a far way
> from showing the temperature drops across the board and the relative
> benefits of adding vias at X as opposed to not having vias at X which is
> the point being discussed.

> You lump the thermal resistance of all the
> vias into a single number 4.7 K/W but each one is 57 K/W.

I calculated the effect of a line of 12 vias in parallel, rather than
clutter the ASCII drawing with 24 individual vias. What's wrong with
that?

> Then you show
> the sheet resistance of the copper as 38 K/W per square without
> factoring in the area and the shape.

Partly true, yet all clearly disclosed in the drawing. It's more than
enough to make relative judgements about thermal vias near the D-PAK.
My aim here was to resolve the solder-wicking; yours was thermal re-design
of this specific instance, a curiosity which I've been trying to accommodate.

So, the bottom pour for the part I'm worried about is 1" x .5". Top pour is
the same. The board is vertically mounted, spaced above an aluminum chassis,
and has some airflow, but not necessarily directly on this board. The original
dissipation was <500mW, new dissipation not known, but what was a bias supply
is now being used as a main power source for loads unknown.

There, have at it.

> So apples and oranges.
>
> John looked at a thermal image and decided that because on a board with
> no vias the temperature in a small area *appeared* to have little
> temperature difference there could be no heat flow if vias were added to
> the board under the package.

Of course adding vias anywhere helps, if only marginally. But, for a
given number, moving them from the edge to the center detracts, not adds.

> Sure it is better to have vias at the edge
> of the chip, but adding vias at the center will still provide additional
> cooling in a significant manner. It is exactly the same as parallel
> resistors. Two 10 ohm resistors in series, the pair in parallel with a
> single 10 ohm resistor lowers the circuit impedance significantly and
> also the voltage drop for a constant current which is the analog to the
> thermal issue we are discussing.

2 5 38K/W
--+---/\/\/---+--/\/\/--+--/\/\/---...----
| | |
| 57 /O You |
'-/\/\/--O' |
O---------'
John

If there's already a 2 ohm resistance to a point, then 5 ohms extra
(or, before you jump on it again, <whatever> value it might be) to a
further point, it's better to connect every one of your 57 ohm resistors
past the 5 ohms than before it.

Cheers,
James Arthur

[John Larkin]

>> >> John provided. His numbers were 6?C drop from the center of the hot

>> >> spot to a point well outside the hot spot which indicates a similar
>> >> thermal conductivity to a group of vias which he or someone else

>> >> calculated at 4?C per Watt aggregate. Clearly nothing in this example
>> >> can have a resistance of 38?K/W as you show it and 4.7 K/W seems

Half a watt would be fine, but something like, say, 5 watts will get serious.
But slap a thermocouple on the tab and be sure.

"Loads unknown" does make analysis more difficult.

I tested a SOT89 (Supertex DN2530 depletion fet) for power capability, and
decided it would be fine at 3 watts with some reasonable copper pours.

Engineering isn't about proving how smart you are, or about showing how dumb
other people are, or indeed about proving anything at all. It's about building
things that work and getting purchase orders for same.

[rickman]

The post I was responding to John said to move *all* the vias to outside
1 and 2 where they suffer the sheet resistance of the top side layer.
My point is that he said because the bottom of the board is isothermal
under the chip and the actual thermal resistance is too high in the
smaller radius area, the inner vias have no useful value. I have
offered him to modify this statement to say they have less use than the
outer vias, but he insists the inner vias conduct virtually no heat.
That is wrong.

>> Your numbers may have been calculated correctly, but they are a far way
>> from showing the temperature drops across the board and the relative
>> benefits of adding vias at X as opposed to not having vias at X which is
>> the point being discussed.
>
>> You lump the thermal resistance of all the
>> vias into a single number 4.7 K/W but each one is 57 K/W.
>
> I calculated the effect of a line of 12 vias in parallel, rather than
> clutter the ASCII drawing with 24 individual vias. What's wrong with
> that?

Because you compare the numbers for the parallel vias to the number for
the sheet resistivity which you graphically show as being in series
several times. Sheet resistivity is not resistance.

>> Then you show
>> the sheet resistance of the copper as 38 K/W per square without
>> factoring in the area and the shape.
>
> Partly true, yet all clearly disclosed in the drawing. It's more than
> enough to make relative judgements about thermal vias near the D-PAK.
> My aim here was to resolve the solder-wicking; yours was thermal re-design
> of this specific instance, a curiosity which I've been trying to accommodate.

I'm not trying to redesign anything. I am commenting on the poor
thought processes being used by John and now you. Your comment above is
a perfect example. You have presented no data that can be usefully
compared regarding the vias under the part.

>> John looked at a thermal image and decided that because on a board with
>> no vias the temperature in a small area *appeared* to have little
>> temperature difference there could be no heat flow if vias were added to
>> the board under the package.
>
> Of course adding vias anywhere helps, if only marginally. But, for a
> given number, moving them from the edge to the center detracts, not adds.

That is the issue, what is "marginal". From the data shown by John I
estimate the vias in the center of the part will have no more than twice
the thermal resistance as the vias outside the edge of the part. So if
they can be added, I would add them.

>> Sure it is better to have vias at the edge
>> of the chip, but adding vias at the center will still provide additional
>> cooling in a significant manner. It is exactly the same as parallel
>> resistors. Two 10 ohm resistors in series, the pair in parallel with a
>> single 10 ohm resistor lowers the circuit impedance significantly and
>> also the voltage drop for a constant current which is the analog to the
>> thermal issue we are discussing.
>
> 2 5 38K/W
> --+---/\/\/---+--/\/\/--+--/\/\/---...----
> | | |
> | 57 /O You |
> '-/\/\/--O' |
> O---------'
> John
>
> If there's already a 2 ohm resistance to a point, then 5 ohms extra
> (or, before you jump on it again, <whatever> value it might be) to a
> further point, it's better to connect every one of your 57 ohm resistors
> past the 5 ohms than before it.

I have no idea where you get these values. I believe the 57 you show is
one via? But what are the 2 and the 5 and the 38? Are you trying to
show the effect of adding one via to a board with dozens of vias
already? BTW, John's point is not to move the via to another location.
He says the vias have no value which means drop them entirely. If I
can add a dozen vias under the pad, in your model, it looks like I would
have about 5 in parallel with 2 which would still produce a useful
improvement. Oh, you continue to confuse sheet resistivity with
resistance. You need to figure out what value to use in place of the 38
K/W/square.


2 5 38K/W
--+---/\/\/---+--/\/\/----/\/\/---...----

| |
| 57 /O You
'-/\/\/--O'
O

John


You can create any absurd model you wish. The point is that the path
through vias under the pad is not *hugely* different in thermal
impedance than the vias outside the pad. John says these under pad vias
are useless, the numbers presented so far say they are not useless.

I realized that John was thinking about this incorrectly when he focused
on the fact that the thermal imager seemed to show the bottom side area
under the pad was all the same temperature with no heat flow from the
center (without vias through the board). The images don't actually show
the area as isothermal and the addition of vias will change the images
greatly.

--

Rick

[dagmarg...@yahoo.com]

On Thursday, July 3, 2014 11:25:59 AM UTC-4, John Larkin wrote:

Definitely. The old rule-of-thumb was 1 sq. in. is good for 1W with
convection. This is a lab environment, 40oC max., with some forced air,
which adds margin.

> But slap a thermocouple on the tab and be sure.

I can't--I've never even seen the board, probably won't, don't know
who even makes them. It would be an absurd situation, of course, but
the customer has made mods, taken on the responsibility for their mods,
and only wants the soldering problem fixed.

> "Loads unknown" does make analysis more difficult.

Naturally. I'm wary, but it's out of my hands (quite literally).

All of this is from the customer's reticence to hire. They outsource
almost everything to avoid Obama-type entanglements.

I guess the accountants like it, but it complicates designing products.
There's no inventory, no approved parts list, so all the parts have to
be qualified from scratch for each design. Time-consuming, and adds
errors.

I get a fair amount outsourced from Germany. Apparently they're even
more eager to avoid hiring actual people.

> I tested a SOT89 (Supertex DN2530 depletion fet) for power capability, and
> decided it would be fine at 3 watts with some reasonable copper pours.
>
> Engineering isn't about proving how smart you are, or about showing how dumb
> other people are, or indeed about proving anything at all. It's about building
> things that work and getting purchase orders for same.

I like Jerry's sig, "Engineering is making what you need from what you have"
(or something like that).

Cheers,
James Arthur

[dagmarg...@yahoo.com]

On Thursday, July 3, 2014 5:48:57 PM UTC-4, rickman wrote:

If you thought John meant to move the vias to 'A' and 'B', that would
certainly explain all your objections.

I never understood any of John's posts to say that. He said to move most
of the vias to the tab's edges, namely, points '1' and '2'.

You're missing what's quite obvious, getting lost in details
that don't matter, possibly because you misunderstood what John posted.

The D-PAK tab is a thermal short. It's so much better than the 2oz
copper we don't *have to* go any farther--using thermal vias to reduce
heat flow through that thermal short is not as effective as using the
D-PAK tab and the vias to jumper past part of the thermal resistance
of the bottom copper pour.

I don't know how to put it any simpler than that.

I've drawn loads of simplified conceptual ASCII drawings to try and
get that across, but you keep pouncing on the details instead.

Yes, the drawings are over-simplified. If you want to do a full-
detail ASCII drawing in 3-D showing all the individual vias, layers
and pours, we're all eyeballs.

> Your comment above is
> a perfect example. You have presented no data that can be usefully
> compared regarding the vias under the part.

I beg to differ. I believe I've presented more than enough for someone
skilled in the art to immediately understand the merits.

I've just been trying, six different ways from Sunday, to explain
that it makes little difference to the D-PAK how you shuffle the
thermal vias under its tab--the tab is a thermal short. But it
makes a difference to the bottom pour if you can skip over a
chunk in the process, since the bottom pour's spreading resistance
is over an order of magnitude higher.

> >> John looked at a thermal image and decided that because on a board with
> >> no vias the temperature in a small area *appeared* to have little
> >> temperature difference there could be no heat flow if vias were added to
> >> the board under the package.
> >
> > Of course adding vias anywhere helps, if only marginally. But, for a
> > given number, moving them from the edge to the center detracts, not adds.
>
>
> That is the issue, what is "marginal". From the data shown by John I
> estimate the vias in the center of the part will have no more than twice
> the thermal resistance as the vias outside the edge of the part. So if
> they can be added, I would add them.

But we already have them--the whole aim here is to reduce or eliminate
them, because they're sucking solder!

> >> Sure it is better to have vias at the edge
> >> of the chip, but adding vias at the center will still provide additional
> >> cooling in a significant manner. It is exactly the same as parallel
> >> resistors. Two 10 ohm resistors in series, the pair in parallel with a
> >> single 10 ohm resistor lowers the circuit impedance significantly and
> >> also the voltage drop for a constant current which is the analog to the
> >> thermal issue we are discussing.
> >
> > 2 5 38K/W
> > --+---/\/\/---+--/\/\/--+--/\/\/---...----
> > | | |
> > | 57 /O You |
> > '-/\/\/--O' |
> > O---------'
> > John
> >
> > If there's already a 2 ohm resistance to a point, then 5 ohms extra
> > (or, before you jump on it again, <whatever> value it might be) to a
> > further point, it's better to connect every one of your 57 ohm resistors
> > past the 5 ohms than before it.
>
> I have no idea where you get these values.

If you had the physical model in mind, there shouldn't be any confusion.
2 ohms is very roughly the half of the D-PAK tab from die to each edge.

5 ohms is *very* order-of-magnitude approximately from "X" to "1" or "2"
on the pour. In retrospect the actual is closer to three squares in
parallel, or 13 ohms in this analogy, not 5.

But you're far too literal. It's not intended to be an accurate model AT
ALL, just illustrating, yet again, the two via-placement possibilities.

> I believe the 57 you show is one via?

Of course.

> But what are the 2 and the 5 and the 38? Are you trying to
> show the effect of adding one via to a board with dozens of vias
> already?

No, showing the incremental effect of any given via.

> BTW, John's point is not to move the via to another location.
> He says the vias have no value which means drop them entirely. If I
> can add a dozen vias under the pad, in your model, it looks like I would
> have about 5 in parallel with 2 which would still produce a useful
> improvement.

> Oh, you continue to confuse sheet resistivity with
> resistance.

No, actually. I've showed the heat-spread in one dimension for
clarity.

Besides that, as explained by the dimensions, the pour is precisely two
squares, one on either side of centerline, each 38 K/W. If I feed the
square's edge with a line of thermal vias, that's a very accurate
approximation, and even still is quite an irrelevant detail when
comparing to a D-PAK tab that's 19 times thicker. I shouldn't
have to explain this.

> You need to figure out what value to use in place of the 38
> K/W/square.

Okay, I give up. But it was fun, and helped clarify some stuff.

Thanks.


Cheers,
James Arthur

[rickman]

John has said many different things. In some posts he says to move the
vias to both just inside and outside the edge of the part. In the post

of 6/25 he says:

> The vias in the interior of the array are doing almost no good,
because they are in the middle of a hot spot.

I've asked him if he modifies this to simply mean the interior vias pass
*less* heat than the exterior vias and he is emphatic that they pass no
useful heat. So there is still some question about what is "useful"
heat. But that is an aside from the other issue that none of his data
supports this claim. Your data is no better.

You said this very clearly, "oversimplified" to the point of being
useless. Although if you change sheet resistivity to a value of
resistance the diagram is very useful. What is important is the
relative values of each component in the diagram. Oh, you also have to
explain where your numbers come from.

>> Your comment above is
>> a perfect example. You have presented no data that can be usefully
>> compared regarding the vias under the part.
>
> I beg to differ. I believe I've presented more than enough for someone
> skilled in the art to immediately understand the merits.
>
> I've just been trying, six different ways from Sunday, to explain
> that it makes little difference to the D-PAK how you shuffle the
> thermal vias under its tab--the tab is a thermal short. But it
> makes a difference to the bottom pour if you can skip over a
> chunk in the process, since the bottom pour's spreading resistance
> is over an order of magnitude higher.

Yes, your have tried, but each time you present data that has problems.
You also fail to understand my point. Again, I have never said there
is *no* difference between vias under the part and vias outside the
part. I am saying you and John have not presented evidence that the
difference makes under part vias useless. You *can* have vias in both
places giving a better solution and giving your part a lower temperature
or allowing a higher power dissipation.

>>>> John looked at a thermal image and decided that because on a board with
>>>> no vias the temperature in a small area *appeared* to have little
>>>> temperature difference there could be no heat flow if vias were added to
>>>> the board under the package.
>>>
>>> Of course adding vias anywhere helps, if only marginally. But, for a
>>> given number, moving them from the edge to the center detracts, not adds.
>>
>>
>> That is the issue, what is "marginal". From the data shown by John I
>> estimate the vias in the center of the part will have no more than twice
>> the thermal resistance as the vias outside the edge of the part. So if
>> they can be added, I would add them.
>
> But we already have them--the whole aim here is to reduce or eliminate
> them, because they're sucking solder!

Yes, that is an issue. But I am addressing an absolute statement by
John, that's all. You can deal with the solder sucking issue in many
ways. But a poor thermal analysis doesn't help that. I am just
refuting some of John's ill conceived ideas.

>>>> Sure it is better to have vias at the edge
>>>> of the chip, but adding vias at the center will still provide additional
>>>> cooling in a significant manner. It is exactly the same as parallel
>>>> resistors. Two 10 ohm resistors in series, the pair in parallel with a
>>>> single 10 ohm resistor lowers the circuit impedance significantly and
>>>> also the voltage drop for a constant current which is the analog to the
>>>> thermal issue we are discussing.
>>>
>>> 2 5 38K/W
>>> --+---/\/\/---+--/\/\/--+--/\/\/---...----
>>> | | |
>>> | 57 /O You |
>>> '-/\/\/--O' |
>>> O---------'
>>> John
>>>
>>> If there's already a 2 ohm resistance to a point, then 5 ohms extra
>>> (or, before you jump on it again, <whatever> value it might be) to a
>>> further point, it's better to connect every one of your 57 ohm resistors
>>> past the 5 ohms than before it.
>>
>> I have no idea where you get these values.
>
> If you had the physical model in mind, there shouldn't be any confusion.
> 2 ohms is very roughly the half of the D-PAK tab from die to each edge.
>
> 5 ohms is *very* order-of-magnitude approximately from "X" to "1" or "2"
> on the pour. In retrospect the actual is closer to three squares in
> parallel, or 13 ohms in this analogy, not 5.

Ok, then your drawing is wrong. John's vias do not short past the 2
ohms of the DPAK. There is only a very high resistance path to the
copper pour other than through the vias which is not reflected in your
drawing.

Not sure how you estimate the "squares" in the 5 ohm path because the
path is radial outward from a via in roughly 180 degrees. Still,
ignoring that the number of squares depends greatly on the spacing of
the inner vias and how far they are from the edge. If you only place
one additional via in the center that is the worst possible case and all
others will be improved.

> But you're far too literal. It's not intended to be an accurate model AT
> ALL, just illustrating, yet again, the two via-placement possibilities.
>
>> I believe the 57 you show is one via?
>
> Of course.
>
>> But what are the 2 and the 5 and the 38? Are you trying to
>> show the effect of adding one via to a board with dozens of vias
>> already?
>
> No, showing the incremental effect of any given via.
>
>> BTW, John's point is not to move the via to another location.
>> He says the vias have no value which means drop them entirely. If I
>> can add a dozen vias under the pad, in your model, it looks like I would
>> have about 5 in parallel with 2 which would still produce a useful
>> improvement.
>
>> Oh, you continue to confuse sheet resistivity with
>> resistance.
>
> No, actually. I've showed the heat-spread in one dimension for
> clarity.

But 38 K/W is sheet resistivity, no? If that is your thermal resistance
then none of this matters much since the lion's share of the temperature
drop will be there.

> Besides that, as explained by the dimensions, the pour is precisely two
> squares, one on either side of centerline, each 38 K/W. If I feed the
> square's edge with a line of thermal vias, that's a very accurate
> approximation, and even still is quite an irrelevant detail when
> comparing to a D-PAK tab that's 19 times thicker. I shouldn't
> have to explain this.

If that is true, then the vias matter little in any case. Put them
where they work best for other reasons as they will have little impact
on the final die temperature.

Die 2 Edge of part
--+---/\/\/---+
| Pad |
\ \
/ /
\ Via \ Via
/ /
\ \
| 5 | 38
+---/\/\/---+--/\/\/---...----
Pour Pour

Clearly if the vias are 57 K/W the added 3 K/W difference between the
two paths is not significant and both will produce very similar cooling.
Even if the 5 turns into 13 the difference between 70 and 59 is not
large. So clearly your data shows the vias inside the part outline and
vias at the edge are not so much different and John's claim is not valid,

> The vias in the interior of the array are doing almost no good,
because they are in the middle of a hot spot.

"almost no good" is clearly not supported by the evidence.

>> You need to figure out what value to use in place of the 38
>> K/W/square.
>
> Okay, I give up. But it was fun, and helped clarify some stuff.

Yes, it does make things more clear.

--

Rick

[Jasen Betts]

On 2014-07-03, rickman <gnu...@gmail.com> wrote:

>>
>> Of course adding vias anywhere helps, if only marginally. But, for a
>> given number, moving them from the edge to the center detracts, not adds.
>
> That is the issue, what is "marginal". From the data shown by John I
> estimate the vias in the center of the part will have no more than twice
> the thermal resistance as the vias outside the edge of the part. So if
> they can be added, I would add them.

sure, However if I could instead add more at the edge of the part I would
add them there first.


--
umop apisdn


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