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better 4046 PLL
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John Larkin
Jun 25, 2013, 4:06:32 PM6/25/13
to
I have a good customer who wants us to build a weird glue-logic fanout
box to solve some system problems. One thing they want to do is give
us a 40 KHz clock and want us to output 100 KHz.
A 4046 or HC4046 could multiply by 5 to 200K, then we could divide by
2 to 100K. That would use the drecky 4046 VCO and the drekkier phase
detector with tons of phase noise. Is there a better 4046 chip around,
or some equivalently simple pll/vco chip?
This is a sort of charity job, no reason to do it except that it's a
good customer. I want to keep it simple, no uP code, no FPGAs to
program, all old fashioned hardware.
--
John Larkin Highland Technology, Inc
jlarkin at highlandtechnology dot com
http://www.highlandtechnology.com
Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Custom laser drivers and controllers
Photonics and fiberoptic TTL data links
VME thermocouple, LVDT, synchro acquisition and simulation
papab...@gmail.com
Jun 25, 2013, 4:28:57 PM6/25/13
to
On Tuesday, June 25, 2013 3:06:32 PM UTC-5, John Larkin wrote:
> I have a good customer who wants us to build a weird glue-logic fanout
>
> box to solve some system problems. One thing they want to do is give
>
> us a 40 KHz clock and want us to output 100 KHz.
>
> I have a good customer who wants us to build a weird glue-logic fanout
>
> box to solve some system problems. One thing they want to do is give
>
> us a 40 KHz clock and want us to output 100 KHz.
>
> John Larkin Highland Technology, Inc
>
Couldn't you use XOR gates to multiply by 10 and then divide by 4 with a couple of flip-flops?
>
Regards,
Ray
Phil Hobbs
Jun 25, 2013, 4:39:35 PM6/25/13
to
On 06/25/2013 04:06 PM, John Larkin wrote:
>
>
> I have a good customer who wants us to build a weird glue-logic fanout
> box to solve some system problems. One thing they want to do is give
> us a 40 KHz clock and want us to output 100 KHz.
>
> A 4046 or HC4046 could multiply by 5 to 200K, then we could divide by
> 2 to 100K. That would use the drecky 4046 VCO and the drekkier phase
> detector with tons of phase noise. Is there a better 4046 chip around,
> or some equivalently simple pll/vco chip?
>
> This is a sort of charity job, no reason to do it except that it's a
> good customer. I want to keep it simple, no uP code, no FPGAs to
> program, all old fashioned hardware.
>
>
What's the accuracy spec on the 40 kHz?
>
>
> I have a good customer who wants us to build a weird glue-logic fanout
> box to solve some system problems. One thing they want to do is give
> us a 40 KHz clock and want us to output 100 KHz.
>
> A 4046 or HC4046 could multiply by 5 to 200K, then we could divide by
> 2 to 100K. That would use the drecky 4046 VCO and the drekkier phase
> detector with tons of phase noise. Is there a better 4046 chip around,
> or some equivalently simple pll/vco chip?
>
> This is a sort of charity job, no reason to do it except that it's a
> good customer. I want to keep it simple, no uP code, no FPGAs to
> program, all old fashioned hardware.
>
>
If it fits within a +- 50 ppm tuning range, I'd tend to multiply up to,
say, 8 MHz with a VCXO and divide down again. The 4046's PFD is better
than good enough for that. VCXOs are pretty cheap, about $3 in onesies,
e.g. http://tinyurl.com/q8nrqlt .
I've used LC VCOs in similar situations. Really dramatically better
than a 4046's oscillator.
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics
160 North State Road #203
Briarcliff Manor NY 10510
hobbs at electrooptical dot net
http://electrooptical.net
Tim Wescott
Jun 25, 2013, 4:44:59 PM6/25/13
to
On Tue, 25 Jun 2013 13:06:32 -0700, John Larkin wrote:
> I have a good customer who wants us to build a weird glue-logic fanout
> box to solve some system problems. One thing they want to do is give us
> a 40 KHz clock and want us to output 100 KHz.
>
> A 4046 or HC4046 could multiply by 5 to 200K, then we could divide by 2
> to 100K. That would use the drecky 4046 VCO and the drekkier phase
> detector with tons of phase noise. Is there a better 4046 chip around,
> or some equivalently simple pll/vco chip?
>
> This is a sort of charity job, no reason to do it except that it's a
> good customer. I want to keep it simple, no uP code, no FPGAs to
> program, all old fashioned hardware.
I think there's a 7046 from someone, but (a) I don't know if it's
> I have a good customer who wants us to build a weird glue-logic fanout
> box to solve some system problems. One thing they want to do is give us
> a 40 KHz clock and want us to output 100 KHz.
>
> A 4046 or HC4046 could multiply by 5 to 200K, then we could divide by 2
> to 100K. That would use the drecky 4046 VCO and the drekkier phase
> detector with tons of phase noise. Is there a better 4046 chip around,
> or some equivalently simple pll/vco chip?
>
> This is a sort of charity job, no reason to do it except that it's a
> good customer. I want to keep it simple, no uP code, no FPGAs to
> program, all old fashioned hardware.
74HC7046, 74AC7046, 74YMMV7046, or what, and (b) I don't know if it's
still available.
Do they really need 100kHz that's better than what the "drecky" 4046 can
supply? If not, why complain?
--
Tim Wescott
Wescott Design Services
http://www.wescottdesign.com
John Larkin
Jun 25, 2013, 5:12:36 PM6/25/13
to
On Tue, 25 Jun 2013 16:39:35 -0400, Phil Hobbs
<pcdhSpamM...@electrooptical.net> wrote:
>On 06/25/2013 04:06 PM, John Larkin wrote:
>>
>>
>> I have a good customer who wants us to build a weird glue-logic fanout
>> box to solve some system problems. One thing they want to do is give
>> us a 40 KHz clock and want us to output 100 KHz.
>>
>> A 4046 or HC4046 could multiply by 5 to 200K, then we could divide by
>> 2 to 100K. That would use the drecky 4046 VCO and the drekkier phase
>> detector with tons of phase noise. Is there a better 4046 chip around,
>> or some equivalently simple pll/vco chip?
>>
>> This is a sort of charity job, no reason to do it except that it's a
>> good customer. I want to keep it simple, no uP code, no FPGAs to
>> program, all old fashioned hardware.
>>
>>
>What's the accuracy spec on the 40 kHz?
Don't know yet! My main contact on this is a software guy.
<pcdhSpamM...@electrooptical.net> wrote:
>On 06/25/2013 04:06 PM, John Larkin wrote:
>>
>>
>> I have a good customer who wants us to build a weird glue-logic fanout
>> box to solve some system problems. One thing they want to do is give
>> us a 40 KHz clock and want us to output 100 KHz.
>>
>> A 4046 or HC4046 could multiply by 5 to 200K, then we could divide by
>> 2 to 100K. That would use the drecky 4046 VCO and the drekkier phase
>> detector with tons of phase noise. Is there a better 4046 chip around,
>> or some equivalently simple pll/vco chip?
>>
>> This is a sort of charity job, no reason to do it except that it's a
>> good customer. I want to keep it simple, no uP code, no FPGAs to
>> program, all old fashioned hardware.
>>
>>
>What's the accuracy spec on the 40 kHz?
>
>If it fits within a +- 50 ppm tuning range, I'd tend to multiply up to,
>say, 8 MHz with a VCXO and divide down again. The 4046's PFD is better
>than good enough for that. VCXOs are pretty cheap, about $3 in onesies,
>e.g. http://tinyurl.com/q8nrqlt .
it would lock.
>
>I've used LC VCOs in similar situations. Really dramatically better
>than a 4046's oscillator.
anywhere from narrowband to octave range. I could put one on the board
layout, as an option to the 4046 VCO.
Thanks
Jim Thompson
Jun 25, 2013, 5:23:53 PM6/25/13
to
didn't. It's some poor copy, done by... I have no clue. The VCO, in
particular, is a real kludge.
...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| San Tan Valley, AZ 85142 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
Michael A. Terrell
Jun 25, 2013, 5:29:14 PM6/25/13
to
Tim Wescott wrote:
>
> On Tue, 25 Jun 2013 13:06:32 -0700, John Larkin wrote:
>
> > I have a good customer who wants us to build a weird glue-logic fanout
> > box to solve some system problems. One thing they want to do is give us
> > a 40 KHz clock and want us to output 100 KHz.
> >
> > A 4046 or HC4046 could multiply by 5 to 200K, then we could divide by 2
> > to 100K. That would use the drecky 4046 VCO and the drekkier phase
> > detector with tons of phase noise. Is there a better 4046 chip around,
> > or some equivalently simple pll/vco chip?
> >
> > This is a sort of charity job, no reason to do it except that it's a
> > good customer. I want to keep it simple, no uP code, no FPGAs to
> > program, all old fashioned hardware.
>
> I think there's a 7046 from someone, but (a) I don't know if it's
> 74HC7046, 74AC7046, 74YMMV7046, or what, and (b) I don't know if it's
> still available.
John Larkin
Jun 25, 2013, 5:53:00 PM6/25/13
to
On Tue, 25 Jun 2013 14:23:53 -0700, Jim Thompson
<To-Email-Use-Th...@On-My-Web-Site.com> wrote:
>On Tue, 25 Jun 2013 15:44:59 -0500, Tim Wescott
><t...@seemywebsite.really> wrote:
>
>>On Tue, 25 Jun 2013 13:06:32 -0700, John Larkin wrote:
>>
>>> I have a good customer who wants us to build a weird glue-logic fanout
>>> box to solve some system problems. One thing they want to do is give us
>>> a 40 KHz clock and want us to output 100 KHz.
>>>
>>> A 4046 or HC4046 could multiply by 5 to 200K, then we could divide by 2
>>> to 100K. That would use the drecky 4046 VCO and the drekkier phase
>>> detector with tons of phase noise. Is there a better 4046 chip around,
>>> or some equivalently simple pll/vco chip?
>>>
>>> This is a sort of charity job, no reason to do it except that it's a
>>> good customer. I want to keep it simple, no uP code, no FPGAs to
>>> program, all old fashioned hardware.
>>
>>I think there's a 7046 from someone, but (a) I don't know if it's
>>74HC7046, 74AC7046, 74YMMV7046, or what, and (b) I don't know if it's
>>still available.
>>
>>Do they really need 100kHz that's better than what the "drecky" 4046 can
>>supply? If not, why complain?
>
>"Drecky" is a Larkin comment only because he thinks I designed it. I
>didn't. It's some poor copy, done by... I have no clue. The VCO, in
>particular, is a real kludge.
You just made no sense at all. You agree with me that the 4046 is a
<To-Email-Use-Th...@On-My-Web-Site.com> wrote:
>On Tue, 25 Jun 2013 15:44:59 -0500, Tim Wescott
><t...@seemywebsite.really> wrote:
>
>>On Tue, 25 Jun 2013 13:06:32 -0700, John Larkin wrote:
>>
>>> I have a good customer who wants us to build a weird glue-logic fanout
>>> box to solve some system problems. One thing they want to do is give us
>>> a 40 KHz clock and want us to output 100 KHz.
>>>
>>> A 4046 or HC4046 could multiply by 5 to 200K, then we could divide by 2
>>> to 100K. That would use the drecky 4046 VCO and the drekkier phase
>>> detector with tons of phase noise. Is there a better 4046 chip around,
>>> or some equivalently simple pll/vco chip?
>>>
>>> This is a sort of charity job, no reason to do it except that it's a
>>> good customer. I want to keep it simple, no uP code, no FPGAs to
>>> program, all old fashioned hardware.
>>
>>I think there's a 7046 from someone, but (a) I don't know if it's
>>74HC7046, 74AC7046, 74YMMV7046, or what, and (b) I don't know if it's
>>still available.
>>
>>Do they really need 100kHz that's better than what the "drecky" 4046 can
>>supply? If not, why complain?
>
>"Drecky" is a Larkin comment only because he thinks I designed it. I
>didn't. It's some poor copy, done by... I have no clue. The VCO, in
>particular, is a real kludge.
pretty bad part. I never said you designed it, and never suspected
that you did. It was an old RCA design originally.
We were talking about PLLs, and you start your idiotic squabbling as
usual. You want to make trouble because you're a mean-spirted paranoid
old git. You're not very good at it.
Hey, Mo won a 1-week all-expenses scholarship to a course at BU (over
a thousand applicants, 20 selected from all over the world) and she
has a very nice dorm room. You know, the very same dorms that you used
to peep into the windows of, when you were there roughly a century
ago. The only real compensation of having one's wife out of town is
that I can eat serious meat three times a day.
Spehro Pefhany
Jun 25, 2013, 5:57:08 PM6/25/13
to
board to program it.
http://www.cirrus.com/en/pubs/proDatasheet/CS2300-OTP_F2.pdf
Only goes down to 6MHz on the output, so it would be at least a 2-chip
solution.
John Larkin
Jun 25, 2013, 5:58:14 PM6/25/13
to
for the link.
Jim Thompson
Jun 25, 2013, 6:51:20 PM6/25/13
to
I never "peeped"... I never joined a frat. I just observed what the
frats did with their front rooms... and you carried that observation
to an all-time-high insane rant.
If you have to wait for your wife to be out of town to "eat serious
meat" you must be pussy whipped >:-} (Not that I'm surprised :-)
As for you understanding PLL's... Bwahahahahahahaha!
John Larkin
Jun 25, 2013, 7:22:44 PM6/25/13
to
On Tue, 25 Jun 2013 15:51:20 -0700, Jim Thompson
http://www.highlandtechnology.com/DSS/V880DS.shtml
Under 3 ps RMS jitter, way under 1 ps/degreeC total-board timing
drift, locking to an OC3 fiberoptic serial data stream. The Vectron
OC3 fiber receivers went out of production halfway through the
project, so I had to design my own. That was tricky, keeping the phase
shift low over 20 dB of optical power level.
It's a bang-bang adaptive-loop d-flop phase detector in differential
Eclips Plus SiGe logic. The major phase noise contributor was
vibration, so I designed some tiny wireform springs to isolate the
nice massive DIP14 ecl vcxo from the PC board. Sort of little
bobblehead dolls like you see in the backs of cars, mechanical
resonance around 10 Hz.
There are a few hundred of these boards firing a couple thousand
client devices in NIF, picoseconds of precision across acres of
facility.
https://dl.dropboxusercontent.com/u/53724080/Jitter3.gif
Many of our boards have PLLs, analog and digital. I've posted about
some before, so your statement above is stupid, as usual.
Under 3 ps RMS jitter, way under 1 ps/degreeC total-board timing
drift, locking to an OC3 fiberoptic serial data stream. The Vectron
OC3 fiber receivers went out of production halfway through the
project, so I had to design my own. That was tricky, keeping the phase
shift low over 20 dB of optical power level.
It's a bang-bang adaptive-loop d-flop phase detector in differential
Eclips Plus SiGe logic. The major phase noise contributor was
vibration, so I designed some tiny wireform springs to isolate the
nice massive DIP14 ecl vcxo from the PC board. Sort of little
bobblehead dolls like you see in the backs of cars, mechanical
resonance around 10 Hz.
There are a few hundred of these boards firing a couple thousand
client devices in NIF, picoseconds of precision across acres of
facility.
https://dl.dropboxusercontent.com/u/53724080/Jitter3.gif
Many of our boards have PLLs, analog and digital. I've posted about
some before, so your statement above is stupid, as usual.
Bill Sloman
Jun 25, 2013, 7:32:54 PM6/25/13
to
On Wednesday, 26 June 2013 07:58:14 UTC+10, John Larkin wrote:
> On Tue, 25 Jun 2013 17:29:14 -0400, "Michael A. Terrell"
> <mike.t...@earthlink.net> wrote:
> >Tim Wescott wrote:
> >> On Tue, 25 Jun 2013 13:06:32 -0700, John Larkin wrote:
> >>
> >> > I have a good customer who wants us to build a weird glue-logic fanout
> >> > box to solve some system problems. One thing they want to do is give us
> >> > a 40 KHz clock and want us to output 100 KHz.
> >> >
> >> > A 4046 or HC4046 could multiply by 5 to 200K, then we could divide by 2
> >> > to 100K. That would use the drecky 4046 VCO and the drekkier phase
> >> > detector with tons of phase noise. Is there a better 4046 chip around,
> >> > or some equivalently simple pll/vco chip?
> >> >
> >> > This is a sort of charity job, no reason to do it except that it's a
> >> > good customer. I want to keep it simple, no uP code, no FPGAs to
> >> > program, all old fashioned hardware.
> >>
> >> I think there's a 7046 from someone, but (a) I don't know if it's
> >> 74HC7046, 74AC7046, 74YMMV7046, or what, and (b) I don't know if it's
> >> still available.
> >
> >http://www.nxp.com/documents/data_sheet/74HCT9046A.pdf
>
> That looks a lot better than a 4046, and runs to 15 MHz typ. Thanks
> for the link.
The data sheet emphasises "No dead zone of PC2" and "Charge pump output on PC2, whose current is set by an external resistor Rbias" which means that you can put together and integrator-based (second order) phase-locked loop without having to provide an op amp to do the integration.
> On Tue, 25 Jun 2013 17:29:14 -0400, "Michael A. Terrell"
> <mike.t...@earthlink.net> wrote:
> >Tim Wescott wrote:
> >> On Tue, 25 Jun 2013 13:06:32 -0700, John Larkin wrote:
> >>
> >> > I have a good customer who wants us to build a weird glue-logic fanout
> >> > box to solve some system problems. One thing they want to do is give us
> >> > a 40 KHz clock and want us to output 100 KHz.
> >> >
> >> > A 4046 or HC4046 could multiply by 5 to 200K, then we could divide by 2
> >> > to 100K. That would use the drecky 4046 VCO and the drekkier phase
> >> > detector with tons of phase noise. Is there a better 4046 chip around,
> >> > or some equivalently simple pll/vco chip?
> >> >
> >> > This is a sort of charity job, no reason to do it except that it's a
> >> > good customer. I want to keep it simple, no uP code, no FPGAs to
> >> > program, all old fashioned hardware.
> >>
> >> I think there's a 7046 from someone, but (a) I don't know if it's
> >> 74HC7046, 74AC7046, 74YMMV7046, or what, and (b) I don't know if it's
> >> still available.
> >
> >http://www.nxp.com/documents/data_sheet/74HCT9046A.pdf
>
> That looks a lot better than a 4046, and runs to 15 MHz typ. Thanks
> for the link.
It's been recommended here from time to time over the years.
The VCO frequency may be tolerably linear function of input voltage - over the input voltage range for which it works, but it stops working at low input voltages, and only offers a roughly 3:1 frequency range.This shouldn't be a problem in your application.
Digi-Key Australia stocks it (19,901 in in stock), for $A3.18 in small quantities, which is comforting - IIRR Farnell gave up on it years ago.
--
Bill Sloman, Sydney
Jim Thompson
Jun 25, 2013, 7:34:48 PM6/25/13
to
On Tue, 25 Jun 2013 16:22:44 -0700, John Larkin
So why didn't you know of the modern HC/HCT versions?
And you're still pussy-whipped >:-}
And a bird-brain.
And you're still pussy-whipped >:-}
And a bird-brain.
Phil Hobbs
Jun 25, 2013, 7:54:11 PM6/25/13
to
thing, with a part that costs $0.17 in qty 25 (Arrow).
The metal-gate 4046 is quite pretty in a 1970ish way--the oscillator can
cover way over 100:1 in frequency. Later models, starting with the
HC4046, are OK as phase detectors if you remember the resistor, but the
oscillators really stink. We went round that mulberry bush in fairly
gruesome detail about 8 months ago in this very boutique.
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics
160 North State Road #203
+1 845 480 2058
John Larkin
Jun 25, 2013, 8:11:48 PM6/25/13
to
On Tue, 25 Jun 2013 16:34:48 -0700, Jim Thompson
Because it's a discussion group, where people help one another out.
You clearly don't get the concept. All you do here is boast and call
other people stupid. And spin technical discussions into bitch-fests.
>
>And you're still pussy-whipped >:-}
>
No complaints. I can't imagine a better woman to do it to me.
I'm reminded of a frat party I went to once (as a guest, not a
member.) A guy had a tee shirt with two big letters PW on the front.
The beautiful girl next to him had a shirt with one big letter, P.
You clearly don't get the concept. All you do here is boast and call
other people stupid. And spin technical discussions into bitch-fests.
>
>And you're still pussy-whipped >:-}
>
I'm reminded of a frat party I went to once (as a guest, not a
member.) A guy had a tee shirt with two big letters PW on the front.
The beautiful girl next to him had a shirt with one big letter, P.
Tim Wescott
Jun 25, 2013, 8:11:52 PM6/25/13
to
than "many".
(Thanks for taking my imperfect recollection and turning it into
something accurate).
It looks like DigiKey has oodles.
John Larkin
Jun 25, 2013, 8:15:19 PM6/25/13
to
On Tue, 25 Jun 2013 19:11:52 -0500, Tim Wescott
<t...@seemywebsite.really> wrote:
>On Tue, 25 Jun 2013 17:29:14 -0400, Michael A. Terrell wrote:
>
>> Tim Wescott wrote:
>>>
>>> On Tue, 25 Jun 2013 13:06:32 -0700, John Larkin wrote:
>>>
>>> > I have a good customer who wants us to build a weird glue-logic
>>> > fanout box to solve some system problems. One thing they want to do
>>> > is give us a 40 KHz clock and want us to output 100 KHz.
>>> >
>>> > A 4046 or HC4046 could multiply by 5 to 200K, then we could divide by
>>> > 2 to 100K. That would use the drecky 4046 VCO and the drekkier phase
>>> > detector with tons of phase noise. Is there a better 4046 chip
>>> > around, or some equivalently simple pll/vco chip?
>>> >
>>> > This is a sort of charity job, no reason to do it except that it's a
>>> > good customer. I want to keep it simple, no uP code, no FPGAs to
>>> > program, all old fashioned hardware.
>>>
>>> I think there's a 7046 from someone, but (a) I don't know if it's
>>> 74HC7046, 74AC7046, 74YMMV7046, or what, and (b) I don't know if it's
>>> still available.
>>
>>
>> http://www.nxp.com/documents/data_sheet/74HCT9046A.pdf
>
>Seven, nine, eh, what's the difference? It's an odd number, and bigger
>than "many".
It's 2.236 times better than a 4046.
<t...@seemywebsite.really> wrote:
>On Tue, 25 Jun 2013 17:29:14 -0400, Michael A. Terrell wrote:
>
>> Tim Wescott wrote:
>>>
>>> On Tue, 25 Jun 2013 13:06:32 -0700, John Larkin wrote:
>>>
>>> > I have a good customer who wants us to build a weird glue-logic
>>> > fanout box to solve some system problems. One thing they want to do
>>> > is give us a 40 KHz clock and want us to output 100 KHz.
>>> >
>>> > A 4046 or HC4046 could multiply by 5 to 200K, then we could divide by
>>> > 2 to 100K. That would use the drecky 4046 VCO and the drekkier phase
>>> > detector with tons of phase noise. Is there a better 4046 chip
>>> > around, or some equivalently simple pll/vco chip?
>>> >
>>> > This is a sort of charity job, no reason to do it except that it's a
>>> > good customer. I want to keep it simple, no uP code, no FPGAs to
>>> > program, all old fashioned hardware.
>>>
>>> I think there's a 7046 from someone, but (a) I don't know if it's
>>> 74HC7046, 74AC7046, 74YMMV7046, or what, and (b) I don't know if it's
>>> still available.
>>
>>
>> http://www.nxp.com/documents/data_sheet/74HCT9046A.pdf
>
>Seven, nine, eh, what's the difference? It's an odd number, and bigger
>than "many".
Jim Thompson
Jun 25, 2013, 8:18:25 PM6/25/13
to
On Tue, 25 Jun 2013 17:11:48 -0700, John Larkin
That's actually funny... so rare for you ;-)
John Fields
Jun 25, 2013, 8:47:45 PM6/25/13
to
>Hey, Mo won a 1-week all-expenses scholarship to a course at BU (over
>a thousand applicants, 20 selected from all over the world) and she
>has a very nice dorm room. You know, the very same dorms that you used
>to peep into the windows of, when you were there roughly a century
>ago. The only real compensation of having one's wife out of town is
>that I can eat serious meat three times a day.
---
>a thousand applicants, 20 selected from all over the world) and she
>has a very nice dorm room. You know, the very same dorms that you used
>to peep into the windows of, when you were there roughly a century
>ago. The only real compensation of having one's wife out of town is
>that I can eat serious meat three times a day.
So she has you on a short leash when she's around, but hasn't quite
figured out how to control you remotely?
Does "pussywhipped" mean the same thing in San Francisco that it does
in Austin?
--
JF
Jim Thompson
Jun 25, 2013, 9:27:16 PM6/25/13
to
John Larkin
Jun 25, 2013, 10:06:53 PM6/25/13
to
>On Tue, 25 Jun 2013 14:53:00 -0700, John Larkin
><jla...@highlandtechnology.com> wrote:
>
>
>>Hey, Mo won a 1-week all-expenses scholarship to a course at BU (over
>>a thousand applicants, 20 selected from all over the world) and she
>>has a very nice dorm room. You know, the very same dorms that you used
>>to peep into the windows of, when you were there roughly a century
>>ago. The only real compensation of having one's wife out of town is
>>that I can eat serious meat three times a day.
>
>---
>So she has you on a short leash when she's around, but hasn't quite
>figured out how to control you remotely?
She doesn't like heavy meat, so we eat light, healthy food. Tastes
><jla...@highlandtechnology.com> wrote:
>
>
>>Hey, Mo won a 1-week all-expenses scholarship to a course at BU (over
>>a thousand applicants, 20 selected from all over the world) and she
>>has a very nice dorm room. You know, the very same dorms that you used
>>to peep into the windows of, when you were there roughly a century
>>ago. The only real compensation of having one's wife out of town is
>>that I can eat serious meat three times a day.
>
>---
>So she has you on a short leash when she's around, but hasn't quite
>figured out how to control you remotely?
great. But once in a while I like serious guy food. It would probably
kill me if I ate like this all the time. Probably bore me, too. I'd
hate to get jaded about baby back ribs or seriously good corned beef.
We do agree about bacon. And gelato. Her chicken dishes, paprica
chicken and chicken marsala, are superb.
It's no great hardship to eat unagi and pasta carbonara and blackened
red snapper and shrimp+grits. I cook a lot of cajun/creole, and she
cooks a lot of California and Italian, and those are not traditionally
meat heavy. The fruits and veggies here in California, especially this
time of year, are fantastic.
>
>Does "pussywhipped" mean the same thing in San Francisco that it does
>in Austin?
of roommate, we'd have to agree on what we cook and eat together. No
point in two people cooking two separate meals.
Do you make all the rules in your household? No compromises at all?
Lord and Master? Do you live with a doormat?
Why do you and Jim keep cackling and squawking in a thread about PLLs?
Do you have anything to say about PLLs?
Thought not.
Bill Sloman
Jun 25, 2013, 10:18:30 PM6/25/13
to
On Wednesday, 26 June 2013 10:15:19 UTC+10, John Larkin wrote:
> On Tue, 25 Jun 2013 19:11:52 -0500, Tim Wescott
> <t...@seemywebsite.really> wrote:
> >On Tue, 25 Jun 2013 17:29:14 -0400, Michael A. Terrell wrote:
> >> Tim Wescott wrote:
> >>> On Tue, 25 Jun 2013 13:06:32 -0700, John Larkin wrote:
> >>>
> >>> > I have a good customer who wants us to build a weird glue-logic
> >>> > fanout box to solve some system problems. One thing they want to do
> >>> > is give us a 40 KHz clock and want us to output 100 KHz.
> >>> >
> >>> > A 4046 or HC4046 could multiply by 5 to 200K, then we could divide by
> >>> > 2 to 100K. That would use the drecky 4046 VCO and the drekkier phase
> >>> > detector with tons of phase noise. Is there a better 4046 chip
> >>> > around, or some equivalently simple pll/vco chip?
> >>> >
> >>> > This is a sort of charity job, no reason to do it except that it's a
> >>> > good customer. I want to keep it simple, no uP code, no FPGAs to
> >>> > program, all old fashioned hardware.
> >>>
> >>> I think there's a 7046 from someone, but (a) I don't know if it's
> >>> 74HC7046, 74AC7046, 74YMMV7046, or what, and (b) I don't know if it's
> >>> still available.
> >>
> >> http://www.nxp.com/documents/data_sheet/74HCT9046A.pdf
> >
> >Seven, nine, eh, what's the difference? It's an odd number, and bigger
> >than "many".
Nine would have been better than seven.
> On Tue, 25 Jun 2013 19:11:52 -0500, Tim Wescott
> <t...@seemywebsite.really> wrote:
> >On Tue, 25 Jun 2013 17:29:14 -0400, Michael A. Terrell wrote:
> >> Tim Wescott wrote:
> >>> On Tue, 25 Jun 2013 13:06:32 -0700, John Larkin wrote:
> >>>
> >>> > I have a good customer who wants us to build a weird glue-logic
> >>> > fanout box to solve some system problems. One thing they want to do
> >>> > is give us a 40 KHz clock and want us to output 100 KHz.
> >>> >
> >>> > A 4046 or HC4046 could multiply by 5 to 200K, then we could divide by
> >>> > 2 to 100K. That would use the drecky 4046 VCO and the drekkier phase
> >>> > detector with tons of phase noise. Is there a better 4046 chip
> >>> > around, or some equivalently simple pll/vco chip?
> >>> >
> >>> > This is a sort of charity job, no reason to do it except that it's a
> >>> > good customer. I want to keep it simple, no uP code, no FPGAs to
> >>> > program, all old fashioned hardware.
> >>>
> >>> I think there's a 7046 from someone, but (a) I don't know if it's
> >>> 74HC7046, 74AC7046, 74YMMV7046, or what, and (b) I don't know if it's
> >>> still available.
> >>
> >> http://www.nxp.com/documents/data_sheet/74HCT9046A.pdf
> >
> >Seven, nine, eh, what's the difference? It's an odd number, and bigger
> >than "many".
There is a 7046
http://www.ti.com/lit/ds/symlink/cd74hc7046a.pdf
but IIRR it has only got the better - but still not very good - VCO and presumably much the same problem with the phase detector 2 as the original 4046. Phil Hobbs' pull-down resistor sort of works there too, I guess, though the difference in leakage currents through the N- and P-channel output transistors might do the same job, biasing the operating point just onto the edge of teh dead spot.
> It's 2.236 times better than a 4046.
--
Bill Sloman, Sydney
bloggs.fred...@gmail.com
Jun 25, 2013, 10:32:13 PM6/25/13
to
>
>
>
> jlarkin at highlandtechnology dot com
>
> http://www.highlandtechnology.com
>
>
>
> Precision electronic instrumentation
>
> Picosecond-resolution Digital Delay and Pulse generators
>
> Custom laser drivers and controllers
>
> Photonics and fiberoptic TTL data links
>
> VME thermocouple, LVDT, synchro acquisition and simulation
John Larkin
Jun 25, 2013, 11:05:03 PM6/25/13
to
to program a frequency is complex, if it's revealed at all.
Fox will program a VCXO to practically any frequency in a few days, their
Xpresso parts. I think some distributors will program them, too. They seem to
have a 3 GHz oscillator somewhere inside, according to our spectrum analyzer.
--
John Larkin Highland Technology Inc
www.highlandtechnology.com jlarkin at highlandtechnology dot com
Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Photonics and fiberoptic TTL data links
VME analog, thermocouple, LVDT, synchro, tachometer
Multichannel arbitrary waveform generators
John Fields
Jun 26, 2013, 11:29:44 AM6/26/13
to
On Tue, 25 Jun 2013 19:06:53 -0700, John Larkin
---
You know the answers to those questions, so now who's being silly?
---
>Why do you and Jim keep cackling and squawking in a thread about PLLs?
---
Actually, _you_ were the one who changed the direction of the thread
with your:
"Hey, Mo won a 1-week all-expenses scholarship to a course at BU (over
a thousand applicants, 20 selected from all over the world) and she
has a very nice dorm room. You know, the very same dorms that you used
to peep into the windows of, when you were there roughly a century
ago. The only real compensation of having one's wife out of town is
that I can eat serious meat three times a day."
My comment was that if you _can't_ eat "serious meat" (what you
referred to later as "serious guy food") three times a day because
_she_ doesn't like it, then you're sexist as well as whupped.
>Do you have anything to say about PLLs?
>
>Thought not.
---
Isn't that putting the cart before the horse???
In the present context, I'd say that PLL is an acronym for
Pussy Licked Larkin.
--
JF
You know the answers to those questions, so now who's being silly?
---
>Why do you and Jim keep cackling and squawking in a thread about PLLs?
Actually, _you_ were the one who changed the direction of the thread
with your:
"Hey, Mo won a 1-week all-expenses scholarship to a course at BU (over
a thousand applicants, 20 selected from all over the world) and she
has a very nice dorm room. You know, the very same dorms that you used
to peep into the windows of, when you were there roughly a century
ago. The only real compensation of having one's wife out of town is
that I can eat serious meat three times a day."
referred to later as "serious guy food") three times a day because
_she_ doesn't like it, then you're sexist as well as whupped.
>Do you have anything to say about PLLs?
>
>Thought not.
Isn't that putting the cart before the horse???
In the present context, I'd say that PLL is an acronym for
Pussy Licked Larkin.
--
JF
Jim Thompson
Jun 26, 2013, 11:54:46 AM6/26/13
to
On Tue, 25 Jun 2013 19:06:53 -0700, John Larkin
<jla...@highlandtechnology.com> wrote:
[snip]
commercial PLL parts?
Hint: It's not you.
<jla...@highlandtechnology.com> wrote:
[snip]
>Why do you and Jim keep cackling and squawking in a thread about PLLs?
>
>Do you have anything to say about PLLs?
>
Well. Who is it that has the patents on some of the very earliest
>
>Do you have anything to say about PLLs?
>
commercial PLL parts?
Hint: It's not you.
John Larkin
Jun 26, 2013, 11:59:01 AM6/26/13
to
On Wed, 26 Jun 2013 10:29:44 -0500, John Fields <jfi...@austininstruments.com>
Idiot. The thread was about PLLs until Thompson issued his entirely illogical,
off-topic attempt at insult, BEFORE I posted the reply that you quote. And your
only posts to this thread have been personal, not to mention coarse, crude, and
misogynistic.
>
>My comment was that if you _can't_ eat "serious meat" (what you
>referred to later as "serious guy food") three times a day because
>_she_ doesn't like it, then you're sexist as well as whupped.
>
>>Do you have anything to say about PLLs?
>>
>>Thought not.
>
>---
>Isn't that putting the cart before the horse???
The topic is electronics design, you moron. Any idiot can type raunchy drivel,
in bad prose or bad verse. It take some actual skill to design a PLL.
--
John Larkin Highland Technology Inc
www.highlandtechnology.com jlarkin at highlandtechnology dot com
Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Custom timing and laser controllers
off-topic attempt at insult, BEFORE I posted the reply that you quote. And your
only posts to this thread have been personal, not to mention coarse, crude, and
misogynistic.
>
>My comment was that if you _can't_ eat "serious meat" (what you
>referred to later as "serious guy food") three times a day because
>_she_ doesn't like it, then you're sexist as well as whupped.
>
>>Do you have anything to say about PLLs?
>>
>>Thought not.
>
>---
>Isn't that putting the cart before the horse???
in bad prose or bad verse. It take some actual skill to design a PLL.
--
John Larkin Highland Technology Inc
Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Photonics and fiberoptic TTL data links
John Larkin
Jun 26, 2013, 12:04:28 PM6/26/13
to
On Wed, 26 Jun 2013 08:54:46 -0700, Jim Thompson
<To-Email-Use-Th...@On-My-Web-Site.com> wrote:
>On Tue, 25 Jun 2013 19:06:53 -0700, John Larkin
><jla...@highlandtechnology.com> wrote:
>
>[snip]
>>Why do you and Jim keep cackling and squawking in a thread about PLLs?
>>
>>Do you have anything to say about PLLs?
>>
>
>Well. Who is it that has the patents on some of the very earliest
>commercial PLL parts?
>
>Hint: It's not you.
>
> ...Jim Thompson
You are all about boasting. What's the use of having your name on an expired
<To-Email-Use-Th...@On-My-Web-Site.com> wrote:
>On Tue, 25 Jun 2013 19:06:53 -0700, John Larkin
><jla...@highlandtechnology.com> wrote:
>
>[snip]
>>Why do you and Jim keep cackling and squawking in a thread about PLLs?
>>
>>Do you have anything to say about PLLs?
>>
>
>Well. Who is it that has the patents on some of the very earliest
>commercial PLL parts?
>
>Hint: It's not you.
>
> ...Jim Thompson
patent that was assigned to someone else in the first place? What did they pay
you for those patents, $50 or something? That's a sucker's game; it doesn't show
how smart you are, it shows how stupid you are.
--
John Larkin Highland Technology Inc
Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Photonics and fiberoptic TTL data links
Jim Thompson
Jun 26, 2013, 12:13:00 PM6/26/13
to
On Wed, 26 Jun 2013 09:04:28 -0700, John Larkin
<jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>On Wed, 26 Jun 2013 08:54:46 -0700, Jim Thompson
><To-Email-Use-Th...@On-My-Web-Site.com> wrote:
>
>>On Tue, 25 Jun 2013 19:06:53 -0700, John Larkin
>><jla...@highlandtechnology.com> wrote:
>>
>>[snip]
>>>Why do you and Jim keep cackling and squawking in a thread about PLLs?
>>>
>>>Do you have anything to say about PLLs?
>>>
>>
>>Well. Who is it that has the patents on some of the very earliest
>>commercial PLL parts?
>>
>>Hint: It's not you.
>>
>> ...Jim Thompson
>
>You are all about boasting. What's the use of having your name on an expired
>patent that was assigned to someone else in the first place? What did they pay
>you for those patents, $50 or something? That's a sucker's game; it doesn't show
>how smart you are, it shows how stupid you are.
You said, in another post, "It take some actual skill to design a
<jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>On Wed, 26 Jun 2013 08:54:46 -0700, Jim Thompson
><To-Email-Use-Th...@On-My-Web-Site.com> wrote:
>
>>On Tue, 25 Jun 2013 19:06:53 -0700, John Larkin
>><jla...@highlandtechnology.com> wrote:
>>
>>[snip]
>>>Why do you and Jim keep cackling and squawking in a thread about PLLs?
>>>
>>>Do you have anything to say about PLLs?
>>>
>>
>>Well. Who is it that has the patents on some of the very earliest
>>commercial PLL parts?
>>
>>Hint: It's not you.
>>
>> ...Jim Thompson
>
>You are all about boasting. What's the use of having your name on an expired
>patent that was assigned to someone else in the first place? What did they pay
>you for those patents, $50 or something? That's a sucker's game; it doesn't show
>how smart you are, it shows how stupid you are.
PLL."
So show us something technical about PLL's... something other than
your standard drivel.
You can't. You're a fraud.
John Fields
Jun 26, 2013, 12:23:34 PM6/26/13
to
On Wed, 26 Jun 2013 09:04:28 -0700, John Larkin
<jjla...@highNOTlandTHIStechnologyPART.com> wrote:
<jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>You are all about boasting. What's the use of having your name on an expired
>patent that was assigned to someone else in the first place? What did they pay
>you for those patents, $50 or something? That's a sucker's game; it doesn't show
>how smart you are, it shows how stupid you are.
---
>patent that was assigned to someone else in the first place? What did they pay
>you for those patents, $50 or something? That's a sucker's game; it doesn't show
>how smart you are, it shows how stupid you are.
John, do you hold any patents?
--
JF
John Larkin
Jun 26, 2013, 12:37:34 PM6/26/13
to
On Wed, 26 Jun 2013 09:13:00 -0700, Jim Thompson
adaptive PLL. I think I've even posted the PLL schematic here before; I can do
it again if anyone's interested.
Bang-bang loops are interesting. There has been a little academic research, but
nothing that I've found to be useful; I have my own way of thinking about them.
I did my first one when I was still a student at Tulane, for a proposal to
Boeing. People thought it wouldn't work, but it locked first time. It was a TDM
analog audio link, and I played music through it to impress the boss.
The problem in the V880 is to keep the jitter *and* the time drift down to
single digits of picoseconds. Any linear phase detector is going to have serious
problems doing that over time and temperature. An all-differential bangbang
phase detector has, in theory, infinite gain and near zero TC.
LLNL liked it.
https://dl.dropboxusercontent.com/u/53724080/NIF3.jpg
Have you done any bangbang PLLs?
All your patents need an additional claim:
12. Thompson worked 70 hour weeks, for which we paid him almost nothing, to
invent this. He's gone now, and has no rights to his invention, and we keep
making millions selling these chips. He is however allowed to brag, to bored
dinner guests, about how smart he is.
<To-Email-Use-Th...@On-My-Web-Site.com> wrote:
>On Wed, 26 Jun 2013 09:04:28 -0700, John Larkin
><jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>
>>On Wed, 26 Jun 2013 08:54:46 -0700, Jim Thompson
>><To-Email-Use-Th...@On-My-Web-Site.com> wrote:
>>
>>>On Tue, 25 Jun 2013 19:06:53 -0700, John Larkin
>>><jla...@highlandtechnology.com> wrote:
>>>
>>>[snip]
>>>>Why do you and Jim keep cackling and squawking in a thread about PLLs?
>>>>
>>>>Do you have anything to say about PLLs?
>>>>
>>>
>>>Well. Who is it that has the patents on some of the very earliest
>>>commercial PLL parts?
>>>
>>>Hint: It's not you.
>>>
>>> ...Jim Thompson
>>
>>You are all about boasting. What's the use of having your name on an expired
>>patent that was assigned to someone else in the first place? What did they pay
>>you for those patents, $50 or something? That's a sucker's game; it doesn't show
>>how smart you are, it shows how stupid you are.
>
>You said, in another post, "It take some actual skill to design a
>PLL."
>
>So show us something technical about PLL's... something other than
>your standard drivel.
>
>You can't. You're a fraud.
>
> ...Jim Thompson
I posted the link to my V880 module that has the picosecond-stability bang-bang
>On Wed, 26 Jun 2013 09:04:28 -0700, John Larkin
><jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>
>>On Wed, 26 Jun 2013 08:54:46 -0700, Jim Thompson
>><To-Email-Use-Th...@On-My-Web-Site.com> wrote:
>>
>>>On Tue, 25 Jun 2013 19:06:53 -0700, John Larkin
>>><jla...@highlandtechnology.com> wrote:
>>>
>>>[snip]
>>>>Why do you and Jim keep cackling and squawking in a thread about PLLs?
>>>>
>>>>Do you have anything to say about PLLs?
>>>>
>>>
>>>Well. Who is it that has the patents on some of the very earliest
>>>commercial PLL parts?
>>>
>>>Hint: It's not you.
>>>
>>> ...Jim Thompson
>>
>>You are all about boasting. What's the use of having your name on an expired
>>patent that was assigned to someone else in the first place? What did they pay
>>you for those patents, $50 or something? That's a sucker's game; it doesn't show
>>how smart you are, it shows how stupid you are.
>
>You said, in another post, "It take some actual skill to design a
>PLL."
>
>So show us something technical about PLL's... something other than
>your standard drivel.
>
>You can't. You're a fraud.
>
> ...Jim Thompson
adaptive PLL. I think I've even posted the PLL schematic here before; I can do
it again if anyone's interested.
Bang-bang loops are interesting. There has been a little academic research, but
nothing that I've found to be useful; I have my own way of thinking about them.
I did my first one when I was still a student at Tulane, for a proposal to
Boeing. People thought it wouldn't work, but it locked first time. It was a TDM
analog audio link, and I played music through it to impress the boss.
The problem in the V880 is to keep the jitter *and* the time drift down to
single digits of picoseconds. Any linear phase detector is going to have serious
problems doing that over time and temperature. An all-differential bangbang
phase detector has, in theory, infinite gain and near zero TC.
LLNL liked it.
https://dl.dropboxusercontent.com/u/53724080/NIF3.jpg
Have you done any bangbang PLLs?
All your patents need an additional claim:
12. Thompson worked 70 hour weeks, for which we paid him almost nothing, to
invent this. He's gone now, and has no rights to his invention, and we keep
making millions selling these chips. He is however allowed to brag, to bored
dinner guests, about how smart he is.
John Fields
Jun 26, 2013, 12:38:13 PM6/26/13
to
>>In the present context, I'd say that PLL is an acronym for
>>Pussy Licked Larkin.
>>Pussy Licked Larkin.
>The topic is electronics design, you moron. Any idiot can type raunchy drivel,
>in bad prose or bad verse. It take some actual skill to design a PLL.
---
>in bad prose or bad verse. It take some actual skill to design a PLL.
You're preaching to the choir, numbnuts.
Besides, I thought you claimed that you never used words like 'Idiot'
or 'Moron' in that high-falutin' twaddle you allude to.
--
JF
Jim Thompson
Jun 26, 2013, 12:40:51 PM6/26/13
to
Charlie E.
Jun 26, 2013, 12:49:07 PM6/26/13
to
On Tue, 25 Jun 2013 19:06:53 -0700, John Larkin
<jla...@highlandtechnology.com> wrote:
>Don't be silly. If I shared shopping and cooking with anyone, any kind
>of roommate, we'd have to agree on what we cook and eat together. No
>point in two people cooking two separate meals.
Actually, it is fairly common for Pamela and I to have two separate
<jla...@highlandtechnology.com> wrote:
>Don't be silly. If I shared shopping and cooking with anyone, any kind
>of roommate, we'd have to agree on what we cook and eat together. No
>point in two people cooking two separate meals.
meals, and often I cook them both!
We have very different tastes in some things, esp. veggies. I love
green peas, but can't handle whole kernal corn. She loves corn on the
cob, bean sprouts, spinach, greens of many types.
Like this morning for breakfast, I boiled her an egg while I made
myself some ham and scrambled eggs with cheese. I had a slice of
toast, while she had some red grapes. We shared the ham and the
grapes. About a quarter of the time we will make two separate dishes
for a meal.
Charlie
Jim Thompson
Jun 26, 2013, 1:14:26 PM6/26/13
to
On Wed, 26 Jun 2013 09:37:34 -0700, John Larkin
Every one of my customers (many hundreds) like my work. Shall I post
my own pontificating display ?:-)
>
>Have you done any bangbang PLLs?
Yep. That was actually my first approach, back in the early '60's...
based on my observation of pushing my children on their swing set.
I've been doing PLL's so far back that no less a personage than
Gardner claimed that what I proposed couldn't work... until he saw me
demonstrate it at Hoffman Electronics (El Monte, CA).
I've also designed DLL's. Have you?
(BTW: I came up with the conceptual idea for today's common PFD. Ron
Treadway took my concept and reduced it to gates. I also am the one
who coined the phrase "charge pump".)
>
>
>All your patents need an additional claim:
>
>12. Thompson worked 70 hour weeks, for which we paid him almost nothing,
I've been paid rather well, all my life. And I've never actually
"worked". I've been playing all my life... I enjoy the challenge of
designing circuits. I'm still playing, though I don't need to
anymore.
>to
>invent this. He's gone now, and has no rights to his invention, and we keep
>making millions selling these chips. He is however allowed to brag, to bored
>dinner guests, about how smart he is.
What? You just described yourself? All you ever do here is shoot off
your mouth, tell us how wonderful you claim to be, and assault/insult
anyone who actually posts a working circuit.
Done any designs recently, or is everything done, as I suspect, by
your minions, but you claim the accolades?
You are, indeed, NOLA white trash.
my own pontificating display ?:-)
>
>Have you done any bangbang PLLs?
based on my observation of pushing my children on their swing set.
I've been doing PLL's so far back that no less a personage than
Gardner claimed that what I proposed couldn't work... until he saw me
demonstrate it at Hoffman Electronics (El Monte, CA).
I've also designed DLL's. Have you?
(BTW: I came up with the conceptual idea for today's common PFD. Ron
Treadway took my concept and reduced it to gates. I also am the one
who coined the phrase "charge pump".)
>
>
>All your patents need an additional claim:
>
>12. Thompson worked 70 hour weeks, for which we paid him almost nothing,
"worked". I've been playing all my life... I enjoy the challenge of
designing circuits. I'm still playing, though I don't need to
anymore.
>to
>invent this. He's gone now, and has no rights to his invention, and we keep
>making millions selling these chips. He is however allowed to brag, to bored
>dinner guests, about how smart he is.
your mouth, tell us how wonderful you claim to be, and assault/insult
anyone who actually posts a working circuit.
Done any designs recently, or is everything done, as I suspect, by
your minions, but you claim the accolades?
You are, indeed, NOLA white trash.
John Larkin
Jun 26, 2013, 2:01:24 PM6/26/13
to
On Wed, 26 Jun 2013 10:14:26 -0700, Jim Thompson
Senile Idiot! I never sell my labor or my IP. I embedd my IP in
products, and sell it thousands of times, or license the IP and get
paid for every use, forever, thousands of times. I have one patent
that I didn't really want, but I demanded that I have rights of use
before I signed the paperwork. Why create something, on a salary, and
watch someone else make big bucks off it?
All you ever do here is shoot off
>your mouth, tell us how wonderful you claim to be, and assault/insult
>anyone who actually posts a working circuit.
Senile ravings again.
>
>Done any designs recently, or is everything done, as I suspect, by
>your minions, but you claim the accolades?
Hell, look at my web site; there are zillions of products. I designed
most of the stuff there, defined the product and the architecture,
drew the schematics. I do collaborate with my guys, and let them do
stuff too, and I don't do the VHDL or embedded C stuff myself,
although I do a lot of the architectural stuff.
You keep saying that I can't design electronics, which is plain
stupid. I never said that you can't design analog ICs.
>
>You are, indeed, NOLA white trash.
You are, indeed, repetitious and boring. You just keep saying the same
dumb stuff, not even very original.
I couldn't design a linear IC, and you couldn't design the stuff that
I do.
https://dl.dropboxusercontent.com/u/53724080/PCBs/V220_board.jpg
https://dl.dropboxusercontent.com/u/53724080/PCBs/TEM2_Ctrl.jpg
https://dl.dropboxusercontent.com/u/53724080/PCBs/T680_PCB.JPG
https://dl.dropboxusercontent.com/u/53724080/PCBs/ESM_rev_B.jpg
I must have designed over a thousand circuit boards by now.
So you're just flailing, jumping into technical threads with stupid
personal clucking and plain-wrong insults, can't imagine why. Basic
meanness compounded by senility, I suppose.
--
John Larkin Highland Technology, Inc
Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Custom laser drivers and controllers
products, and sell it thousands of times, or license the IP and get
paid for every use, forever, thousands of times. I have one patent
that I didn't really want, but I demanded that I have rights of use
before I signed the paperwork. Why create something, on a salary, and
watch someone else make big bucks off it?
All you ever do here is shoot off
>your mouth, tell us how wonderful you claim to be, and assault/insult
>anyone who actually posts a working circuit.
>
>Done any designs recently, or is everything done, as I suspect, by
>your minions, but you claim the accolades?
most of the stuff there, defined the product and the architecture,
drew the schematics. I do collaborate with my guys, and let them do
stuff too, and I don't do the VHDL or embedded C stuff myself,
although I do a lot of the architectural stuff.
You keep saying that I can't design electronics, which is plain
stupid. I never said that you can't design analog ICs.
>
>You are, indeed, NOLA white trash.
dumb stuff, not even very original.
I couldn't design a linear IC, and you couldn't design the stuff that
I do.
https://dl.dropboxusercontent.com/u/53724080/PCBs/V220_board.jpg
https://dl.dropboxusercontent.com/u/53724080/PCBs/TEM2_Ctrl.jpg
https://dl.dropboxusercontent.com/u/53724080/PCBs/T680_PCB.JPG
https://dl.dropboxusercontent.com/u/53724080/PCBs/ESM_rev_B.jpg
I must have designed over a thousand circuit boards by now.
So you're just flailing, jumping into technical threads with stupid
personal clucking and plain-wrong insults, can't imagine why. Basic
meanness compounded by senility, I suppose.
--
John Larkin Highland Technology, Inc
jlarkin at highlandtechnology dot com
http://www.highlandtechnology.com
Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Photonics and fiberoptic TTL data links
John Larkin
Jun 26, 2013, 2:04:49 PM6/26/13
to
didn't want it, but the company I was working with did. It's assigned
to Imago Corporation, but I insisted on my rights to use it, which I
have. Search for Larkin+Gribb+Imago.
--
John Larkin Highland Technology, Inc
jlarkin at highlandtechnology dot com
http://www.highlandtechnology.com
Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Photonics and fiberoptic TTL data links
John Larkin
Jun 26, 2013, 2:10:18 PM6/26/13
to
On Wed, 26 Jun 2013 09:49:07 -0700, Charlie E. <edmo...@ieee.org>
wrote:
>On Tue, 25 Jun 2013 19:06:53 -0700, John Larkin
><jla...@highlandtechnology.com> wrote:
>
>
>>Don't be silly. If I shared shopping and cooking with anyone, any kind
>>of roommate, we'd have to agree on what we cook and eat together. No
>>point in two people cooking two separate meals.
>
>Actually, it is fairly common for Pamela and I to have two separate
>meals, and often I cook them both!
>
>We have very different tastes in some things, esp. veggies. I love
>green peas, but can't handle whole kernal corn. She loves corn on the
>cob, bean sprouts, spinach, greens of many types.
We're a bit more compatible than that. She just doesn't like a lot of
red meat.
>
>Like this morning for breakfast, I boiled her an egg while I made
>myself some ham and scrambled eggs with cheese. I had a slice of
>toast, while she had some red grapes. We shared the ham and the
>grapes. About a quarter of the time we will make two separate dishes
>for a meal.
>
>Charlie
I do most of the cooking, 100% of the breakfasts, but I prefer to just
cook one meal at home. I can always have a big bloody burger or a
carnitas taco for lunch.
So much food, so little time.
wrote:
>On Tue, 25 Jun 2013 19:06:53 -0700, John Larkin
><jla...@highlandtechnology.com> wrote:
>
>
>>Don't be silly. If I shared shopping and cooking with anyone, any kind
>>of roommate, we'd have to agree on what we cook and eat together. No
>>point in two people cooking two separate meals.
>
>Actually, it is fairly common for Pamela and I to have two separate
>meals, and often I cook them both!
>
>We have very different tastes in some things, esp. veggies. I love
>green peas, but can't handle whole kernal corn. She loves corn on the
>cob, bean sprouts, spinach, greens of many types.
red meat.
>
>Like this morning for breakfast, I boiled her an egg while I made
>myself some ham and scrambled eggs with cheese. I had a slice of
>toast, while she had some red grapes. We shared the ham and the
>grapes. About a quarter of the time we will make two separate dishes
>for a meal.
>
>Charlie
cook one meal at home. I can always have a big bloody burger or a
carnitas taco for lunch.
So much food, so little time.
Joerg
Jun 26, 2013, 2:13:06 PM6/26/13
to
John Larkin wrote:
> On Tue, 25 Jun 2013 17:29:14 -0400, "Michael A. Terrell"
> <mike.t...@earthlink.net> wrote:
> On Tue, 25 Jun 2013 17:29:14 -0400, "Michael A. Terrell"
>
>> Tim Wescott wrote:
>>> On Tue, 25 Jun 2013 13:06:32 -0700, John Larkin wrote:
>>>
>>>> I have a good customer who wants us to build a weird glue-logic fanout
>>>> box to solve some system problems. One thing they want to do is give us
>>>> a 40 KHz clock and want us to output 100 KHz.
>>>>
>>>> A 4046 or HC4046 could multiply by 5 to 200K, then we could divide by 2
>>>> to 100K. That would use the drecky 4046 VCO and the drekkier phase
>>>> detector with tons of phase noise. Is there a better 4046 chip around,
>>>> or some equivalently simple pll/vco chip?
>>>>
>>>> This is a sort of charity job, no reason to do it except that it's a
>>>> good customer. I want to keep it simple, no uP code, no FPGAs to
>>>> program, all old fashioned hardware.
>>>
>>>> I have a good customer who wants us to build a weird glue-logic fanout
>>>> box to solve some system problems. One thing they want to do is give us
>>>> a 40 KHz clock and want us to output 100 KHz.
>>>>
>>>> A 4046 or HC4046 could multiply by 5 to 200K, then we could divide by 2
>>>> to 100K. That would use the drecky 4046 VCO and the drekkier phase
>>>> detector with tons of phase noise. Is there a better 4046 chip around,
>>>> or some equivalently simple pll/vco chip?
>>>>
>>>> This is a sort of charity job, no reason to do it except that it's a
>>>> good customer. I want to keep it simple, no uP code, no FPGAs to
>>>> program, all old fashioned hardware.
>>> I think there's a 7046 from someone, but (a) I don't know if it's
>>> 74HC7046, 74AC7046, 74YMMV7046, or what, and (b) I don't know if it's
>>> still available.
>>
>> http://www.nxp.com/documents/data_sheet/74HCT9046A.pdf
>
>>> 74HC7046, 74AC7046, 74YMMV7046, or what, and (b) I don't know if it's
>>> still available.
>>
>> http://www.nxp.com/documents/data_sheet/74HCT9046A.pdf
>
> That looks a lot better than a 4046, and runs to 15 MHz typ. Thanks
> for the link.
>
I have tried the 9046 once. Did not find it to be much better and
> for the link.
>
abandoned it, rolled my own PLL instead.
--
Regards, Joerg
http://www.analogconsultants.com/
John Fields
Jun 26, 2013, 2:47:02 PM6/26/13
to
On Wed, 26 Jun 2013 11:04:49 -0700, John Larkin
<jla...@highlandtechnology.com> wrote:
>On Wed, 26 Jun 2013 11:23:34 -0500, John Fields
><jfi...@austininstruments.com> wrote:
>
>>On Wed, 26 Jun 2013 09:04:28 -0700, John Larkin
>><jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>>
>>
>>>You are all about boasting. What's the use of having your name on an expired
>>>patent that was assigned to someone else in the first place? What did they pay
>>>you for those patents, $50 or something? That's a sucker's game; it doesn't show
>>>how smart you are, it shows how stupid you are.
>>
>>---
>>John, do you hold any patents?
>
>Only one, about 2D delay-line anodes for imaging charged particles. I
>didn't want it, but the company I was working with did.
---
<jla...@highlandtechnology.com> wrote:
>On Wed, 26 Jun 2013 11:23:34 -0500, John Fields
><jfi...@austininstruments.com> wrote:
>
>>On Wed, 26 Jun 2013 09:04:28 -0700, John Larkin
>><jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>>
>>
>>>You are all about boasting. What's the use of having your name on an expired
>>>patent that was assigned to someone else in the first place? What did they pay
>>>you for those patents, $50 or something? That's a sucker's game; it doesn't show
>>>how smart you are, it shows how stupid you are.
>>
>>---
>>John, do you hold any patents?
>
>Only one, about 2D delay-line anodes for imaging charged particles. I
>didn't want it, but the company I was working with did.
If you were salaried you were no peer and you weren't working _with_
them, you were working _for_ them.
A subtle distinction perhaps, but one which speaks volumes about the
chip on your shoulder and your abhorrence at being taken advantage of.
Even here, where you refuse to concede the slightest point even if
you're dead wrong.
Or, perhaps, especially here - where you seem to think you're
surrounded by incompetents - and have the most face to lose by being
called to task for an error committed, by the hoi polloi.
---
>It's assigned
>to Imago Corporation, but I insisted on my rights to use it, which I
>have. Search for Larkin+Gribb+Imago.
So, other than the one patent, you hold nothing which legally protects
your IP from pirates?
Is that really a good idea?
--
JF
John Fields
Jun 26, 2013, 2:53:53 PM6/26/13
to
On Wed, 26 Jun 2013 11:10:18 -0700, John Larkin
Lucky you?
--
JF
<jla...@highlandtechnology.com> wrote:
>On Wed, 26 Jun 2013 09:49:07 -0700, Charlie E. <edmo...@ieee.org>
>wrote:
>
>>On Tue, 25 Jun 2013 19:06:53 -0700, John Larkin
>><jla...@highlandtechnology.com> wrote:
>>
>>
>>>Don't be silly. If I shared shopping and cooking with anyone, any kind
>>>of roommate, we'd have to agree on what we cook and eat together. No
>>>point in two people cooking two separate meals.
>>
>>Actually, it is fairly common for Pamela and I to have two separate
>>meals, and often I cook them both!
>>
>>We have very different tastes in some things, esp. veggies. I love
>>green peas, but can't handle whole kernal corn. She loves corn on the
>>cob, bean sprouts, spinach, greens of many types.
>
>We're a bit more compatible than that. She just doesn't like a lot of
>red meat.
---
>On Wed, 26 Jun 2013 09:49:07 -0700, Charlie E. <edmo...@ieee.org>
>wrote:
>
>>On Tue, 25 Jun 2013 19:06:53 -0700, John Larkin
>><jla...@highlandtechnology.com> wrote:
>>
>>
>>>Don't be silly. If I shared shopping and cooking with anyone, any kind
>>>of roommate, we'd have to agree on what we cook and eat together. No
>>>point in two people cooking two separate meals.
>>
>>Actually, it is fairly common for Pamela and I to have two separate
>>meals, and often I cook them both!
>>
>>We have very different tastes in some things, esp. veggies. I love
>>green peas, but can't handle whole kernal corn. She loves corn on the
>>cob, bean sprouts, spinach, greens of many types.
>
>We're a bit more compatible than that. She just doesn't like a lot of
>red meat.
Lucky you?
--
JF
Michael A. Terrell
Jun 26, 2013, 3:03:37 PM6/26/13
to
Tim Wescott wrote:
>
> On Tue, 25 Jun 2013 17:29:14 -0400, Michael A. Terrell wrote:
>
> > Tim Wescott wrote:
> >>
> >> On Tue, 25 Jun 2013 13:06:32 -0700, John Larkin wrote:
> >>
> >> > I have a good customer who wants us to build a weird glue-logic
> >> > fanout box to solve some system problems. One thing they want to do
> >> > is give us a 40 KHz clock and want us to output 100 KHz.
> >> >
> >> > A 4046 or HC4046 could multiply by 5 to 200K, then we could divide by
> >> > 2 to 100K. That would use the drecky 4046 VCO and the drekkier phase
> >> > detector with tons of phase noise. Is there a better 4046 chip
> >> > around, or some equivalently simple pll/vco chip?
> >> >
> >> > This is a sort of charity job, no reason to do it except that it's a
> >> > good customer. I want to keep it simple, no uP code, no FPGAs to
> >> > program, all old fashioned hardware.
> >>
> >> I think there's a 7046 from someone, but (a) I don't know if it's
> >> 74HC7046, 74AC7046, 74YMMV7046, or what, and (b) I don't know if it's
> >> still available.
> >
> >
> > http://www.nxp.com/documents/data_sheet/74HCT9046A.pdf
>
> On Tue, 25 Jun 2013 17:29:14 -0400, Michael A. Terrell wrote:
>
> > Tim Wescott wrote:
> >>
> >> On Tue, 25 Jun 2013 13:06:32 -0700, John Larkin wrote:
> >>
> >> > I have a good customer who wants us to build a weird glue-logic
> >> > fanout box to solve some system problems. One thing they want to do
> >> > is give us a 40 KHz clock and want us to output 100 KHz.
> >> >
> >> > A 4046 or HC4046 could multiply by 5 to 200K, then we could divide by
> >> > 2 to 100K. That would use the drecky 4046 VCO and the drekkier phase
> >> > detector with tons of phase noise. Is there a better 4046 chip
> >> > around, or some equivalently simple pll/vco chip?
> >> >
> >> > This is a sort of charity job, no reason to do it except that it's a
> >> > good customer. I want to keep it simple, no uP code, no FPGAs to
> >> > program, all old fashioned hardware.
> >>
> >> I think there's a 7046 from someone, but (a) I don't know if it's
> >> 74HC7046, 74AC7046, 74YMMV7046, or what, and (b) I don't know if it's
> >> still available.
> >
> >
> > http://www.nxp.com/documents/data_sheet/74HCT9046A.pdf
>
> Seven, nine, eh, what's the difference? It's an odd number, and bigger
> than "many".
>
> (Thanks for taking my imperfect recollection and turning it into
> than "many".
>
> something accurate).
Someone has to keep you on your toes! ;-)
Phil Hobbs
Jun 26, 2013, 3:07:44 PM6/26/13
to
has a crappy oscillator, and the phase detector is no better than a 4046
with a 1 meg resistor to ground from the PD output.
All you have to do to clean up PD2 is pull the servo point ~10 ns away
from the deadband. Compared to using a boutique part, that's a win.
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics
160 North State Road #203
Briarcliff Manor NY 10510
hobbs at electrooptical dot net
http://electrooptical.net
John Larkin
Jun 26, 2013, 3:14:41 PM6/26/13
to
On Wed, 26 Jun 2013 13:47:02 -0500, John Fields
for the atom probe was all for free. I even paid my own air fares.
Madison Wisconsin is kind of neat.
>
>A subtle distinction perhaps, but one which speaks volumes about the
>chip on your shoulder and your abhorrence at being taken advantage of.
You like being taken advantage of? Enjoy!
>
>Even here, where you refuse to concede the slightest point even if
>you're dead wrong.
>
>Or, perhaps, especially here - where you seem to think you're
>surrounded by incompetents - and have the most face to lose by being
>called to task for an error committed, by the hoi polloi.
>---
>
>>It's assigned
>>to Imago Corporation, but I insisted on my rights to use it, which I
>>have. Search for Larkin+Gribb+Imago.
>
>---
>So, other than the one patent, you hold nothing which legally protects
>your IP from pirates?
>
>Is that really a good idea?
>
>
Patents are just an expensive, time-consuming license to litigate,
even if you can somehow find out that someone has copied a design.
It's more time-efficient to just keep designing better stuff and keep
ahead of the competition. Besides, if any of my customers discovered
that someone had copied our designs, they'd blackball them. It has
happened.
A lot of the stuff we do would be very hard to reverse engineer
anyhow, to fight for half of a niche market. And if it happened once
in a while, it's not a disaster. Like I said, just keep ahead of them.
I have a couple of new ideas that I may just publish in the public
domain, so somebody else can't patent them. This new "first to file"
thing is outrageous. It's a consequence of the US Patent office being
a profit center, not a public service.
<jfi...@austininstruments.com> wrote:
>On Wed, 26 Jun 2013 11:04:49 -0700, John Larkin
><jla...@highlandtechnology.com> wrote:
>
>>On Wed, 26 Jun 2013 11:23:34 -0500, John Fields
>><jfi...@austininstruments.com> wrote:
>>
>>>On Wed, 26 Jun 2013 09:04:28 -0700, John Larkin
>>><jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>>>
>>>
>>>>You are all about boasting. What's the use of having your name on an expired
>>>>patent that was assigned to someone else in the first place? What did they pay
>>>>you for those patents, $50 or something? That's a sucker's game; it doesn't show
>>>>how smart you are, it shows how stupid you are.
>>>
>>>---
>>>John, do you hold any patents?
>>
>>Only one, about 2D delay-line anodes for imaging charged particles. I
>>didn't want it, but the company I was working with did.
>
>---
>If you were salaried you were no peer and you weren't working _with_
>them, you were working _for_ them.
I was not their employee, I was not salaried, and the brainstorming
>On Wed, 26 Jun 2013 11:04:49 -0700, John Larkin
><jla...@highlandtechnology.com> wrote:
>
>>On Wed, 26 Jun 2013 11:23:34 -0500, John Fields
>><jfi...@austininstruments.com> wrote:
>>
>>>On Wed, 26 Jun 2013 09:04:28 -0700, John Larkin
>>><jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>>>
>>>
>>>>You are all about boasting. What's the use of having your name on an expired
>>>>patent that was assigned to someone else in the first place? What did they pay
>>>>you for those patents, $50 or something? That's a sucker's game; it doesn't show
>>>>how smart you are, it shows how stupid you are.
>>>
>>>---
>>>John, do you hold any patents?
>>
>>Only one, about 2D delay-line anodes for imaging charged particles. I
>>didn't want it, but the company I was working with did.
>
>---
>If you were salaried you were no peer and you weren't working _with_
>them, you were working _for_ them.
for the atom probe was all for free. I even paid my own air fares.
Madison Wisconsin is kind of neat.
>
>A subtle distinction perhaps, but one which speaks volumes about the
>chip on your shoulder and your abhorrence at being taken advantage of.
>
>Even here, where you refuse to concede the slightest point even if
>you're dead wrong.
>
>Or, perhaps, especially here - where you seem to think you're
>surrounded by incompetents - and have the most face to lose by being
>called to task for an error committed, by the hoi polloi.
>---
>
>>It's assigned
>>to Imago Corporation, but I insisted on my rights to use it, which I
>>have. Search for Larkin+Gribb+Imago.
>
>---
>So, other than the one patent, you hold nothing which legally protects
>your IP from pirates?
>
>Is that really a good idea?
>
>
even if you can somehow find out that someone has copied a design.
It's more time-efficient to just keep designing better stuff and keep
ahead of the competition. Besides, if any of my customers discovered
that someone had copied our designs, they'd blackball them. It has
happened.
A lot of the stuff we do would be very hard to reverse engineer
anyhow, to fight for half of a niche market. And if it happened once
in a while, it's not a disaster. Like I said, just keep ahead of them.
I have a couple of new ideas that I may just publish in the public
domain, so somebody else can't patent them. This new "first to file"
thing is outrageous. It's a consequence of the US Patent office being
a profit center, not a public service.
Jim Thompson
Jun 26, 2013, 3:30:37 PM6/26/13
to
On Wed, 26 Jun 2013 12:14:41 -0700, John Larkin
<jla...@highlandtechnology.com> wrote:
[snip]
notices.
There's been a recent significant change that I posted here, multiple
times, but no one has noticed, which proves my point.
>This new "first to file"
>thing is outrageous. It's a consequence of the US Patent office being
>a profit center, not a public service.
At least we agree on one thing ;-)
<jla...@highlandtechnology.com> wrote:
[snip]
>
>I have a couple of new ideas that I may just publish in the public
>domain, so somebody else can't patent them.
I do it all the time, I just don't announce it, so virtually no one
>I have a couple of new ideas that I may just publish in the public
>domain, so somebody else can't patent them.
notices.
There's been a recent significant change that I posted here, multiple
times, but no one has noticed, which proves my point.
>This new "first to file"
>thing is outrageous. It's a consequence of the US Patent office being
>a profit center, not a public service.
John Larkin
Jun 26, 2013, 4:12:06 PM6/26/13
to
On Wed, 26 Jun 2013 12:30:37 -0700, Jim Thompson
<To-Email-Use-Th...@On-My-Web-Site.com> wrote:
>On Wed, 26 Jun 2013 12:14:41 -0700, John Larkin
><jla...@highlandtechnology.com> wrote:
>
>[snip]
>>
>>I have a couple of new ideas that I may just publish in the public
>>domain, so somebody else can't patent them.
>
>I do it all the time, I just don't announce it, so virtually no one
>notices.
>
>There's been a recent significant change that I posted here, multiple
>times, but no one has noticed, which proves my point.
I don't think that posting to SED is adequate public disclosure. The
<To-Email-Use-Th...@On-My-Web-Site.com> wrote:
>On Wed, 26 Jun 2013 12:14:41 -0700, John Larkin
><jla...@highlandtechnology.com> wrote:
>
>[snip]
>>
>>I have a couple of new ideas that I may just publish in the public
>>domain, so somebody else can't patent them.
>
>I do it all the time, I just don't announce it, so virtually no one
>notices.
>
>There's been a recent significant change that I posted here, multiple
>times, but no one has noticed, which proves my point.
legal requirement is that it be published in "a printed publication."
A couple of outfits will do that, for around $100.
John Larkin
Jun 26, 2013, 4:12:55 PM6/26/13
to
Jim Thompson
Jun 26, 2013, 8:32:09 PM6/26/13
to
On Wed, 26 Jun 2013 13:12:06 -0700, John Larkin
<jla...@highlandtechnology.com> wrote:
>On Wed, 26 Jun 2013 12:30:37 -0700, Jim Thompson
><To-Email-Use-Th...@On-My-Web-Site.com> wrote:
>
>>On Wed, 26 Jun 2013 12:14:41 -0700, John Larkin
>><jla...@highlandtechnology.com> wrote:
>>
>>[snip]
>>>
>>>I have a couple of new ideas that I may just publish in the public
>>>domain, so somebody else can't patent them.
>>
>>I do it all the time, I just don't announce it, so virtually no one
>>notices.
>>
>>There's been a recent significant change that I posted here, multiple
>>times, but no one has noticed, which proves my point.
>
>I don't think that posting to SED is adequate public disclosure. The
>legal requirement is that it be published in "a printed publication."
>A couple of outfits will do that, for around $100.
I think it's any public "forum".
>On Wed, 26 Jun 2013 12:30:37 -0700, Jim Thompson
><To-Email-Use-Th...@On-My-Web-Site.com> wrote:
>
>>On Wed, 26 Jun 2013 12:14:41 -0700, John Larkin
>><jla...@highlandtechnology.com> wrote:
>>
>>[snip]
>>>
>>>I have a couple of new ideas that I may just publish in the public
>>>domain, so somebody else can't patent them.
>>
>>I do it all the time, I just don't announce it, so virtually no one
>>notices.
>>
>>There's been a recent significant change that I posted here, multiple
>>times, but no one has noticed, which proves my point.
>
>I don't think that posting to SED is adequate public disclosure. The
>legal requirement is that it be published in "a printed publication."
>A couple of outfits will do that, for around $100.
John Larkin
Jun 26, 2013, 9:16:43 PM6/26/13
to
On Wed, 26 Jun 2013 17:32:09 -0700, Jim Thompson
http://pubs.acs.org/subscribe/archive/ci/31/i04/html/04cogen.html
--
John Larkin Highland Technology Inc
www.highlandtechnology.com jlarkin at highlandtechnology dot com
Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Custom timing and laser controllers
<To-Email-Use-Th...@On-My-Web-Site.com> wrote:
>On Wed, 26 Jun 2013 13:12:06 -0700, John Larkin
><jla...@highlandtechnology.com> wrote:
>
>>On Wed, 26 Jun 2013 12:30:37 -0700, Jim Thompson
>><To-Email-Use-Th...@On-My-Web-Site.com> wrote:
>>
>>>On Wed, 26 Jun 2013 12:14:41 -0700, John Larkin
>>><jla...@highlandtechnology.com> wrote:
>>>
>>>[snip]
>>>>
>>>>I have a couple of new ideas that I may just publish in the public
>>>>domain, so somebody else can't patent them.
>>>
>>>I do it all the time, I just don't announce it, so virtually no one
>>>notices.
>>>
>>>There's been a recent significant change that I posted here, multiple
>>>times, but no one has noticed, which proves my point.
>>
>>I don't think that posting to SED is adequate public disclosure. The
>>legal requirement is that it be published in "a printed publication."
>>A couple of outfits will do that, for around $100.
>
>I think it's any public "forum".
>
> ...Jim Thompson
Then why would these people charge $100?
>On Wed, 26 Jun 2013 13:12:06 -0700, John Larkin
><jla...@highlandtechnology.com> wrote:
>
>>On Wed, 26 Jun 2013 12:30:37 -0700, Jim Thompson
>><To-Email-Use-Th...@On-My-Web-Site.com> wrote:
>>
>>>On Wed, 26 Jun 2013 12:14:41 -0700, John Larkin
>>><jla...@highlandtechnology.com> wrote:
>>>
>>>[snip]
>>>>
>>>>I have a couple of new ideas that I may just publish in the public
>>>>domain, so somebody else can't patent them.
>>>
>>>I do it all the time, I just don't announce it, so virtually no one
>>>notices.
>>>
>>>There's been a recent significant change that I posted here, multiple
>>>times, but no one has noticed, which proves my point.
>>
>>I don't think that posting to SED is adequate public disclosure. The
>>legal requirement is that it be published in "a printed publication."
>>A couple of outfits will do that, for around $100.
>
>I think it's any public "forum".
>
> ...Jim Thompson
http://pubs.acs.org/subscribe/archive/ci/31/i04/html/04cogen.html
--
John Larkin Highland Technology Inc
Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Photonics and fiberoptic TTL data links
Jim Thompson
Jun 26, 2013, 10:18:16 PM6/26/13
to
On Wed, 26 Jun 2013 18:16:43 -0700, John Larkin
<jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>On Wed, 26 Jun 2013 17:32:09 -0700, Jim Thompson
><To-Email-Use-Th...@On-My-Web-Site.com> wrote:
>
>>On Wed, 26 Jun 2013 13:12:06 -0700, John Larkin
>><jla...@highlandtechnology.com> wrote:
>>
>>>On Wed, 26 Jun 2013 12:30:37 -0700, Jim Thompson
>>><To-Email-Use-Th...@On-My-Web-Site.com> wrote:
>>>
>>>>On Wed, 26 Jun 2013 12:14:41 -0700, John Larkin
>>>><jla...@highlandtechnology.com> wrote:
>>>>
>>>>[snip]
>>>>>
>>>>>I have a couple of new ideas that I may just publish in the public
>>>>>domain, so somebody else can't patent them.
>>>>
>>>>I do it all the time, I just don't announce it, so virtually no one
>>>>notices.
>>>>
>>>>There's been a recent significant change that I posted here, multiple
>>>>times, but no one has noticed, which proves my point.
>>>
>>>I don't think that posting to SED is adequate public disclosure. The
>>>legal requirement is that it be published in "a printed publication."
>>>A couple of outfits will do that, for around $100.
>>
>>I think it's any public "forum".
>>
>> ...Jim Thompson
>
>
>Then why would these people charge $100?
>
>http://pubs.acs.org/subscribe/archive/ci/31/i04/html/04cogen.html
The P.T.Barnum effect ?:-)
<jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>On Wed, 26 Jun 2013 17:32:09 -0700, Jim Thompson
><To-Email-Use-Th...@On-My-Web-Site.com> wrote:
>
>>On Wed, 26 Jun 2013 13:12:06 -0700, John Larkin
>><jla...@highlandtechnology.com> wrote:
>>
>>>On Wed, 26 Jun 2013 12:30:37 -0700, Jim Thompson
>>><To-Email-Use-Th...@On-My-Web-Site.com> wrote:
>>>
>>>>On Wed, 26 Jun 2013 12:14:41 -0700, John Larkin
>>>><jla...@highlandtechnology.com> wrote:
>>>>
>>>>[snip]
>>>>>
>>>>>I have a couple of new ideas that I may just publish in the public
>>>>>domain, so somebody else can't patent them.
>>>>
>>>>I do it all the time, I just don't announce it, so virtually no one
>>>>notices.
>>>>
>>>>There's been a recent significant change that I posted here, multiple
>>>>times, but no one has noticed, which proves my point.
>>>
>>>I don't think that posting to SED is adequate public disclosure. The
>>>legal requirement is that it be published in "a printed publication."
>>>A couple of outfits will do that, for around $100.
>>
>>I think it's any public "forum".
>>
>> ...Jim Thompson
>
>
>Then why would these people charge $100?
>
>http://pubs.acs.org/subscribe/archive/ci/31/i04/html/04cogen.html
Bill Sloman
Jun 26, 2013, 10:30:27 PM6/26/13
to
On Thursday, 27 June 2013 03:14:26 UTC+10, Jim Thompson wrote:
> On Wed, 26 Jun 2013 09:37:34 -0700, John Larkin
> <jjla...@highNOTlandTHIStechnologyPART.com> wrote:
> >On Wed, 26 Jun 2013 09:13:00 -0700, Jim Thompson
> ><To-Email-Use-Th...@On-My-Web-Site.com> wrote:
> >>On Wed, 26 Jun 2013 09:04:28 -0700, John Larkin
> >><jjla...@highNOTlandTHIStechnologyPART.com> wrote:
> >>>On Wed, 26 Jun 2013 08:54:46 -0700, Jim Thompson
> >>><To-Email-Use-Th...@On-My-Web-Site.com> wrote:
> >>>>On Tue, 25 Jun 2013 19:06:53 -0700, John Larkin
> >>>><jla...@highlandtechnology.com> wrote:
[snip]
> On Wed, 26 Jun 2013 09:37:34 -0700, John Larkin
> <jjla...@highNOTlandTHIStechnologyPART.com> wrote:
> >On Wed, 26 Jun 2013 09:13:00 -0700, Jim Thompson
> ><To-Email-Use-Th...@On-My-Web-Site.com> wrote:
> >>On Wed, 26 Jun 2013 09:04:28 -0700, John Larkin
> >><jjla...@highNOTlandTHIStechnologyPART.com> wrote:
> >>>On Wed, 26 Jun 2013 08:54:46 -0700, Jim Thompson
> >>><To-Email-Use-Th...@On-My-Web-Site.com> wrote:
> >>>>On Tue, 25 Jun 2013 19:06:53 -0700, John Larkin
> >>>><jla...@highlandtechnology.com> wrote:
[snip]
> I've been doing PLL's so far back that no less a personage than
> Gardner claimed that what I proposed couldn't work... until he saw me
> demonstrate it at Hoffman Electronics (El Monte, CA).
That may explain why Gardner's "Phaselock Techniques" doesn't mention the MC4024 and MC4044, which were around when the book was published.
> Gardner claimed that what I proposed couldn't work... until he saw me
> demonstrate it at Hoffman Electronics (El Monte, CA).
I've mentioned before that I found that to be an unexpected omission. Granting Jim's winning personality and irresistible charm, it has to be the only possible explanation.
<snip>
--
Bill Sloman, Sydney
John K
Jun 28, 2013, 11:36:45 PM6/28/13
to
John Larkin <jla...@highlandtechnology.com> wrote:
> On Tue, 25 Jun 2013 14:23:53 -0700, Jim Thompson
> <To-Email-Use-Th...@On-My-Web-Site.com> wrote:
>>>can supply? If not, why complain?
>>
>>"Drecky" is a Larkin comment only because he thinks I designed it. I
>>didn't. It's some poor copy, done by... I have no clue. The VCO, in
>>particular, is a real kludge.
>
> You just made no sense at all. You agree with me that the 4046 is a
> pretty bad part. I never said you designed it, and never suspected
> that you did. It was an old RCA design originally.
John, do you have any more information on the original RCA 4046 design?
Did they also do the 4044? Do you recall any dates when they were on the
market?
Any pointers to manuals or app notes?
Any information you can give would be much appreciated.
Thanks,
JK
> On Tue, 25 Jun 2013 14:23:53 -0700, Jim Thompson
> <To-Email-Use-Th...@On-My-Web-Site.com> wrote:
>
>>On Tue, 25 Jun 2013 15:44:59 -0500, Tim Wescott
>><t...@seemywebsite.really> wrote:
>>
>>>On Tue, 25 Jun 2013 13:06:32 -0700, John Larkin wrote:
>>>
>>>> I have a good customer who wants us to build a weird glue-logic
>>>> fanout box to solve some system problems. One thing they want to do
>>>> is give us a 40 KHz clock and want us to output 100 KHz.
>>>>
>>>> A 4046 or HC4046 could multiply by 5 to 200K, then we could divide
>>>> by 2 to 100K. That would use the drecky 4046 VCO and the drekkier
>>>> phase detector with tons of phase noise. Is there a better 4046
>>>> chip around, or some equivalently simple pll/vco chip?
>>>>
>>>> This is a sort of charity job, no reason to do it except that it's
>>>> a good customer. I want to keep it simple, no uP code, no FPGAs to
>>>> program, all old fashioned hardware.
>>>
>>>I think there's a 7046 from someone, but (a) I don't know if it's
>>>74HC7046, 74AC7046, 74YMMV7046, or what, and (b) I don't know if it's
>>>still available.
>>>
>>>Do they really need 100kHz that's better than what the "drecky" 4046
>>On Tue, 25 Jun 2013 15:44:59 -0500, Tim Wescott
>><t...@seemywebsite.really> wrote:
>>
>>>On Tue, 25 Jun 2013 13:06:32 -0700, John Larkin wrote:
>>>
>>>> I have a good customer who wants us to build a weird glue-logic
>>>> fanout box to solve some system problems. One thing they want to do
>>>> is give us a 40 KHz clock and want us to output 100 KHz.
>>>>
>>>> A 4046 or HC4046 could multiply by 5 to 200K, then we could divide
>>>> by 2 to 100K. That would use the drecky 4046 VCO and the drekkier
>>>> phase detector with tons of phase noise. Is there a better 4046
>>>> chip around, or some equivalently simple pll/vco chip?
>>>>
>>>> This is a sort of charity job, no reason to do it except that it's
>>>> a good customer. I want to keep it simple, no uP code, no FPGAs to
>>>> program, all old fashioned hardware.
>>>
>>>I think there's a 7046 from someone, but (a) I don't know if it's
>>>74HC7046, 74AC7046, 74YMMV7046, or what, and (b) I don't know if it's
>>>still available.
>>>
>>>can supply? If not, why complain?
>>
>>"Drecky" is a Larkin comment only because he thinks I designed it. I
>>didn't. It's some poor copy, done by... I have no clue. The VCO, in
>>particular, is a real kludge.
>
> You just made no sense at all. You agree with me that the 4046 is a
> pretty bad part. I never said you designed it, and never suspected
> that you did. It was an old RCA design originally.
John, do you have any more information on the original RCA 4046 design?
Did they also do the 4044? Do you recall any dates when they were on the
market?
Any pointers to manuals or app notes?
Any information you can give would be much appreciated.
Thanks,
JK
John Larkin
Jun 29, 2013, 12:45:22 AM6/29/13
to
latch."
There must be databooks online somewhere. If not, I can scan the CD4046 part of
the book, which is 6 pages and a lot of data, including an image of the mask.
The CD4046A is listed in the 1975 RCA Solid-State Devices Manual too.
Jim Thompson
Jun 29, 2013, 12:57:16 AM6/29/13
to
On Sat, 29 Jun 2013 03:36:45 GMT, John K <sp...@me.not> wrote:
by Ron Treadway.
The MC4024 was my first VCM.
See my website for links.
Bill Sloman
Jun 29, 2013, 1:59:34 AM6/29/13
to
On Saturday, 29 June 2013 13:36:45 UTC+10, John K wrote:
> John Larkin <jla...@highlandtechnology.com> wrote:
> > On Tue, 25 Jun 2013 14:23:53 -0700, Jim Thompson
> > <To-Email-Use-Th...@On-My-Web-Site.com> wrote:
> >>On Tue, 25 Jun 2013 15:44:59 -0500, Tim Wescott
> >><t...@seemywebsite.really> wrote:
> >>>On Tue, 25 Jun 2013 13:06:32 -0700, John Larkin wrote:
> >>>
> >>>> I have a good customer who wants us to build a weird glue-logic
> >>>> fanout box to solve some system problems. One thing they want to do
> >>>> is give us a 40 KHz clock and want us to output 100 kHz.
> John Larkin <jla...@highlandtechnology.com> wrote:
> > On Tue, 25 Jun 2013 14:23:53 -0700, Jim Thompson
> > <To-Email-Use-Th...@On-My-Web-Site.com> wrote:
> >>On Tue, 25 Jun 2013 15:44:59 -0500, Tim Wescott
> >><t...@seemywebsite.really> wrote:
> >>>On Tue, 25 Jun 2013 13:06:32 -0700, John Larkin wrote:
> >>>
> >>>> I have a good customer who wants us to build a weird glue-logic
> >>>> fanout box to solve some system problems. One thing they want to do
> >>>>
> >>>> A 4046 or HC4046 could multiply by 5 to 200K, then we could divide
> >>>> by 2 to 100K. That would use the drecky 4046 VCO and the drekkier
> >>>> phase detector with tons of phase noise. Is there a better 4046
> >>>> chip around, or some equivalently simple pll/vco chip?
> >>>>
> >>>> This is a sort of charity job, no reason to do it except that it's
> >>>> a good customer. I want to keep it simple, no uP code, no FPGAs to
> >>>> program, all old fashioned hardware.
> >>>
> >>>I think there's a 7046 from someone, but (a) I don't know if it's
> >>>74HC7046, 74AC7046, 74YMMV7046, or what, and (b) I don't know if it's
> >>>still available.
> >>>
> >>>Do they really need 100kHz that's better than what the "drecky" 4046
> >>>can supply? If not, why complain?
> >>
> >>"Drecky" is a Larkin comment only because he thinks I designed it. I
> >>didn't. It's some poor copy, done by... I have no clue. The VCO, in
> >>particular, is a real kludge.
> >
> > You just made no sense at all. You agree with me that the 4046 is a
> > pretty bad part. I never said you designed it, and never suspected
> > that you did. It was an old RCA design originally.
>
> John, do you have any more information on the original RCA 4046 design?
>
> Did they also do the 4044? Do you recall any dates when they were on the
> market?
The RCA 4046 seems to have been half-inspired by Motorola' MC4024 oscillator, designed by our very own Jim Thompson, who also claims to have had a hand in the other half of the inspiration, the Motorola MC4044 phase detector chip.
> >>>> A 4046 or HC4046 could multiply by 5 to 200K, then we could divide
> >>>> by 2 to 100K. That would use the drecky 4046 VCO and the drekkier
> >>>> phase detector with tons of phase noise. Is there a better 4046
> >>>> chip around, or some equivalently simple pll/vco chip?
> >>>>
> >>>> This is a sort of charity job, no reason to do it except that it's
> >>>> a good customer. I want to keep it simple, no uP code, no FPGAs to
> >>>> program, all old fashioned hardware.
> >>>
> >>>I think there's a 7046 from someone, but (a) I don't know if it's
> >>>74HC7046, 74AC7046, 74YMMV7046, or what, and (b) I don't know if it's
> >>>still available.
> >>>
> >>>Do they really need 100kHz that's better than what the "drecky" 4046
> >>>can supply? If not, why complain?
> >>
> >>"Drecky" is a Larkin comment only because he thinks I designed it. I
> >>didn't. It's some poor copy, done by... I have no clue. The VCO, in
> >>particular, is a real kludge.
> >
> > You just made no sense at all. You agree with me that the 4046 is a
> > pretty bad part. I never said you designed it, and never suspected
> > that you did. It was an old RCA design originally.
>
> John, do you have any more information on the original RCA 4046 design?
>
> Did they also do the 4044? Do you recall any dates when they were on the
> market?
Both the Motorola parts were TTL, and putting them together in one chip would probably have produced a device that ran too hot to work. Motorola certainly paired them up in its publicity material, and I used them as a pair back in 1972.
John K
Jun 29, 2013, 2:00:22 AM6/29/13
to
John Larkin <jjla...@highNOTlandTHIStechnologyPART.com> wrote:
> According to the 1980 RCA COS/MOS Data Book, the CD4044 was a
> "three-state quad latch."
> There must be databooks online somewhere. If not, I can scan the
> CD4046 part of the book, which is 6 pages and a lot of data, including
> an image of the mask.
> The CD4046A is listed in the 1975 RCA Solid-State Devices Manual too.
Thanks very much for your help. I am trying to track down examples of the
> According to the 1980 RCA COS/MOS Data Book, the CD4044 was a
> "three-state quad latch."
> There must be databooks online somewhere. If not, I can scan the
> CD4046 part of the book, which is 6 pages and a lot of data, including
> an image of the mask.
> The CD4046A is listed in the 1975 RCA Solid-State Devices Manual too.
phase-frequency detector prior to Ron Treadway's 1971 patent:
http://www.google.com/patents?vid=uspat3610954
Dobbie's 1961 patent looks very similar:
http://www.google.com/patents?vid=uspat2985773
I understand there was a British radio receiver from this time frame that
used a similar configuration, but I have so far had no luck in locating
any more information.
The phase-frequency detector is probably one of the most important single
inventions in frequency synthesis, and it is buried inside a great deal
of conventional technology. Nobody knows it even exists. I'd like to
learn more about who first invented it, where it was used, and what other
inventions and technological developments resulted.
Thanks again for your help.
JK
Bill Sloman
Jun 29, 2013, 10:37:15 AM6/29/13
to
The first is referenced back to a paper by C.J. Byrne, "Properties and design of the Phase-Controlled Oscillator with a Sawtooth Comparator", published in March 1962 in the Bell System Technical Journal, volume 41, pages 559-602. The other is referenced to the Motorola and RCA data books for 1973 and 1972 respectively.
There are suggestions that Floyd M. Gardener didn't like Motorola - Ron Treadway's 1971 patent should have had precedence, if Gardner knew about it, and presumably Treadway's patent was carefully formulated to get around whatever it was that Byrne had published.
--
Bill Sloman, Sydney
Jim Thompson
Jun 29, 2013, 10:39:36 AM6/29/13
to
On Sat, 29 Jun 2013 06:00:22 GMT, John K <sp...@me.not> wrote:
[snip]
and was implemented in digital by Ron Treadway back when we were both
employed by Motorola in the mid '60's and were trying to make our
2-meter rigs tune nicely....
http://www.analog-innovations.com/SED/MC4044_MC4344.pdf
>
>Thanks again for your help.
>
>JK
[snip]
>
>The phase-frequency detector is probably one of the most important single
>inventions in frequency synthesis, and it is buried inside a great deal
>of conventional technology. Nobody knows it even exists. I'd like to
>learn more about who first invented it, where it was used, and what other
>inventions and technological developments resulted.
The PFD edge sequence scheme and charge-pump was my conceptual idea,
>The phase-frequency detector is probably one of the most important single
>inventions in frequency synthesis, and it is buried inside a great deal
>of conventional technology. Nobody knows it even exists. I'd like to
>learn more about who first invented it, where it was used, and what other
>inventions and technological developments resulted.
and was implemented in digital by Ron Treadway back when we were both
employed by Motorola in the mid '60's and were trying to make our
2-meter rigs tune nicely....
http://www.analog-innovations.com/SED/MC4044_MC4344.pdf
>
>Thanks again for your help.
>
>JK
John Larkin
Jun 29, 2013, 11:28:06 AM6/29/13
to
On Sat, 29 Jun 2013 07:39:36 -0700, Jim Thompson
<To-Email-Use-Th...@On-My-Web-Site.com> wrote:
>On Sat, 29 Jun 2013 06:00:22 GMT, John K <sp...@me.not> wrote:
>
>[snip]
>>
>>The phase-frequency detector is probably one of the most important single
>>inventions in frequency synthesis, and it is buried inside a great deal
>>of conventional technology. Nobody knows it even exists. I'd like to
>>learn more about who first invented it, where it was used, and what other
>>inventions and technological developments resulted.
>
>The PFD edge sequence scheme and charge-pump was my conceptual idea,
>and was implemented in digital by Ron Treadway back when we were both
>employed by Motorola in the mid '60's and were trying to make our
>2-meter rigs tune nicely....
>
>http://www.analog-innovations.com/SED/MC4044_MC4344.pdf
>
>>
>>Thanks again for your help.
>>
>>JK
>
> ...Jim Thompson
Why aren't you listed on the patent as a co-inventor?
<To-Email-Use-Th...@On-My-Web-Site.com> wrote:
>On Sat, 29 Jun 2013 06:00:22 GMT, John K <sp...@me.not> wrote:
>
>[snip]
>>
>>The phase-frequency detector is probably one of the most important single
>>inventions in frequency synthesis, and it is buried inside a great deal
>>of conventional technology. Nobody knows it even exists. I'd like to
>>learn more about who first invented it, where it was used, and what other
>>inventions and technological developments resulted.
>
>The PFD edge sequence scheme and charge-pump was my conceptual idea,
>and was implemented in digital by Ron Treadway back when we were both
>employed by Motorola in the mid '60's and were trying to make our
>2-meter rigs tune nicely....
>
>http://www.analog-innovations.com/SED/MC4044_MC4344.pdf
>
>>
>>Thanks again for your help.
>>
>>JK
>
> ...Jim Thompson
Treadway did cite Dobbie as prior art.
John Larkin
Jun 29, 2013, 11:30:32 AM6/29/13
to
On Sat, 29 Jun 2013 06:00:22 GMT, John K <sp...@me.not> wrote:
>John Larkin <jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>
>> According to the 1980 RCA COS/MOS Data Book, the CD4044 was a
>> "three-state quad latch."
>
>> There must be databooks online somewhere. If not, I can scan the
>> CD4046 part of the book, which is 6 pages and a lot of data, including
>> an image of the mask.
>
>> The CD4046A is listed in the 1975 RCA Solid-State Devices Manual too.
>
>Thanks very much for your help. I am trying to track down examples of the
>phase-frequency detector prior to Ron Treadway's 1971 patent:
>
>http://www.google.com/patents?vid=uspat3610954
>
>Dobbie's 1961 patent looks very similar:
>
>http://www.google.com/patents?vid=uspat2985773
>
>I understand there was a British radio receiver from this time frame that
>used a similar configuration, but I have so far had no luck in locating
>any more information.
>
>The phase-frequency detector is probably one of the most important single
>inventions in frequency synthesis, and it is buried inside a great deal
>of conventional technology. Nobody knows it even exists.
We sure do! We embedd a deadband-free version inside FPGAs all the time. We
>John Larkin <jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>
>> According to the 1980 RCA COS/MOS Data Book, the CD4044 was a
>> "three-state quad latch."
>
>> There must be databooks online somewhere. If not, I can scan the
>> CD4046 part of the book, which is 6 pages and a lot of data, including
>> an image of the mask.
>
>> The CD4046A is listed in the 1975 RCA Solid-State Devices Manual too.
>
>Thanks very much for your help. I am trying to track down examples of the
>phase-frequency detector prior to Ron Treadway's 1971 patent:
>
>http://www.google.com/patents?vid=uspat3610954
>
>Dobbie's 1961 patent looks very similar:
>
>http://www.google.com/patents?vid=uspat2985773
>
>I understand there was a British radio receiver from this time frame that
>used a similar configuration, but I have so far had no luck in locating
>any more information.
>
>The phase-frequency detector is probably one of the most important single
>inventions in frequency synthesis, and it is buried inside a great deal
>of conventional technology. Nobody knows it even exists.
don't use a charge pump, but a pair of hard logic outputs, into a dual schottky
diode and an RC or opamp.
Jim Thompson
Jun 29, 2013, 11:31:42 AM6/29/13
to
On Sat, 29 Jun 2013 08:28:06 -0700, John Larkin
<jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>On Sat, 29 Jun 2013 07:39:36 -0700, Jim Thompson
><To-Email-Use-Th...@On-My-Web-Site.com> wrote:
>
>>On Sat, 29 Jun 2013 06:00:22 GMT, John K <sp...@me.not> wrote:
>>
>>[snip]
>>>
>>>The phase-frequency detector is probably one of the most important single
>>>inventions in frequency synthesis, and it is buried inside a great deal
>>>of conventional technology. Nobody knows it even exists. I'd like to
>>>learn more about who first invented it, where it was used, and what other
>>>inventions and technological developments resulted.
>>
>>The PFD edge sequence scheme and charge-pump was my conceptual idea,
>>and was implemented in digital by Ron Treadway back when we were both
>>employed by Motorola in the mid '60's and were trying to make our
>>2-meter rigs tune nicely....
>>
>>http://www.analog-innovations.com/SED/MC4044_MC4344.pdf
>>
>>>
>>>Thanks again for your help.
>>>
>>>JK
>>
>> ...Jim Thompson
>
>Why aren't you listed on the patent as a co-inventor?
>
>Treadway did cite Dobbie as prior art.
I didn't contribute to the circuit, I just told Ron, "Here's what I'd
<jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>On Sat, 29 Jun 2013 07:39:36 -0700, Jim Thompson
><To-Email-Use-Th...@On-My-Web-Site.com> wrote:
>
>>On Sat, 29 Jun 2013 06:00:22 GMT, John K <sp...@me.not> wrote:
>>
>>[snip]
>>>
>>>The phase-frequency detector is probably one of the most important single
>>>inventions in frequency synthesis, and it is buried inside a great deal
>>>of conventional technology. Nobody knows it even exists. I'd like to
>>>learn more about who first invented it, where it was used, and what other
>>>inventions and technological developments resulted.
>>
>>The PFD edge sequence scheme and charge-pump was my conceptual idea,
>>and was implemented in digital by Ron Treadway back when we were both
>>employed by Motorola in the mid '60's and were trying to make our
>>2-meter rigs tune nicely....
>>
>>http://www.analog-innovations.com/SED/MC4044_MC4344.pdf
>>
>>>
>>>Thanks again for your help.
>>>
>>>JK
>>
>> ...Jim Thompson
>
>Why aren't you listed on the patent as a co-inventor?
>
>Treadway did cite Dobbie as prior art.
like it to do..."
I can round up Ron to verify that, if you're out to make an issue of
it.
Jim Thompson
Jun 29, 2013, 11:33:22 AM6/29/13
to
On Sat, 29 Jun 2013 08:30:32 -0700, John Larkin
<jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>On Sat, 29 Jun 2013 06:00:22 GMT, John K <sp...@me.not> wrote:
>
>>John Larkin <jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>>
>>> According to the 1980 RCA COS/MOS Data Book, the CD4044 was a
>>> "three-state quad latch."
>>
>>> There must be databooks online somewhere. If not, I can scan the
>>> CD4046 part of the book, which is 6 pages and a lot of data, including
>>> an image of the mask.
>>
>>> The CD4046A is listed in the 1975 RCA Solid-State Devices Manual too.
>>
>>Thanks very much for your help. I am trying to track down examples of the
>>phase-frequency detector prior to Ron Treadway's 1971 patent:
>>
>>http://www.google.com/patents?vid=uspat3610954
>>
>>Dobbie's 1961 patent looks very similar:
>>
>>http://www.google.com/patents?vid=uspat2985773
>>
>>I understand there was a British radio receiver from this time frame that
>>used a similar configuration, but I have so far had no luck in locating
>>any more information.
>>
>>The phase-frequency detector is probably one of the most important single
>>inventions in frequency synthesis, and it is buried inside a great deal
>>of conventional technology. Nobody knows it even exists.
>
>We sure do! We embedd a deadband-free version inside FPGAs all the time. We
>don't use a charge pump, but a pair of hard logic outputs, into a dual schottky
>diode and an RC or opamp.
And in many of my custom I/C's, even in a recent chip that measures
<jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>On Sat, 29 Jun 2013 06:00:22 GMT, John K <sp...@me.not> wrote:
>
>>John Larkin <jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>>
>>> According to the 1980 RCA COS/MOS Data Book, the CD4044 was a
>>> "three-state quad latch."
>>
>>> There must be databooks online somewhere. If not, I can scan the
>>> CD4046 part of the book, which is 6 pages and a lot of data, including
>>> an image of the mask.
>>
>>> The CD4046A is listed in the 1975 RCA Solid-State Devices Manual too.
>>
>>Thanks very much for your help. I am trying to track down examples of the
>>phase-frequency detector prior to Ron Treadway's 1971 patent:
>>
>>http://www.google.com/patents?vid=uspat3610954
>>
>>Dobbie's 1961 patent looks very similar:
>>
>>http://www.google.com/patents?vid=uspat2985773
>>
>>I understand there was a British radio receiver from this time frame that
>>used a similar configuration, but I have so far had no luck in locating
>>any more information.
>>
>>The phase-frequency detector is probably one of the most important single
>>inventions in frequency synthesis, and it is buried inside a great deal
>>of conventional technology. Nobody knows it even exists.
>
>We sure do! We embedd a deadband-free version inside FPGAs all the time. We
>don't use a charge pump, but a pair of hard logic outputs, into a dual schottky
>diode and an RC or opamp.
soil moisture ;-)
John Larkin
Jun 29, 2013, 11:42:36 AM6/29/13
to
On Sat, 29 Jun 2013 08:31:42 -0700, Jim Thompson
So you described what you wanted, not how to implement it?
Either you didn't invent anything, or you weren't properly credited.
Either you didn't invent anything, or you weren't properly credited.
Jim Thompson
Jun 29, 2013, 11:48:21 AM6/29/13
to
On Sat, 29 Jun 2013 08:42:36 -0700, John Larkin
Correct. I told Ron what an ideal PFD would do, but had no clue about
how to do it... at least back then... my current bag of tricks
includes how to do it when there are missing edges.
>
>Either you didn't invent anything, or you weren't properly credited.
I didn't invent the circuit... just like your customers who come in
and ask for a box to "do so and so" didn't design the your box.
how to do it... at least back then... my current bag of tricks
includes how to do it when there are missing edges.
>
>Either you didn't invent anything, or you weren't properly credited.
and ask for a box to "do so and so" didn't design the your box.
John K
Jun 29, 2013, 11:59:21 AM6/29/13
to
John Larkin <jjla...@highNOTlandTHIStechnologyPART.com> wrote:
> We sure do! We embedd a deadband-free version inside FPGAs all the
> time. We don't use a charge pump, but a pair of hard logic outputs,
> into a dual schottky diode and an RC or opamp.
Deadband comes from the analog charge pump, and not the digital logic
> We sure do! We embedd a deadband-free version inside FPGAs all the
> time. We don't use a charge pump, but a pair of hard logic outputs,
> into a dual schottky diode and an RC or opamp.
portion. When you are on time, the narrow pulses won't go through the
charge pump so there is no correction. When you have a small time offset,
the pulse widens and starts to go through the charge pump so you start to
get correction.
The op amp is unlikely to be fast enough to follow the narrow on-time
pulses, so you probably are getting deadband. But crosstalk to the vco can
injection-lock the oscillator to the reference and make it seem you have no
deadband.
Worst possible combination you can have.
JK
Jim Thompson
Jun 29, 2013, 12:05:53 PM6/29/13
to
external resistors for accuracy, if I can convince the customer ;-)
The best game is to have one external resistor set a master current
reference... then everything is ratiometric internally, and absolute
values (+/- 25% on-chip) don't matter nearly so much.
John Larkin
Jun 29, 2013, 12:45:43 PM6/29/13
to
On Sat, 29 Jun 2013 15:59:21 GMT, John K <sp...@me.not> wrote:
>John Larkin <jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>
>> We sure do! We embedd a deadband-free version inside FPGAs all the
>> time. We don't use a charge pump, but a pair of hard logic outputs,
>> into a dual schottky diode and an RC or opamp.
>
>Deadband comes from the analog charge pump, and not the digital logic
>portion. When you are on time, the narrow pulses won't go through the
>charge pump so there is no correction. When you have a small time offset,
>the pulse widens and starts to go through the charge pump so you start to
>get correction.
It's not hard to make the charge pump UP and DOWN blips overlap a little,
>John Larkin <jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>
>> We sure do! We embedd a deadband-free version inside FPGAs all the
>> time. We don't use a charge pump, but a pair of hard logic outputs,
>> into a dual schottky diode and an RC or opamp.
>
>Deadband comes from the analog charge pump, and not the digital logic
>portion. When you are on time, the narrow pulses won't go through the
>charge pump so there is no correction. When you have a small time offset,
>the pulse widens and starts to go through the charge pump so you start to
>get correction.
eliminating the deadband. In our voltage-output version, we also overlap a
little to kill the deadband. That increases the loop gain by 2:1 in the narrow
overlap region, no problem if you plan for it.
FPGA outputs aren't ideal for charge pumping; the tristates are slower paths
than the logic levels, and the pullup/pulldown currents are vaguely defined. A
dual diode and a couple of resistors fix all that.
>
>The op amp is unlikely to be fast enough to follow the narrow on-time
>pulses, so you probably are getting deadband.
The opamp is slow, like kilohertz closed-loop bandwidth in a 100 MHz PLL. We
generally plan for the PLL bandwidth to align with the VCO 1/f phase noise
corner, to pick up control where we need it. That minimizes jitter.
But crosstalk to the vco can
>injection-lock the oscillator to the reference and make it seem you have no
>deadband.
>
>Worst possible combination you can have.
John K
Jun 30, 2013, 12:22:44 PM6/30/13
to
John Larkin <jjla...@highNOTlandTHIStechnologyPART.com> wrote:
> On Sat, 29 Jun 2013 15:59:21 GMT, John K <sp...@me.not> wrote:
>
>>John Larkin <jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>>
>>> We sure do! We embedd a deadband-free version inside FPGAs all the
>>> time. We don't use a charge pump, but a pair of hard logic outputs,
>>> into a dual schottky diode and an RC or opamp.
>>
>>Deadband comes from the analog charge pump, and not the digital logic
>>portion. When you are on time, the narrow pulses won't go through the
>>charge pump so there is no correction. When you have a small time
>>offset, the pulse widens and starts to go through the charge pump so
>>you start to get correction.
>
> It's not hard to make the charge pump UP and DOWN blips overlap a
> little, eliminating the deadband.
The deadband does not occur in the digital logic. Deadband occurs in the
> On Sat, 29 Jun 2013 15:59:21 GMT, John K <sp...@me.not> wrote:
>
>>John Larkin <jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>>
>>> We sure do! We embedd a deadband-free version inside FPGAs all the
>>> time. We don't use a charge pump, but a pair of hard logic outputs,
>>> into a dual schottky diode and an RC or opamp.
>>
>>Deadband comes from the analog charge pump, and not the digital logic
>>portion. When you are on time, the narrow pulses won't go through the
>>charge pump so there is no correction. When you have a small time
>>offset, the pulse widens and starts to go through the charge pump so
>>you start to get correction.
>
> It's not hard to make the charge pump UP and DOWN blips overlap a
> little, eliminating the deadband.
analog portion that follows the phase detector, when it cannot respond to
the small pulse widths around zero.
The sample terminates when both latches are clocked. The NAND feedback
starts when the signal from both latches has propagated to the output.
The output is applied to the latch resets. Both latches start to reset,
and the NAND is no longer satisfied. The reset pulse goes away when the
result has propagated through the NAND. The reset pulse width is twice
the propagation delay through the loop.
During the reset, both latches are turned on. The UP and DOWN blips are
both on and theoretically cancel at the junction of the resistors so
there is no net signal to the op amp.
The problem occurs when there is a small time error around zero. If the
op amp does not respond, then the output to the VCO doesn't change. This
means time small errors are not corrected, resulting in deadband.
> In our voltage-output version, we
> also overlap a little to kill the deadband. That increases the loop
> gain by 2:1 in the narrow overlap region, no problem if you plan for
> it.
this time, the UP and DOWN blips cancel at the junction of the resistors.
There is no output from the phase detector, so there is no input to the
op amp.
The problem occurs when there is a small time error in the input signals.
The Up and DOWN blips no longer cancel at the beginning. This creates
narrow pulses to the input of the op amp. The result depends on how the
op amp responds.
[...]
>>The op amp is unlikely to be fast enough to follow the narrow on-time
>>pulses, so you probably are getting deadband.
>
> Well, no. Charge is still conserved. The diode current has to go
> somewhere.
loop filter is lost. Charge is no longer conserved.
> The opamp is slow, like kilohertz closed-loop bandwidth in a 100 MHz
> PLL. We generally plan for the PLL bandwidth to align with the VCO 1/f
> phase noise corner, to pick up control where we need it. That
> minimizes jitter.
zero.
> But crosstalk to the vco can
>>injection-lock the oscillator to the reference and make it seem you
>>have no deadband.
>>
>>Worst possible combination you can have.
>
> Well, no.
RC oscillators are very easy to injection-lock. It is much harder to
injection-lock a LC oscillator.
Phil had a revelation recently about using RC oscillators compared to LC
oscillators in a PLL. From his post on Tue, 25 June:
> I've used LC VCOs in similar situations. Really dramatically
> better than a 4046's oscillator.
> Cheers
> Phil Hobbs
The problem with an RC oscillator is it has no phase memory. You can
change the phase instantaneously. A small amount of crosstalk can cause a
step change in the phase of the oscillator.
This means the PLL loop now has an error, which will drive the oscillator
back to zero error. It returns to the spot where it got in trouble in the
first place, and crosstalk drives it away again.
This sets up a limit cycle oscillation, which can be bad enough to render
the loop useless.
I have never built a PLL using a RC oscillator that you can't find a
limit cycle oscillation somewhere in the loop range. However, it is much
harder to do a step change in phase in an LC oscillator, since the tank
provides a flywheel effect that remembers the phase of the previous
cycles.
JK
John Larkin
Jun 30, 2013, 12:58:00 PM6/30/13
to
On Sun, 30 Jun 2013 16:22:44 GMT, John K <sp...@me.not> wrote:
>John Larkin <jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>
>> On Sat, 29 Jun 2013 15:59:21 GMT, John K <sp...@me.not> wrote:
>>
>>>John Larkin <jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>>>
>>>> We sure do! We embedd a deadband-free version inside FPGAs all the
>>>> time. We don't use a charge pump, but a pair of hard logic outputs,
>>>> into a dual schottky diode and an RC or opamp.
>>>
>>>Deadband comes from the analog charge pump, and not the digital logic
>>>portion. When you are on time, the narrow pulses won't go through the
>>>charge pump so there is no correction. When you have a small time
>>>offset, the pulse widens and starts to go through the charge pump so
>>>you start to get correction.
>>
>> It's not hard to make the charge pump UP and DOWN blips overlap a
>> little, eliminating the deadband.
>
>The deadband does not occur in the digital logic. Deadband occurs in the
>analog portion that follows the phase detector, when it cannot respond to
>the small pulse widths around zero.
>
>The sample terminates when both latches are clocked. The NAND feedback
>starts when the signal from both latches has propagated to the output.
>
So add a little prop delay somewhere to force both the UP and DOWN pulses to be
>John Larkin <jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>
>> On Sat, 29 Jun 2013 15:59:21 GMT, John K <sp...@me.not> wrote:
>>
>>>John Larkin <jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>>>
>>>> We sure do! We embedd a deadband-free version inside FPGAs all the
>>>> time. We don't use a charge pump, but a pair of hard logic outputs,
>>>> into a dual schottky diode and an RC or opamp.
>>>
>>>Deadband comes from the analog charge pump, and not the digital logic
>>>portion. When you are on time, the narrow pulses won't go through the
>>>charge pump so there is no correction. When you have a small time
>>>offset, the pulse widens and starts to go through the charge pump so
>>>you start to get correction.
>>
>> It's not hard to make the charge pump UP and DOWN blips overlap a
>> little, eliminating the deadband.
>
>The deadband does not occur in the digital logic. Deadband occurs in the
>analog portion that follows the phase detector, when it cannot respond to
>the small pulse widths around zero.
>
>The sample terminates when both latches are clocked. The NAND feedback
>starts when the signal from both latches has propagated to the output.
>
finite width and overlapping a bit at zero phase error. That works whether you
use a charge pump or hard UP/DOWN outputs. Tons of people have done it.
>The output is applied to the latch resets. Both latches start to reset,
>and the NAND is no longer satisfied. The reset pulse goes away when the
>result has propagated through the NAND. The reset pulse width is twice
>the propagation delay through the loop.
>
>During the reset, both latches are turned on. The UP and DOWN blips are
>both on and theoretically cancel at the junction of the resistors so
>there is no net signal to the op amp.
>
>The problem occurs when there is a small time error around zero. If the
>op amp does not respond, then the output to the VCO doesn't change. This
>means time small errors are not corrected, resulting in deadband.
>
>> In our voltage-output version, we
>> also overlap a little to kill the deadband. That increases the loop
>> gain by 2:1 in the narrow overlap region, no problem if you plan for
>> it.
>
>Adding delay to the phase detector reset increases the overlap. During
>this time, the UP and DOWN blips cancel at the junction of the resistors.
>There is no output from the phase detector, so there is no input to the
>op amp.
question is: what's the graph of opamp input current versus phase error. The
4046 has a flat spot around zero. Other phase detectors don't.
>
>The problem occurs when there is a small time error in the input signals.
>The Up and DOWN blips no longer cancel at the beginning. This creates
>narrow pulses to the input of the op amp. The result depends on how the
>op amp responds.
>
>[...]
>
>>>The op amp is unlikely to be fast enough to follow the narrow on-time
>>>pulses, so you probably are getting deadband.
>>
>> Well, no. Charge is still conserved. The diode current has to go
>> somewhere.
>
>That's the problem. If the op amp overloads, the feedback through the
>loop filter is lost. Charge is no longer conserved.
>
>> The opamp is slow, like kilohertz closed-loop bandwidth in a 100 MHz
>> PLL. We generally plan for the PLL bandwidth to align with the VCO 1/f
>> phase noise corner, to pick up control where we need it. That
>> minimizes jitter.
>
>That slow op amp means it won't respond well to narrow pulses around
>zero.
electrons.
better, narrowband oscillator, LC or XO, if you want low noise. And use a phase
detector with no deadband.
Here's a circuit we've used a couple of times.
https://dl.dropboxusercontent.com/u/53724080/Circuits/Phase_Detector.jpg
the up/down blips come from the phase-frequency detector in an FPGA and the
opamp output goes to a VCXO. One cute trick is that we can lock the VCXO if we
have an external reference, or use it unlocked but calibrated if we don't. In
unlocked mode, we turn on U4 to make the opamp amplify (not integrate) and use
the up/down signals as a delta-sigma DAC, with value from a cal table in eeprom.
John K
Jun 30, 2013, 2:23:19 PM6/30/13
to
John Larkin <jjla...@highNOTlandTHIStechnologyPART.com> wrote:
> On Sun, 30 Jun 2013 16:22:44 GMT, John K <sp...@me.not> wrote:
>
>>The sample terminates when both latches are clocked. The NAND feedback
>>starts when the signal from both latches has propagated to the output.
> So add a little prop delay somewhere to force both the UP and DOWN
> pulses to be finite width and overlapping a bit at zero phase error.
> That works whether you use a charge pump or hard UP/DOWN outputs. Tons
> of people have done it.
The UP and DOWN pulses are already finite width.
> On Sun, 30 Jun 2013 16:22:44 GMT, John K <sp...@me.not> wrote:
>
>>The sample terminates when both latches are clocked. The NAND feedback
>>starts when the signal from both latches has propagated to the output.
> So add a little prop delay somewhere to force both the UP and DOWN
> pulses to be finite width and overlapping a bit at zero phase error.
> That works whether you use a charge pump or hard UP/DOWN outputs. Tons
> of people have done it.
The only place you can add delay is in the NAND feedback path.
In this circuit, the overlap width has little or no effect since the UP
and DOWN pulses cancel during the overlap.
>>>>The op amp is unlikely to be fast enough to follow the narrow
>>>>on-time pulses, so you probably are getting deadband.
>>>
>>> Well, no. Charge is still conserved. The diode current has to go
>>> somewhere.
>>
>>That's the problem. If the op amp overloads, the feedback through the
>>loop filter is lost. Charge is no longer conserved.
>
> Why would it overload with a small loop error?
due to the high gain. The result depends on how the op amp responds to
overload.
> Here's a circuit we've used a couple of times.
>
> https://dl.dropboxusercontent.com/u/53724080/Circuits/Phase_Detector.jp
> g
input to the op amp. This can create problems around zero phase error
when the op amp can't respond to the narrow pulses. The performance
depends on the op amp characteristics.
I made a simple PFD and Op Amp analysis circuit for you. The circuit
sweeps the phase error from +48ns to -48 ns in 2ns steps. You can zoom in
on each sample to see what is happening on that sample. On Time is in the
exact center at the 25uS sample.
The parameters for each device are brought out to a spice directive. You
can edit the D-flop and NAND speed, and the Gain, Bandwidth and Slew Rate
of the op amp by clicking on the desired directive and editing it.
You can see what happens when you change the width of the UP and DOWN
pulses by changing the NAND delay. In this circuit, yu will see it has
little effect on the op amp response since the UP and DOWN currents
cancel each other during the overlap time.
Changing the bandwidth and/or slew rate of the op amp can have a dramatic
effect on the response around zero.
You can add the op amp of your choice and see how it responds to the
narrow pulses around zero.
I added a ripple filter to the input of the op amp. You can cut the trace
from the PD output and connect the filter in its place. You can see it
has a dramatic effect on the response of the op amp by reducing the
amplitude of the pulses from the phase detector.
All these effects are only to give an idea how an actual loop will
respond. They do not include effects such as crosstalk and are no
substitute for measurements on the bench.
You will need Helmut's 74HC.lib installed, plus a small text file for the
1n5771 which I supply below.
JK
Version 4
SHEET 1 1260 800
WIRE -176 96 -224 96
WIRE -144 96 -176 96
WIRE -16 96 -80 96
WIRE 80 96 64 96
WIRE 432 160 416 160
WIRE 528 160 512 160
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WIRE 464 464 464 448
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WIRE -512 496 -560 496
WIRE -416 512 -448 512
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WIRE -16 512 -80 512
WIRE 80 512 80 304
WIRE 80 512 64 512
WIRE -736 528 -736 208
WIRE -512 528 -736 528
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WIRE -592 576 -592 496
WIRE -304 592 -304 576
WIRE -192 592 -304 592
WIRE -32 592 -32 272
WIRE -32 592 -192 592
WIRE -736 672 -736 656
WIRE -592 672 -592 656
FLAG -416 256 VCC
FLAG -304 32 VCC
FLAG -384 96 VCC
FLAG -304 352 VCC
FLAG -384 416 VCC
FLAG -416 512 VCO
FLAG -416 192 DATA
FLAG -192 592 CLR
FLAG -416 352 0
FLAG 128 400 0
FLAG 256 400 0
FLAG -592 672 0
FLAG -736 672 0
FLAG -592 352 0
FLAG -688 208 Ramp
FLAG -576 176 Dly
FLAG -560 496 Ref
FLAG -480 224 0
FLAG -480 160 VCC
FLAG -480 544 0
FLAG -480 480 VCC
FLAG 464 304 Vin
FLAG 640 240 VDC
FLAG 464 464 0
FLAG 528 352 0
FLAG 528 288 VCC
SYMBOL Voltage -416 240 R0
WINDOW 3 28 84 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR Value +5V
SYMATTR InstName V1
SYMBOL 74hc74 -304 32 R0
WINDOW 40 20 14 Left 2
SYMATTR InstName U1
SYMATTR SpiceLine VCC=5 TRIPDT=1e-9
SYMATTR SpiceLine2 SPEED=1
SYMBOL 74hc74 -304 352 R0
WINDOW 40 -45 260 Left 2
SYMATTR InstName U2
SYMATTR SpiceLine VCC=5 DELAY=0.1 TRIPDT=1e-9
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SYMATTR InstName U3
SYMATTR SpiceLine VCC=5 TRIPDT=1e-9
SYMATTR SpiceLine2 SPEED=1
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WINDOW 0 0 56 VBottom 2
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SYMATTR InstName UP
SYMATTR Value 1k
SYMBOL res 80 496 R90
WINDOW 0 0 56 VBottom 2
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SYMATTR Value 1k
SYMBOL cap 112 320 R0
SYMATTR InstName C1
SYMATTR Value 1n
SYMBOL res 256 288 R90
WINDOW 0 0 56 VBottom 2
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SYMATTR InstName R3
SYMATTR Value 1k
SYMBOL cap 240 320 R0
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SYMATTR Value 500p
SYMBOL cap 512 224 R90
WINDOW 0 0 32 VBottom 2
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SYMATTR Value 10n
SYMBOL cap 608 224 R90
WINDOW 0 0 32 VBottom 2
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SYMATTR Value 1n
SYMBOL res 528 144 R90
WINDOW 0 0 56 VBottom 2
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SYMATTR Value 1k
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SYMATTR InstName R4
SYMATTR Value 1k
SYMBOL voltage -592 560 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value 2V
SYMBOL voltage -736 560 R0
WINDOW 3 4 149 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR Value PULSE(0 4 500n 1u 0 0 1u)
SYMATTR InstName V3
SYMBOL voltage -592 240 R0
WINDOW 3 -102 146 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR Value PULSE(1.8 2.2 0 50u 1ns 1n)
SYMATTR InstName V4
SYMBOL opamps\\1pole -480 192 R0
SYMATTR InstName U5
SYMATTR Value2 Avol=1Meg GBW=1e9 Slew=1e9
SYMBOL opamps\\1pole -480 512 R0
SYMATTR InstName U6
SYMATTR Value2 Avol=1Meg GBW=1e9 Slew=1e9
SYMBOL diode -144 112 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName X1
SYMATTR Value DN5711
SYMATTR Prefix X
SYMBOL diode -80 496 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName X2
SYMATTR Value DN5711
SYMATTR Prefix X
SYMBOL Voltage 464 352 R0
WINDOW 3 28 84 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR Value 2.5V
SYMATTR InstName V5
SYMBOL opamps\\1pole 528 320 R0
WINDOW 123 -119 181 Left 2
SYMATTR InstName U4
SYMATTR Value2 Avol=1Meg GBW=1e6 Slew=1e6
SYMATTR SpiceLine2 en=0 enk=0 in=0 ink=0 Rin=10Meg
TEXT -376 -64 Left 2 ;'PFD and Op Amp Analysis
TEXT -376 -40 Left 2 !.tran 0 50u 0
TEXT 160 24 Left 2 !.include 74hc.lib
TEXT 160 -48 Left 2 !.options plotwinsize=0
TEXT 160 96 Left 2 ;NOTE: Filter values are for illustrative purposes
only
TEXT 160 -32 Left 2 !.options nomarch
TEXT 160 0 Left 2 !.ic V(VDC) = 2.5
TEXT 160 40 Left 2 !.include dn5711.txt
TEXT 160 432 Left 2 ;Ripple Filter
[Transient Analysis]
{
Npanes: 3
Active Pane: 2
{
traces: 1 {524293,0,"V(vin)"}
X: ('µ',0,0,5e-006,5e-005)
Y[0]: (' ',3,2.486,0.002,2.512)
Y[1]: ('m',1,1e+308,0.0003,-1e+308)
Volts: (' ',0,0,3,2.486,0.002,2.512)
Log: 0 0 0
GridStyle: 1
},
{
traces: 2 {34603010,0,"I(Up)"} {34603011,0,"I(Down)"}
X: ('µ',0,0,5e-006,5e-005)
Y[0]: ('m',1,-0.0016,0.0004,0.0024)
Y[1]: ('m',0,1e+308,0.01,-1e+308)
Amps: ('m',0,0,1,-0.0016,0.0004,0.0024)
Log: 0 0 0
GridStyle: 1
},
{
traces: 1 {589828,0,"V(vdc)"}
X: ('µ',0,0,5e-006,5e-005)
Y[0]: (' ',1,1.5,0.1,2.6)
Y[1]: ('m',0,1e+308,0.01,-1e+308)
Volts: (' ',0,0,1,1.5,0.1,2.6)
Log: 0 0 0
GridStyle: 1
}
}
Save the following as dn5711.txt
****************************************
* (c)1999 Thomatronik GmbH *
* in...@thomatronik.de *
* *
* Author: Arpad Buermen *
* Arpad....@ieee.org *
****************************************
*Pin order A K
.SUBCKT DN5711 1 2
.MODEL SD D (
+ N=1.68359
+ IS=1.50122E-007
+ RS=31.3769
+ EG=0.69
+ XTI=2
+ CJO=2E-012
+ VJ=0.393705
+ M=0.196045
+ FC=0.5
+ TT=1.4427E-009
+ BV=70
+ IBV=0.001
+ KF=0
+ AF=1)
.MODEL PND D (
+ N=1.14222
+ IS=1.16495E-014
+ RS=1.06783
+ EG=1.11
+ XTI=3)
D1 1 2 SD
D2 1 2 PND
.ENDS
John K
Jun 30, 2013, 2:32:25 PM6/30/13
to
Sorry - please fix the wrap on the following line:
TEXT 160 96 Left 2 ;NOTE: Filter values are for illustrative purposes
only
JK
TEXT 160 96 Left 2 ;NOTE: Filter values are for illustrative purposes
only
Jim Thompson
Jun 30, 2013, 4:42:09 PM6/30/13
to
control is very high impedance).
Charge pump UP/DN are switchable current mirrors with a defined
current (external R) and operate into a series RC to ground (also
external, single-pin). Above loop bandwidth this RC is paralleled
with another C to "de-spur".
So I get the requisite lead-lag without the pain of an OpAmp
struggling to keep up.
John K
Jun 30, 2013, 10:35:09 PM6/30/13
to
I have been following the thread "Boost Converter Efficiency
Improvements" and the struggle to improve the analysis speed using the
SMS7621.
I tried it in the PFD Analysis circuit and found it was orders of
magnitude slower than the 1N5711. I mean really, really slow. It is
unusable.
The 1N5711 has an undesirable undershoot when turning off. In real life,
the SMS7621 probably has much less undershoot, but it is impossible to
use it in LTspice.
Since all we want for that function in the circuit is a fast diode with
no undershoot, I looked for another way to perform the same function. It
turns out a diode-connected BFG198 is perfect. It is fast and has no
undesirable underdshoot when turning off. The model statement is
.model BFG198 NPN(IS=1.8998E-15 ISE=7.1424E-14 ISC=2.0992E-15
+ XTI=3 BF=132.75 BR=11.407 IKF=0.44125 IKR=0.010016 XTB=1.5
+ VAF=15 VAR=4.1613 VJE=0.85909 VJC=0.81533 RE=1.1351 RC=0.27485
+ RB=1.2652 RBM=1.0893 IRB=2.8135E-5 CJE=5.0933E-15 CJC=2.3278E-12
+ XCJC=0.14496 FC=0.92887 NF=0.89608 NR=0.91008 NE=1.3235 NC=1.4602
+ MJE=0.69062 MJC=0.46849 TF=3.5786E-11 TR=1.2466E-9 PTF=0 ITF=0.062059
+ VTF=0.10681 XTF=0.44444 EG=1.11 KF=1E-9 AF=1 MFG=Siemens)
It obviously doesn't have the same forward drop as a schottky, but if all
you need is a fast diode with no undershoot, it works pretty good.
Here is the new PFD Analysis using the BFG198. You can see what a huge
difference it makes in the I(UP) and I(DOWN) waveforms. Watch the wrap in
the model statement at the end.
Version 4
SHEET 1 4472 800
WIRE 96 32 0 32
WIRE 96 48 96 32
WIRE 0 96 -176 96
WIRE 32 96 0 96
WIRE 96 160 96 144
WIRE 560 176 544 176
WIRE 160 256 96 256
WIRE 448 256 448 176
WIRE 480 256 448 256
WIRE 560 256 560 176
WIRE 560 256 544 256
WIRE 576 256 560 256
WIRE 656 256 640 256
WIRE 672 256 656 256
WIRE 704 256 672 256
WIRE 160 320 160 256
WIRE 192 320 160 320
WIRE 288 320 272 320
WIRE 320 320 288 320
WIRE 448 320 448 256
WIRE 448 320 400 320
WIRE 496 320 448 320
WIRE 528 320 496 320
WIRE 160 336 160 320
WIRE 288 336 288 320
WIRE 656 336 656 256
WIRE 656 336 592 336
WIRE 496 384 496 352
WIRE 96 400 96 384
WIRE 96 400 16 400
WIRE 160 416 160 400
WIRE 288 416 288 400
WIRE 96 464 96 400
WIRE 96 464 80 464
WIRE 496 480 496 464
FLAG 288 416 0
FLAG 672 256 VDC
FLAG 496 480 0
FLAG 560 368 0
FLAG 560 304 VCC
SYMBOL Voltage 496 368 R0
WINDOW 3 64 76 Left 2
SYMATTR Value BFG198
SYMATTR InstName Q1
SYMBOL Npn 80 416 M0
SYMATTR InstName Q2
SYMATTR Value BFG198
only
TEXT -488 648 Left 2 !.model BFG198 NPN(IS=1.8998E-15 ISE=7.1424E-14 ISC=
2.0992E-15 XTI=3 BF=132.75 BR=11.407 IKF=0.44125 IKR=0.010016 XTB=1.5
VAF=15\n+ VAR=4.1613 VJE=0.85909 VJC=0.81533 RE=1.1351 RC=0.27485 RB=
1.2652 RBM=1.0893 IRB=2.8135E-5 CJE=5.0933E-15 CJC=2.3278E-12 \n+ XCJC=
0.14496 FC=0.92887 NF=0.89608 NR=0.91008 NE=1.3235 NC=1.4602 MJE=0.69062
MJC=0.46849 TF=3.5786E-11 TR=1.2466E-9 \n+ PTF=0 ITF=0.062059 VTF=0.10681
XTF=0.44444 EG=1.11 KF=1E-9 AF=1 MFG=Siemens)
Improvements" and the struggle to improve the analysis speed using the
SMS7621.
I tried it in the PFD Analysis circuit and found it was orders of
magnitude slower than the 1N5711. I mean really, really slow. It is
unusable.
The 1N5711 has an undesirable undershoot when turning off. In real life,
the SMS7621 probably has much less undershoot, but it is impossible to
use it in LTspice.
Since all we want for that function in the circuit is a fast diode with
no undershoot, I looked for another way to perform the same function. It
turns out a diode-connected BFG198 is perfect. It is fast and has no
undesirable underdshoot when turning off. The model statement is
.model BFG198 NPN(IS=1.8998E-15 ISE=7.1424E-14 ISC=2.0992E-15
+ XTI=3 BF=132.75 BR=11.407 IKF=0.44125 IKR=0.010016 XTB=1.5
+ VAF=15 VAR=4.1613 VJE=0.85909 VJC=0.81533 RE=1.1351 RC=0.27485
+ RB=1.2652 RBM=1.0893 IRB=2.8135E-5 CJE=5.0933E-15 CJC=2.3278E-12
+ XCJC=0.14496 FC=0.92887 NF=0.89608 NR=0.91008 NE=1.3235 NC=1.4602
+ MJE=0.69062 MJC=0.46849 TF=3.5786E-11 TR=1.2466E-9 PTF=0 ITF=0.062059
+ VTF=0.10681 XTF=0.44444 EG=1.11 KF=1E-9 AF=1 MFG=Siemens)
It obviously doesn't have the same forward drop as a schottky, but if all
you need is a fast diode with no undershoot, it works pretty good.
Here is the new PFD Analysis using the BFG198. You can see what a huge
difference it makes in the I(UP) and I(DOWN) waveforms. Watch the wrap in
the model statement at the end.
Version 4
SHEET 1 4472 800
WIRE 96 32 0 32
WIRE 96 48 96 32
WIRE -176 96 -224 96
WIRE 0 96 0 32
WIRE 0 96 -176 96
WIRE 32 96 0 96
WIRE 96 160 96 144
WIRE -576 176 -592 176
WIRE -512 176 -576 176
WIRE 464 176 448 176
WIRE -512 176 -576 176
WIRE 560 176 544 176
WIRE -416 192 -448 192
WIRE -384 192 -416 192
WIRE -176 192 -176 96
WIRE -160 192 -176 192
WIRE -688 208 -736 208
WIRE -512 208 -688 208
WIRE -32 208 -48 208
WIRE -160 224 -176 224
WIRE -384 192 -416 192
WIRE -176 192 -176 96
WIRE -160 192 -176 192
WIRE -688 208 -736 208
WIRE -512 208 -688 208
WIRE -32 208 -48 208
WIRE -160 224 -176 224
WIRE -592 256 -592 176
WIRE 96 256 96 240
WIRE 160 256 96 256
WIRE 448 256 448 176
WIRE 480 256 448 256
WIRE 560 256 560 176
WIRE 560 256 544 256
WIRE 576 256 560 256
WIRE 656 256 640 256
WIRE 672 256 656 256
WIRE 704 256 672 256
WIRE -304 272 -304 256
WIRE -32 272 -32 208
WIRE -32 272 -304 272
WIRE 96 304 96 256
WIRE -32 272 -32 208
WIRE -32 272 -304 272
WIRE 160 320 160 256
WIRE 192 320 160 320
WIRE 288 320 272 320
WIRE 320 320 288 320
WIRE 448 320 448 256
WIRE 448 320 400 320
WIRE 496 320 448 320
WIRE 528 320 496 320
WIRE 160 336 160 320
WIRE 288 336 288 320
WIRE 656 336 656 256
WIRE 656 336 592 336
WIRE -592 352 -592 336
WIRE -416 352 -416 336
WIRE 528 352 496 352
WIRE -416 352 -416 336
WIRE 496 384 496 352
WIRE 96 400 96 384
WIRE 96 400 16 400
WIRE -176 416 -176 224
WIRE -176 416 -224 416
WIRE 16 416 16 400
WIRE -176 416 -224 416
WIRE 160 416 160 400
WIRE 288 416 288 400
WIRE 96 464 96 400
WIRE 96 464 80 464
WIRE 496 480 496 464
WIRE -560 496 -592 496
WIRE -512 496 -560 496
WIRE -416 512 -448 512
WIRE -384 512 -416 512
WIRE 16 512 -224 512
WIRE -512 496 -560 496
WIRE -416 512 -448 512
WIRE -384 512 -416 512
WIRE -736 528 -736 208
WIRE -512 528 -736 528
WIRE -736 576 -736 528
WIRE -592 576 -592 496
WIRE -304 592 -304 576
WIRE -192 592 -304 592
WIRE -32 592 -32 272
WIRE -32 592 -192 592
WIRE -736 672 -736 656
WIRE -592 672 -592 656
FLAG -416 256 VCC
FLAG -304 32 VCC
FLAG -384 96 VCC
FLAG -304 352 VCC
FLAG -384 416 VCC
FLAG -416 512 VCO
FLAG -416 192 DATA
FLAG -192 592 CLR
FLAG -416 352 0
FLAG 160 416 0
WIRE -512 528 -736 528
WIRE -736 576 -736 528
WIRE -592 576 -592 496
WIRE -304 592 -304 576
WIRE -192 592 -304 592
WIRE -32 592 -32 272
WIRE -32 592 -192 592
WIRE -736 672 -736 656
WIRE -592 672 -592 656
FLAG -416 256 VCC
FLAG -304 32 VCC
FLAG -384 96 VCC
FLAG -304 352 VCC
FLAG -384 416 VCC
FLAG -416 512 VCO
FLAG -416 192 DATA
FLAG -192 592 CLR
FLAG -416 352 0
FLAG 288 416 0
FLAG -592 672 0
FLAG -736 672 0
FLAG -592 352 0
FLAG -688 208 Ramp
FLAG -576 176 Dly
FLAG -560 496 Ref
FLAG -480 224 0
FLAG -480 160 VCC
FLAG -480 544 0
FLAG -480 480 VCC
FLAG 496 320 Vin
FLAG -736 672 0
FLAG -592 352 0
FLAG -688 208 Ramp
FLAG -576 176 Dly
FLAG -560 496 Ref
FLAG -480 224 0
FLAG -480 160 VCC
FLAG -480 544 0
FLAG -480 480 VCC
FLAG 672 256 VDC
FLAG 496 480 0
FLAG 560 368 0
FLAG 560 304 VCC
SYMBOL Voltage -416 240 R0
WINDOW 3 28 84 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR Value +5V
SYMATTR InstName V1
SYMBOL 74hc74 -304 32 R0
WINDOW 40 20 14 Left 2
SYMATTR SpiceLine2 SPEED=1
WINDOW 3 28 84 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR Value +5V
SYMATTR InstName V1
SYMBOL 74hc74 -304 32 R0
WINDOW 40 20 14 Left 2
SYMATTR InstName U1
SYMATTR SpiceLine VCC=5 TRIPDT=1e-9
SYMATTR SpiceLine VCC=5 TRIPDT=1e-9
SYMBOL 74hc74 -304 352 R0
WINDOW 40 -45 260 Left 2
SYMATTR SpiceLine2 SPEED=1
WINDOW 40 -45 260 Left 2
SYMATTR InstName U2
SYMATTR SpiceLine VCC=5 DELAY=0.1 TRIPDT=1e-9
SYMATTR SpiceLine VCC=5 DELAY=0.1 TRIPDT=1e-9
SYMBOL digital\\74hc00 -112 144 R0
WINDOW 40 -42 152 Left 2
SYMATTR SpiceLine2 SPEED=1
WINDOW 40 -42 152 Left 2
SYMATTR InstName U3
SYMATTR SpiceLine VCC=5 TRIPDT=1e-9
SYMBOL res 112 144 M0
SYMATTR SpiceLine VCC=5 TRIPDT=1e-9
SYMATTR InstName UP
SYMATTR Value 1k
SYMBOL res 112 288 M0
SYMATTR Value 1k
SYMATTR InstName DOWN
SYMATTR Value 1k
SYMBOL cap 144 336 R0
SYMATTR Value 1k
SYMATTR InstName C1
SYMATTR Value 1n
SYMBOL res 288 304 R90
SYMATTR Value 1n
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 1k
SYMBOL cap 272 336 R0
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 1k
SYMATTR InstName C2
SYMATTR Value 500p
SYMBOL cap 544 240 R90
SYMATTR Value 500p
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value 10n
SYMBOL cap 640 240 R90
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value 10n
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C4
SYMATTR Value 1n
SYMBOL res 560 160 R90
WINDOW 3 32 32 VTop 2
SYMATTR InstName C4
SYMATTR Value 1n
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value 1k
SYMBOL res 416 304 R90
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value 1k
WINDOW 3 28 84 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR Value 2.5V
SYMATTR InstName V5
SYMBOL opamps\\1pole 560 336 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR Value 2.5V
SYMATTR InstName V5
WINDOW 123 -119 181 Left 2
SYMATTR Value2 Avol=1Meg GBW=1e6 Slew=1e6
SYMATTR InstName U4
SYMATTR SpiceLine2 en=0 enk=0 in=0 ink=0 Rin=10Meg
SYMBOL Npn 32 48 R0
WINDOW 3 64 76 Left 2
SYMATTR Value BFG198
SYMATTR InstName Q1
SYMBOL Npn 80 416 M0
SYMATTR InstName Q2
SYMATTR Value BFG198
TEXT -376 -64 Left 2 ;'PFD and Op Amp Analysis
TEXT -376 -40 Left 2 !.tran 0 50u 0
TEXT 160 24 Left 2 !.include 74hc.lib
TEXT 160 -48 Left 2 !.options plotwinsize=0
TEXT 280 120 Left 2 ;NOTE: Filter values are for illustrative purposes
TEXT -376 -40 Left 2 !.tran 0 50u 0
TEXT 160 24 Left 2 !.include 74hc.lib
TEXT 160 -48 Left 2 !.options plotwinsize=0
only
TEXT 160 -32 Left 2 !.options nomarch
TEXT 160 0 Left 2 !.ic V(VDC) = 2.5
TEXT 192 448 Left 2 ;Ripple Filter
TEXT 160 0 Left 2 !.ic V(VDC) = 2.5
TEXT -488 648 Left 2 !.model BFG198 NPN(IS=1.8998E-15 ISE=7.1424E-14 ISC=
2.0992E-15 XTI=3 BF=132.75 BR=11.407 IKF=0.44125 IKR=0.010016 XTB=1.5
VAF=15\n+ VAR=4.1613 VJE=0.85909 VJC=0.81533 RE=1.1351 RC=0.27485 RB=
1.2652 RBM=1.0893 IRB=2.8135E-5 CJE=5.0933E-15 CJC=2.3278E-12 \n+ XCJC=
0.14496 FC=0.92887 NF=0.89608 NR=0.91008 NE=1.3235 NC=1.4602 MJE=0.69062
MJC=0.46849 TF=3.5786E-11 TR=1.2466E-9 \n+ PTF=0 ITF=0.062059 VTF=0.10681
XTF=0.44444 EG=1.11 KF=1E-9 AF=1 MFG=Siemens)
Jim Thompson
Jun 30, 2013, 10:46:23 PM6/30/13
to
On Mon, 01 Jul 2013 02:35:09 GMT, John K <sp...@me.not> wrote:
>I have been following the thread "Boost Converter Efficiency
>Improvements" and the struggle to improve the analysis speed using the
>SMS7621.
>
>I tried it in the PFD Analysis circuit and found it was orders of
>magnitude slower than the 1N5711. I mean really, really slow. It is
>unusable.
>
>The 1N5711 has an undesirable undershoot when turning off. In real life,
>the SMS7621 probably has much less undershoot, but it is impossible to
>use it in LTspice.
Why is it "impossible to use it in LTspice"?
>I have been following the thread "Boost Converter Efficiency
>Improvements" and the struggle to improve the analysis speed using the
>SMS7621.
>
>I tried it in the PFD Analysis circuit and found it was orders of
>magnitude slower than the 1N5711. I mean really, really slow. It is
>unusable.
>
>The 1N5711 has an undesirable undershoot when turning off. In real life,
>the SMS7621 probably has much less undershoot, but it is impossible to
>use it in LTspice.
The Spice parameters are in the data sheet...
Table 3. SPICE Model Parameters SMS7621-060:
IS = 2.6459E-8
RS = 12.5
N = 1.01
TT = 1E-11
CJO = 0.13pF
M = 0.35
EG = 0.69
XTI = 2
FC = 0.5
BV = 3
IBV = 1E-5
VJ = 0.51
John Larkin
Jul 1, 2013, 1:44:41 AM7/1/13
to
On Mon, 01 Jul 2013 02:35:09 GMT, John K <sp...@me.not> wrote:
>I have been following the thread "Boost Converter Efficiency
>Improvements" and the struggle to improve the analysis speed using the
>SMS7621.
>
>I tried it in the PFD Analysis circuit and found it was orders of
>magnitude slower than the 1N5711. I mean really, really slow. It is
>unusable.
>
>The 1N5711 has an undesirable undershoot when turning off. In real life,
>the SMS7621 probably has much less undershoot, but it is impossible to
>use it in LTspice.
>
>Since all we want for that function in the circuit is a fast diode with
>no undershoot, I looked for another way to perform the same function. It
>turns out a diode-connected BFG198 is perfect. It is fast and has no
>undesirable underdshoot when turning off. The model statement is
>
>.model BFG198 NPN(IS=1.8998E-15 ISE=7.1424E-14 ISC=2.0992E-15
>+ XTI=3 BF=132.75 BR=11.407 IKF=0.44125 IKR=0.010016 XTB=1.5
>+ VAF=15 VAR=4.1613 VJE=0.85909 VJC=0.81533 RE=1.1351 RC=0.27485
>+ RB=1.2652 RBM=1.0893 IRB=2.8135E-5 CJE=5.0933E-15 CJC=2.3278E-12
>+ XCJC=0.14496 FC=0.92887 NF=0.89608 NR=0.91008 NE=1.3235 NC=1.4602
>+ MJE=0.69062 MJC=0.46849 TF=3.5786E-11 TR=1.2466E-9 PTF=0 ITF=0.062059
>+ VTF=0.10681 XTF=0.44444 EG=1.11 KF=1E-9 AF=1 MFG=Siemens)
>
Anything with that many parameters will need a lot of computing!
>I have been following the thread "Boost Converter Efficiency
>Improvements" and the struggle to improve the analysis speed using the
>SMS7621.
>
>I tried it in the PFD Analysis circuit and found it was orders of
>magnitude slower than the 1N5711. I mean really, really slow. It is
>unusable.
>
>The 1N5711 has an undesirable undershoot when turning off. In real life,
>the SMS7621 probably has much less undershoot, but it is impossible to
>use it in LTspice.
>
>Since all we want for that function in the circuit is a fast diode with
>no undershoot, I looked for another way to perform the same function. It
>turns out a diode-connected BFG198 is perfect. It is fast and has no
>undesirable underdshoot when turning off. The model statement is
>
>.model BFG198 NPN(IS=1.8998E-15 ISE=7.1424E-14 ISC=2.0992E-15
>+ XTI=3 BF=132.75 BR=11.407 IKF=0.44125 IKR=0.010016 XTB=1.5
>+ VAF=15 VAR=4.1613 VJE=0.85909 VJC=0.81533 RE=1.1351 RC=0.27485
>+ RB=1.2652 RBM=1.0893 IRB=2.8135E-5 CJE=5.0933E-15 CJC=2.3278E-12
>+ XCJC=0.14496 FC=0.92887 NF=0.89608 NR=0.91008 NE=1.3235 NC=1.4602
>+ MJE=0.69062 MJC=0.46849 TF=3.5786E-11 TR=1.2466E-9 PTF=0 ITF=0.062059
>+ VTF=0.10681 XTF=0.44444 EG=1.11 KF=1E-9 AF=1 MFG=Siemens)
>
>It obviously doesn't have the same forward drop as a schottky, but if all
>you need is a fast diode with no undershoot, it works pretty good.
.model DID D(Vfwd=0.3 Ron=10 Roff=1M)
or something like that. You could add the 0.2 pF shunt capacitance of the 7621,
but it probably doesn't matter.
I don't think we Spiced the phase detector that I posted. Just did a Bode plot
of the loop.
Jim Thompson
Jul 1, 2013, 2:07:21 AM7/1/13
to
On Sun, 30 Jun 2013 22:44:41 -0700, John Larkin
<jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>On Mon, 01 Jul 2013 02:35:09 GMT, John K <sp...@me.not> wrote:
>
>>I have been following the thread "Boost Converter Efficiency
>>Improvements" and the struggle to improve the analysis speed using the
>>SMS7621.
>>
>>I tried it in the PFD Analysis circuit and found it was orders of
>>magnitude slower than the 1N5711. I mean really, really slow. It is
>>unusable.
>>
>>The 1N5711 has an undesirable undershoot when turning off. In real life,
>>the SMS7621 probably has much less undershoot, but it is impossible to
>>use it in LTspice.
>>
>>Since all we want for that function in the circuit is a fast diode with
>>no undershoot, I looked for another way to perform the same function. It
>>turns out a diode-connected BFG198 is perfect. It is fast and has no
>>undesirable underdshoot when turning off. The model statement is
>>
>>.model BFG198 NPN(IS=1.8998E-15 ISE=7.1424E-14 ISC=2.0992E-15
>>+ XTI=3 BF=132.75 BR=11.407 IKF=0.44125 IKR=0.010016 XTB=1.5
>>+ VAF=15 VAR=4.1613 VJE=0.85909 VJC=0.81533 RE=1.1351 RC=0.27485
>>+ RB=1.2652 RBM=1.0893 IRB=2.8135E-5 CJE=5.0933E-15 CJC=2.3278E-12
>>+ XCJC=0.14496 FC=0.92887 NF=0.89608 NR=0.91008 NE=1.3235 NC=1.4602
>>+ MJE=0.69062 MJC=0.46849 TF=3.5786E-11 TR=1.2466E-9 PTF=0 ITF=0.062059
>>+ VTF=0.10681 XTF=0.44444 EG=1.11 KF=1E-9 AF=1 MFG=Siemens)
>>
>
>Anything with that many parameters will need a lot of computing!
Nonsense. That's no more parameters than typically in a BJT.
<jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>On Mon, 01 Jul 2013 02:35:09 GMT, John K <sp...@me.not> wrote:
>
>>I have been following the thread "Boost Converter Efficiency
>>Improvements" and the struggle to improve the analysis speed using the
>>SMS7621.
>>
>>I tried it in the PFD Analysis circuit and found it was orders of
>>magnitude slower than the 1N5711. I mean really, really slow. It is
>>unusable.
>>
>>The 1N5711 has an undesirable undershoot when turning off. In real life,
>>the SMS7621 probably has much less undershoot, but it is impossible to
>>use it in LTspice.
>>
>>Since all we want for that function in the circuit is a fast diode with
>>no undershoot, I looked for another way to perform the same function. It
>>turns out a diode-connected BFG198 is perfect. It is fast and has no
>>undesirable underdshoot when turning off. The model statement is
>>
>>.model BFG198 NPN(IS=1.8998E-15 ISE=7.1424E-14 ISC=2.0992E-15
>>+ XTI=3 BF=132.75 BR=11.407 IKF=0.44125 IKR=0.010016 XTB=1.5
>>+ VAF=15 VAR=4.1613 VJE=0.85909 VJC=0.81533 RE=1.1351 RC=0.27485
>>+ RB=1.2652 RBM=1.0893 IRB=2.8135E-5 CJE=5.0933E-15 CJC=2.3278E-12
>>+ XCJC=0.14496 FC=0.92887 NF=0.89608 NR=0.91008 NE=1.3235 NC=1.4602
>>+ MJE=0.69062 MJC=0.46849 TF=3.5786E-11 TR=1.2466E-9 PTF=0 ITF=0.062059
>>+ VTF=0.10681 XTF=0.44444 EG=1.11 KF=1E-9 AF=1 MFG=Siemens)
>>
>
>Anything with that many parameters will need a lot of computing!
>
>>It obviously doesn't have the same forward drop as a schottky, but if all
>>you need is a fast diode with no undershoot, it works pretty good.
>
>A simple diode model would work as well, and it would be fast:
>
>.model DID D(Vfwd=0.3 Ron=10 Roff=1M)
>
>or something like that. You could add the 0.2 pF shunt capacitance of the 7621,
>but it probably doesn't matter.
>
>I don't think we Spiced the phase detector that I posted. Just did a Bode plot
>of the loop.
Bill Sloman
Jul 1, 2013, 2:13:45 AM7/1/13
to
On Monday, 1 July 2013 15:44:41 UTC+10, John Larkin wrote:
> On Mon, 01 Jul 2013 02:35:09 GMT, John K <sp...@me.not> wrote:
>
> >I have been following the thread "Boost Converter Efficiency
> >Improvements" and the struggle to improve the analysis speed using the
> >SMS7621.
> >
> >I tried it in the PFD Analysis circuit and found it was orders of
> >magnitude slower than the 1N5711. I mean really, really slow. It is
> >unusable.
> >
> >The 1N5711 has an undesirable undershoot when turning off. In real life,
> >the SMS7621 probably has much less undershoot, but it is impossible to
> >use it in LTspice.
> >
> >Since all we want for that function in the circuit is a fast diode with
> >no undershoot, I looked for another way to perform the same function. It
> >turns out a diode-connected BFG198 is perfect. It is fast and has no
> >undesirable undershoot when turning off. The model statement is
> On Mon, 01 Jul 2013 02:35:09 GMT, John K <sp...@me.not> wrote:
>
> >I have been following the thread "Boost Converter Efficiency
> >Improvements" and the struggle to improve the analysis speed using the
> >SMS7621.
> >
> >I tried it in the PFD Analysis circuit and found it was orders of
> >magnitude slower than the 1N5711. I mean really, really slow. It is
> >unusable.
> >
> >The 1N5711 has an undesirable undershoot when turning off. In real life,
> >the SMS7621 probably has much less undershoot, but it is impossible to
> >use it in LTspice.
> >
> >Since all we want for that function in the circuit is a fast diode with
> >no undershoot, I looked for another way to perform the same function. It
> >turns out a diode-connected BFG198 is perfect. It is fast and has no
> >
> >.model BFG198 NPN(IS=1.8998E-15 ISE=7.1424E-14 ISC=2.0992E-15
> >+ XTI=3 BF=132.75 BR=11.407 IKF=0.44125 IKR=0.010016 XTB=1.5
> >+ VAF=15 VAR=4.1613 VJE=0.85909 VJC=0.81533 RE=1.1351 RC=0.27485
> >+ RB=1.2652 RBM=1.0893 IRB=2.8135E-5 CJE=5.0933E-15 CJC=2.3278E-12
> >+ XCJC=0.14496 FC=0.92887 NF=0.89608 NR=0.91008 NE=1.3235 NC=1.4602
> >+ MJE=0.69062 MJC=0.46849 TF=3.5786E-11 TR=1.2466E-9 PTF=0 ITF=0.062059
> >+ VTF=0.10681 XTF=0.44444 EG=1.11 KF=1E-9 AF=1 MFG=Siemens)
>
> Anything with that many parameters will need a lot of computing!
That does not follow. It's the standard Gummell-Poon model, with the same number of parameters as any other transistor.
> >.model BFG198 NPN(IS=1.8998E-15 ISE=7.1424E-14 ISC=2.0992E-15
> >+ XTI=3 BF=132.75 BR=11.407 IKF=0.44125 IKR=0.010016 XTB=1.5
> >+ VAF=15 VAR=4.1613 VJE=0.85909 VJC=0.81533 RE=1.1351 RC=0.27485
> >+ RB=1.2652 RBM=1.0893 IRB=2.8135E-5 CJE=5.0933E-15 CJC=2.3278E-12
> >+ XCJC=0.14496 FC=0.92887 NF=0.89608 NR=0.91008 NE=1.3235 NC=1.4602
> >+ MJE=0.69062 MJC=0.46849 TF=3.5786E-11 TR=1.2466E-9 PTF=0 ITF=0.062059
> >+ VTF=0.10681 XTF=0.44444 EG=1.11 KF=1E-9 AF=1 MFG=Siemens)
>
> Anything with that many parameters will need a lot of computing!
It is an 8GHz device, and that could slow down your simulation by imposing a small step size, but it's not the number of parameters involved that would create that problem, but their values. Since it is being used as a diode, this probably wouldn't be a issue.
> >It obviously doesn't have the same forward drop as a schottky, but if all
> >you need is a fast diode with no undershoot, it works pretty good.
John K
Jul 1, 2013, 5:35:38 AM7/1/13
to
John Larkin <jjla...@highNOTlandTHIStechnologyPART.com> wrote:
> On Mon, 01 Jul 2013 02:35:09 GMT, John K <sp...@me.not> wrote:
>>.model BFG198 NPN(IS=1.8998E-15 ISE=7.1424E-14 ISC=2.0992E-15
>>+ XTI=3 BF=132.75 BR=11.407 IKF=0.44125 IKR=0.010016 XTB=1.5
>>+ VAF=15 VAR=4.1613 VJE=0.85909 VJC=0.81533 RE=1.1351 RC=0.27485
>>+ RB=1.2652 RBM=1.0893 IRB=2.8135E-5 CJE=5.0933E-15 CJC=2.3278E-12
>>+ XCJC=0.14496 FC=0.92887 NF=0.89608 NR=0.91008 NE=1.3235 NC=1.4602
>>+ MJE=0.69062 MJC=0.46849 TF=3.5786E-11 TR=1.2466E-9 PTF=0
>>ITF=0.062059 + VTF=0.10681 XTF=0.44444 EG=1.11 KF=1E-9 AF=1
>>MFG=Siemens)
> Anything with that many parameters will need a lot of computing!
> A simple diode model would work as well, and it would be fast:
>
> .model DID D(Vfwd=0.3 Ron=10 Roff=1M)
>
> or something like that. You could add the 0.2 pF shunt capacitance of
> the 7621, but it probably doesn't matter.
work fine. That is a lot easier than playing with a BFG198. It doesn't
matter what is performing that function, as long as it doesn't undershoot
at turnoff like the 1N5711. That messes up the waveforms and makes it
harder to understand what is going on.
The purpose for the analysis is to show how the PFD and op amp work. It
clearly shows that increasing the NAND delay has little or no effect on
the op amp input as you claimed.
> I don't think we Spiced the phase detector that I posted. Just did a
> Bode plot of the loop.
cannot do a Bode plot of the entire loop with the PFD using AC Analysis.
You described the phase detector verbally and the changes you had to
make. The PFD I posted is the standard Dual-D with NAND feedback. It
should operate exactly the same as yours, if it is a standard
frequency/phase detector.
You posted the op amp and feedback components.
The PFD analysis I posted is exactly the same configuration. Op amp +
goes to a reference voltage. Loop filter goes to op amp -.
The UP and DOWN logic levels go through diode and series resistor to op
amp -.
Exactly the same configuration, except you have no ripple filter at the
input of the op amp.
JK
John Larkin
Jul 1, 2013, 11:43:14 AM7/1/13
to
changed. Or give up simulating it.
>
>>
>>>It obviously doesn't have the same forward drop as a schottky, but if all
>>>you need is a fast diode with no undershoot, it works pretty good.
>>
>>A simple diode model would work as well, and it would be fast:
>>
>>.model DID D(Vfwd=0.3 Ron=10 Roff=1M)
>
>Simplistic will zing you in the ass every time.
other situations, like the boost converter soft-start I posted, what you're
after is modeling loop dynamics. A simple diode model, or an ideal diode model,
can work fine *IF* you understand what's going on. Nobody sane is going to model
every parasitic of every part.
>
>>
>>or something like that. You could add the 0.2 pF shunt capacitance of the 7621,
>>but it probably doesn't matter.
>>
>>I don't think we Spiced the phase detector that I posted. Just did a Bode plot
>>of the loop.
>
>And then you whined when a simulation was taking forever in LTspice??
dynamics. If the loop is linear enough, like our FPGA PLL, it then makes sense
to use 10 minutes of classic Bode analysis. Or if it's too nonlinear, like my
boost converter, breadboard.
The third choice, the one I generally use, is to just design the board the way
that ought to work, lay it out as rev A, and let manufacturing build one. Leave
in enough hooks to get out of trouble. IC designers can't do that, which
distorts your perspective. The other thing that distorts your perspective is
that you're a mean-spirited, paranoid, vain old git.
On a board with 800 parts, 11 power supplies, ARM CPU, a couple of FPGAs,
thermal issues, transmission lines, 8-layer PCB to lay out and check, all sorts
of stuff, we can't spend weeks simulating every subcircuit. Most of our stuff
works rev A, first time, with little or no simulation. If we have to tweak a
couple of parts values, no big deal: we save tons of time by working this way.
For example: we use a lot of resistor and capacitor networks to save space and
production costs, but they lock you into fixed ratios. At design reviews, one
thing we do is look for places to use networks, and places where networks could
create hazards.
Have I mentioned lately that you're an idiot?
John Larkin
Jul 1, 2013, 11:59:16 AM7/1/13
to
On Mon, 01 Jul 2013 09:35:38 GMT, John K <sp...@me.not> wrote:
>
>John Larkin <jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>
>> On Mon, 01 Jul 2013 02:35:09 GMT, John K <sp...@me.not> wrote:
>
>>>.model BFG198 NPN(IS=1.8998E-15 ISE=7.1424E-14 ISC=2.0992E-15
>>>+ XTI=3 BF=132.75 BR=11.407 IKF=0.44125 IKR=0.010016 XTB=1.5
>>>+ VAF=15 VAR=4.1613 VJE=0.85909 VJC=0.81533 RE=1.1351 RC=0.27485
>>>+ RB=1.2652 RBM=1.0893 IRB=2.8135E-5 CJE=5.0933E-15 CJC=2.3278E-12
>>>+ XCJC=0.14496 FC=0.92887 NF=0.89608 NR=0.91008 NE=1.3235 NC=1.4602
>>>+ MJE=0.69062 MJC=0.46849 TF=3.5786E-11 TR=1.2466E-9 PTF=0
>>>ITF=0.062059 + VTF=0.10681 XTF=0.44444 EG=1.11 KF=1E-9 AF=1
>>>MFG=Siemens)
>
>> Anything with that many parameters will need a lot of computing!
>
>Doesn't seem to slow it down at all.
>
>> A simple diode model would work as well, and it would be fast:
>>
>> .model DID D(Vfwd=0.3 Ron=10 Roff=1M)
>>
>> or something like that. You could add the 0.2 pF shunt capacitance of
>> the 7621, but it probably doesn't matter.
>
>It turns out just adding a diode without selecting any model seems to
>work fine. That is a lot easier than playing with a BFG198. It doesn't
>matter what is performing that function, as long as it doesn't undershoot
>at turnoff like the 1N5711. That messes up the waveforms and makes it
>harder to understand what is going on.
5711 is a schottky, so the undershoot is capacitance. I like the SMS7621 because
>
>John Larkin <jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>
>> On Mon, 01 Jul 2013 02:35:09 GMT, John K <sp...@me.not> wrote:
>
>>>.model BFG198 NPN(IS=1.8998E-15 ISE=7.1424E-14 ISC=2.0992E-15
>>>+ XTI=3 BF=132.75 BR=11.407 IKF=0.44125 IKR=0.010016 XTB=1.5
>>>+ VAF=15 VAR=4.1613 VJE=0.85909 VJC=0.81533 RE=1.1351 RC=0.27485
>>>+ RB=1.2652 RBM=1.0893 IRB=2.8135E-5 CJE=5.0933E-15 CJC=2.3278E-12
>>>+ XCJC=0.14496 FC=0.92887 NF=0.89608 NR=0.91008 NE=1.3235 NC=1.4602
>>>+ MJE=0.69062 MJC=0.46849 TF=3.5786E-11 TR=1.2466E-9 PTF=0
>>>ITF=0.062059 + VTF=0.10681 XTF=0.44444 EG=1.11 KF=1E-9 AF=1
>>>MFG=Siemens)
>
>> Anything with that many parameters will need a lot of computing!
>
>Doesn't seem to slow it down at all.
>
>> A simple diode model would work as well, and it would be fast:
>>
>> .model DID D(Vfwd=0.3 Ron=10 Roff=1M)
>>
>> or something like that. You could add the 0.2 pF shunt capacitance of
>> the 7621, but it probably doesn't matter.
>
>It turns out just adding a diode without selecting any model seems to
>work fine. That is a lot easier than playing with a BFG198. It doesn't
>matter what is performing that function, as long as it doesn't undershoot
>at turnoff like the 1N5711. That messes up the waveforms and makes it
>harder to understand what is going on.
it's only about 0.25 pF. The tau against 1.3K is only a few hundred picoseconds.
>
>The purpose for the analysis is to show how the PFD and op amp work. It
>clearly shows that increasing the NAND delay has little or no effect on
>the op amp input as you claimed.
>
>> I don't think we Spiced the phase detector that I posted. Just did a
>> Bode plot of the loop.
>
>You did a Bode plot of the op amp with feedback. That is trivial. You
>cannot do a Bode plot of the entire loop with the PFD using AC Analysis.
The ECL bangbang PLL, the one we did for NIF, also works great. It has a ps or
so of RMS jitter and temperature drift below 1 ps/degC. It was designed with
Bode plots, never simulated.
>
>You described the phase detector verbally and the changes you had to
>make. The PFD I posted is the standard Dual-D with NAND feedback. It
>should operate exactly the same as yours, if it is a standard
>frequency/phase detector.
did the diode-amplifier thing I posted, pencil on vellum. I think it was my
suggestion to go with hard outputs, instead of a charge pump, when Rob started
describing the risks of using FPGA tri-states to make a charge pump. I never
liked charge pumps anyhow.
The other zero-deadband loop that would be easy is to make a hybrid, a circuit
that's a frequency error detector out of lock and an XOR close in, sort of like
the AD9901. Their logic diagram is on their data sheet. It looks like hell when
it's out of lock, but it works. The loop filter could be a single RC into the
VCO.
FPGAs can use counters and stuff to do the coarse lock, too.
Jim Thompson
Jul 1, 2013, 12:13:03 PM7/1/13
to
On Mon, 01 Jul 2013 08:43:14 -0700, John Larkin
Neeerp! You're the moron. BJT (or diode) models don't slow
simulations... Berkeley-based simulators are designed specifically to
handle such models. What slowed your simulation was likely a poorly
constructed behavioral model. My guess would be the use of the (hard)
LIMIT function... I see that a lot in amateurish modeling efforts.
And I don't know how many times I've seen poorly constructed
behavioral models (or "ideal" diodes :) hide defects in a design.
>
>>
>>>
>>>>It obviously doesn't have the same forward drop as a schottky, but if all
>>>>you need is a fast diode with no undershoot, it works pretty good.
>>>
>>>A simple diode model would work as well, and it would be fast:
>>>
>>>.model DID D(Vfwd=0.3 Ron=10 Roff=1M)
>>
>>Simplistic will zing you in the ass every time.
>
>Idiot. In a basic circuit like the phase detector amp that I posted, and in many
>other situations, like the boost converter soft-start I posted, what you're
>after is modeling loop dynamics. A simple diode model, or an ideal diode model,
>can work fine *IF* you understand what's going on. Nobody sane is going to model
>every parasitic of every part.
You just have to be so-o-o-o technical and name-call and name-call.
You're clearly an amateur when it comes to understanding and using a
simulator.
>
>>
>>>
>>>or something like that. You could add the 0.2 pF shunt capacitance of the 7621,
>>>but it probably doesn't matter.
>>>
>>>I don't think we Spiced the phase detector that I posted. Just did a Bode plot
>>>of the loop.
It shows... or more accurately, as JK showed you up ;-)
>>
>>And then you whined when a simulation was taking forever in LTspice??
>
>A simulation that takes a day, or a week, per run isn't useful in iterating loop
>dynamics. If the loop is linear enough, like our FPGA PLL, it then makes sense
>to use 10 minutes of classic Bode analysis. Or if it's too nonlinear, like my
>boost converter, breadboard.
I did a whole chip simulation last night... 155 devices (MOS),
admittedly a small chip as my chip designs go, but absolutely no
behavioral devices, video DC restore and (UTC) data recovery, actual
video signal... took about 5 minutes.
BTW: "Iterating" is hacker's terminology... can't calculate/design,
then "iterate" ;-)
>
>The third choice, the one I generally use, is to just design the board the way
>that ought to work, lay it out as rev A, and let manufacturing build one. Leave
>in enough hooks to get out of trouble. IC designers can't do that, which
>distorts your perspective. The other thing that distorts your perspective is
>that you're a mean-spirited, paranoid, vain old git.
>
>On a board with 800 parts, 11 power supplies, ARM CPU, a couple of FPGAs,
>thermal issues, transmission lines, 8-layer PCB to lay out and check, all sorts
>of stuff, we can't spend weeks simulating every subcircuit. Most of our stuff
>works rev A, first time, with little or no simulation. If we have to tweak a
>couple of parts values, no big deal: we save tons of time by working this way.
>
>For example: we use a lot of resistor and capacitor networks to save space and
>production costs, but they lock you into fixed ratios. At design reviews, one
>thing we do is look for places to use networks, and places where networks could
>create hazards.
>
>Have I mentioned lately that you're an idiot?
You never fail to. But you're so wonderful... you just can't avoid
demonstrating your manic-depressive (and associated
superiority-inferiority) complexes over and over and over...
Designed anything properly recently... or do you just cover your
failures with supposed alternate "analyses"... and "iteration" ?>:-}
simulations... Berkeley-based simulators are designed specifically to
handle such models. What slowed your simulation was likely a poorly
constructed behavioral model. My guess would be the use of the (hard)
LIMIT function... I see that a lot in amateurish modeling efforts.
And I don't know how many times I've seen poorly constructed
behavioral models (or "ideal" diodes :) hide defects in a design.
>
>>
>>>
>>>>It obviously doesn't have the same forward drop as a schottky, but if all
>>>>you need is a fast diode with no undershoot, it works pretty good.
>>>
>>>A simple diode model would work as well, and it would be fast:
>>>
>>>.model DID D(Vfwd=0.3 Ron=10 Roff=1M)
>>
>>Simplistic will zing you in the ass every time.
>
>Idiot. In a basic circuit like the phase detector amp that I posted, and in many
>other situations, like the boost converter soft-start I posted, what you're
>after is modeling loop dynamics. A simple diode model, or an ideal diode model,
>can work fine *IF* you understand what's going on. Nobody sane is going to model
>every parasitic of every part.
You're clearly an amateur when it comes to understanding and using a
simulator.
>
>>
>>>
>>>or something like that. You could add the 0.2 pF shunt capacitance of the 7621,
>>>but it probably doesn't matter.
>>>
>>>I don't think we Spiced the phase detector that I posted. Just did a Bode plot
>>>of the loop.
>>
>>And then you whined when a simulation was taking forever in LTspice??
>
>A simulation that takes a day, or a week, per run isn't useful in iterating loop
>dynamics. If the loop is linear enough, like our FPGA PLL, it then makes sense
>to use 10 minutes of classic Bode analysis. Or if it's too nonlinear, like my
>boost converter, breadboard.
admittedly a small chip as my chip designs go, but absolutely no
behavioral devices, video DC restore and (UTC) data recovery, actual
video signal... took about 5 minutes.
BTW: "Iterating" is hacker's terminology... can't calculate/design,
then "iterate" ;-)
>
>The third choice, the one I generally use, is to just design the board the way
>that ought to work, lay it out as rev A, and let manufacturing build one. Leave
>in enough hooks to get out of trouble. IC designers can't do that, which
>distorts your perspective. The other thing that distorts your perspective is
>that you're a mean-spirited, paranoid, vain old git.
>
>On a board with 800 parts, 11 power supplies, ARM CPU, a couple of FPGAs,
>thermal issues, transmission lines, 8-layer PCB to lay out and check, all sorts
>of stuff, we can't spend weeks simulating every subcircuit. Most of our stuff
>works rev A, first time, with little or no simulation. If we have to tweak a
>couple of parts values, no big deal: we save tons of time by working this way.
>
>For example: we use a lot of resistor and capacitor networks to save space and
>production costs, but they lock you into fixed ratios. At design reviews, one
>thing we do is look for places to use networks, and places where networks could
>create hazards.
>
>Have I mentioned lately that you're an idiot?
demonstrating your manic-depressive (and associated
superiority-inferiority) complexes over and over and over...
Designed anything properly recently... or do you just cover your
failures with supposed alternate "analyses"... and "iteration" ?>:-}
John Larkin
Jul 1, 2013, 12:36:27 PM7/1/13
to
On Mon, 01 Jul 2013 09:13:03 -0700, Jim Thompson
I never said that they do; John K did, about the SMS7621. Argue with him.
In other cases, I've had transistor-level models seriously slow down a sim,
enough to be inconvenient.
What slowed your simulation was likely a poorly
>constructed behavioral model. My guess would be the use of the (hard)
>LIMIT function... I see that a lot in amateurish modeling efforts.
>
>And I don't know how many times I've seen poorly constructed
>behavioral models (or "ideal" diodes :) hide defects in a design.
If someone doesn't undestand a circuit, and *has* to simulate it, then every
device model must be fully accurate; good luck with that. If you understand a
circuit and, say, just want to tune loop transient response, simplifications are
fine and save time.
>
>>
>>>
>>>>
>>>>>It obviously doesn't have the same forward drop as a schottky, but if all
>>>>>you need is a fast diode with no undershoot, it works pretty good.
>>>>
>>>>A simple diode model would work as well, and it would be fast:
>>>>
>>>>.model DID D(Vfwd=0.3 Ron=10 Roff=1M)
>>>
>>>Simplistic will zing you in the ass every time.
>>
>>Idiot. In a basic circuit like the phase detector amp that I posted, and in many
>>other situations, like the boost converter soft-start I posted, what you're
>>after is modeling loop dynamics. A simple diode model, or an ideal diode model,
>>can work fine *IF* you understand what's going on. Nobody sane is going to model
>>every parasitic of every part.
>
>You just have to be so-o-o-o technical and name-call and name-call.
>You're clearly an amateur when it comes to understanding and using a
>simulator.
I don't simulate a lot: I design. It's a different process. Since I don't live
by simulation, I'm not as familiar with Spice as people who simulate constantly.
>
>>
>>>
>>>>
>>>>or something like that. You could add the 0.2 pF shunt capacitance of the 7621,
>>>>but it probably doesn't matter.
>>>>
>>>>I don't think we Spiced the phase detector that I posted. Just did a Bode plot
>>>>of the loop.
>
>It shows... or more accurately, as JK showed you up ;-)
We've sold megabucks of gear with our PLLs inside. They all work.
You can't help turning technical posts personal. You can't help, period.
>
>Designed anything properly recently...
Just recently?
24-channel LVDT/Synchro acquisition/simulation board.
Several multichannel ARBs
Several laser drivers, some picoseconds, some hundreds of amps
VME digital i/o board
Parts of a couple of PCI Express controllers.
Bunch of picosecond timing and fiberoptic things
Controller and several i/o boxes for an EUV lithography source.
Another NMR gradient driver
Another magnetic field mapping system
All stuff that you couldn't do.
or do you just cover your
>failures with supposed alternate "analyses"... and "iteration" ?>:-}
They all work. People are buying them. No technical failures, except that not
everything always sells.
In my career, over a thousand PCB designs, I've only done a couple that were
technical "failures." They could have been fixed, but the customer went away
first. One was a tugboat alarm system that had intermittent CMOS latchup
problems, before I knew about CMOS latchup. One other was a microstepping
driver, problems with the H-bridge power stage caused us to miss the boat. Both
decades ago. But there's no serious money in either business, so no loss to
anything but pride.
In other cases, I've had transistor-level models seriously slow down a sim,
enough to be inconvenient.
What slowed your simulation was likely a poorly
>constructed behavioral model. My guess would be the use of the (hard)
>LIMIT function... I see that a lot in amateurish modeling efforts.
>
>And I don't know how many times I've seen poorly constructed
>behavioral models (or "ideal" diodes :) hide defects in a design.
device model must be fully accurate; good luck with that. If you understand a
circuit and, say, just want to tune loop transient response, simplifications are
fine and save time.
>
>>
>>>
>>>>
>>>>>It obviously doesn't have the same forward drop as a schottky, but if all
>>>>>you need is a fast diode with no undershoot, it works pretty good.
>>>>
>>>>A simple diode model would work as well, and it would be fast:
>>>>
>>>>.model DID D(Vfwd=0.3 Ron=10 Roff=1M)
>>>
>>>Simplistic will zing you in the ass every time.
>>
>>Idiot. In a basic circuit like the phase detector amp that I posted, and in many
>>other situations, like the boost converter soft-start I posted, what you're
>>after is modeling loop dynamics. A simple diode model, or an ideal diode model,
>>can work fine *IF* you understand what's going on. Nobody sane is going to model
>>every parasitic of every part.
>
>You just have to be so-o-o-o technical and name-call and name-call.
>You're clearly an amateur when it comes to understanding and using a
>simulator.
by simulation, I'm not as familiar with Spice as people who simulate constantly.
>
>>
>>>
>>>>
>>>>or something like that. You could add the 0.2 pF shunt capacitance of the 7621,
>>>>but it probably doesn't matter.
>>>>
>>>>I don't think we Spiced the phase detector that I posted. Just did a Bode plot
>>>>of the loop.
>
>It shows... or more accurately, as JK showed you up ;-)
>
>Designed anything properly recently...
Just recently?
24-channel LVDT/Synchro acquisition/simulation board.
Several multichannel ARBs
Several laser drivers, some picoseconds, some hundreds of amps
VME digital i/o board
Parts of a couple of PCI Express controllers.
Bunch of picosecond timing and fiberoptic things
Controller and several i/o boxes for an EUV lithography source.
Another NMR gradient driver
Another magnetic field mapping system
All stuff that you couldn't do.
or do you just cover your
>failures with supposed alternate "analyses"... and "iteration" ?>:-}
everything always sells.
In my career, over a thousand PCB designs, I've only done a couple that were
technical "failures." They could have been fixed, but the customer went away
first. One was a tugboat alarm system that had intermittent CMOS latchup
problems, before I knew about CMOS latchup. One other was a microstepping
driver, problems with the H-bridge power stage caused us to miss the boat. Both
decades ago. But there's no serious money in either business, so no loss to
anything but pride.
Jim Thompson
Jul 1, 2013, 1:02:15 PM7/1/13
to
On Mon, 01 Jul 2013 09:36:27 -0700, John Larkin
I don't know how many times I've said, I usually design by doodling on
paper, then verifying by simulating all process corners.
But I guess your superiority complex says that only you design and
everyone else is helpless without a simulation?
[snip]
in concrete... simulate all "construction" possibilities.
As an amateur in simulation you ought to be careful criticizing what
you don't understand.
[snip]
but didn't move the right variable?
[snip]
terms like "moron" and "Have I mentioned lately that you're an idiot?"
in response to my technical issues.
>>
>>Designed anything properly recently...
>
>
>Just recently?
>
>24-channel LVDT/Synchro acquisition/simulation board.
>
>Several multichannel ARBs
>
>Several laser drivers, some picoseconds, some hundreds of amps
>
>VME digital i/o board
>
>Parts of a couple of PCI Express controllers.
>
>Bunch of picosecond timing and fiberoptic things
>
>Controller and several i/o boxes for an EUV lithography source.
>
>Another NMR gradient driver
>
>Another magnetic field mapping system
>
>All stuff that you couldn't do.
>
Anything you "built" that has ECL/PECL or LVDS in it... I probably
designed the chip that you are using. And who knows what other
chips... I've designed so many I lose track of all the functions I've
done.
>
>
>or do you just cover your
>>failures with supposed alternate "analyses"... and "iteration" ?>:-}
>
>They all work. People are buying them. No technical failures, except that not
>everything always sells.
>
>In my career, over a thousand PCB designs, I've only done a couple that were
>technical "failures." They could have been fixed, but the customer went away
>first. One was a tugboat alarm system that had intermittent CMOS latchup
>problems, before I knew about CMOS latchup. One other was a microstepping
>driver, problems with the H-bridge power stage caused us to miss the boat. Both
>decades ago. But there's no serious money in either business, so no loss to
>anything but pride.
Whoopee doooo >:-}
But you're so wonderful... you just can't avoid
demonstrating your manic-depressive (and associated
superiority-inferiority) complexes over and over and over...
<jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>On Mon, 01 Jul 2013 09:13:03 -0700, Jim Thompson
><To-Email-Use-Th...@On-My-Web-Site.com> wrote:
>
>>On Mon, 01 Jul 2013 08:43:14 -0700, John Larkin
>><jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>>
>>>On Sun, 30 Jun 2013 23:07:21 -0700, Jim Thompson
>>><To-Email-Use-Th...@On-My-Web-Site.com> wrote:
>>>
>>>>On Sun, 30 Jun 2013 22:44:41 -0700, John Larkin
>>>><jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>>>>
[snip]
>On Mon, 01 Jul 2013 09:13:03 -0700, Jim Thompson
><To-Email-Use-Th...@On-My-Web-Site.com> wrote:
>
>>On Mon, 01 Jul 2013 08:43:14 -0700, John Larkin
>><jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>>
>>>On Sun, 30 Jun 2013 23:07:21 -0700, Jim Thompson
>>><To-Email-Use-Th...@On-My-Web-Site.com> wrote:
>>>
>>>>On Sun, 30 Jun 2013 22:44:41 -0700, John Larkin
>>>><jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>>>>
paper, then verifying by simulating all process corners.
But I guess your superiority complex says that only you design and
everyone else is helpless without a simulation?
[snip]
>>
>>You just have to be so-o-o-o technical and name-call and name-call.
>>You're clearly an amateur when it comes to understanding and using a
>>simulator.
>
>I don't simulate a lot: I design. It's a different process. Since I don't live
>by simulation, I'm not as familiar with Spice as people who simulate constantly.
>
Those of us who can't go back a tweak a board... silicon is like cast
>>You just have to be so-o-o-o technical and name-call and name-call.
>>You're clearly an amateur when it comes to understanding and using a
>>simulator.
>
>I don't simulate a lot: I design. It's a different process. Since I don't live
>by simulation, I'm not as familiar with Spice as people who simulate constantly.
>
in concrete... simulate all "construction" possibilities.
As an amateur in simulation you ought to be careful criticizing what
you don't understand.
[snip]
>>>>>
>>>>>I don't think we Spiced the phase detector that I posted. Just did a Bode plot
>>>>>of the loop.
>>
>>It shows... or more accurately, as JK showed you up ;-)
>
>We've sold megabucks of gear with our PLLs inside. They all work.
>
Do they work as well as they could, or only as good as you iterated
>>>>>I don't think we Spiced the phase detector that I posted. Just did a Bode plot
>>>>>of the loop.
>>
>>It shows... or more accurately, as JK showed you up ;-)
>
>We've sold megabucks of gear with our PLLs inside. They all work.
>
but didn't move the right variable?
[snip]
>>
>>BTW: "Iterating" is hacker's terminology... can't calculate/design,
>>then "iterate" ;-)
>>
[snip]
>>BTW: "Iterating" is hacker's terminology... can't calculate/design,
>>then "iterate" ;-)
>>
>>>
>>>Have I mentioned lately that you're an idiot?
>>
>>You never fail to. But you're so wonderful... you just can't avoid
>>demonstrating your manic-depressive (and associated
>>superiority-inferiority) complexes over and over and over...
>
>You can't help turning technical posts personal. You can't help, period.
Do you have any idea how ridiculous that statement sounds? You used
>>>Have I mentioned lately that you're an idiot?
>>
>>You never fail to. But you're so wonderful... you just can't avoid
>>demonstrating your manic-depressive (and associated
>>superiority-inferiority) complexes over and over and over...
>
>You can't help turning technical posts personal. You can't help, period.
terms like "moron" and "Have I mentioned lately that you're an idiot?"
in response to my technical issues.
>>
>>Designed anything properly recently...
>
>
>Just recently?
>
>24-channel LVDT/Synchro acquisition/simulation board.
>
>Several multichannel ARBs
>
>Several laser drivers, some picoseconds, some hundreds of amps
>
>VME digital i/o board
>
>Parts of a couple of PCI Express controllers.
>
>Bunch of picosecond timing and fiberoptic things
>
>Controller and several i/o boxes for an EUV lithography source.
>
>Another NMR gradient driver
>
>Another magnetic field mapping system
>
>All stuff that you couldn't do.
>
designed the chip that you are using. And who knows what other
chips... I've designed so many I lose track of all the functions I've
done.
>
>
>or do you just cover your
>>failures with supposed alternate "analyses"... and "iteration" ?>:-}
>
>They all work. People are buying them. No technical failures, except that not
>everything always sells.
>
>In my career, over a thousand PCB designs, I've only done a couple that were
>technical "failures." They could have been fixed, but the customer went away
>first. One was a tugboat alarm system that had intermittent CMOS latchup
>problems, before I knew about CMOS latchup. One other was a microstepping
>driver, problems with the H-bridge power stage caused us to miss the boat. Both
>decades ago. But there's no serious money in either business, so no loss to
>anything but pride.
But you're so wonderful... you just can't avoid
demonstrating your manic-depressive (and associated
superiority-inferiority) complexes over and over and over...
Phil Hobbs
Jul 1, 2013, 1:30:41 PM7/1/13
to
capacitor is for.
>
> > The opamp is slow, like kilohertz closed-loop bandwidth in a 100 MHz
> > PLL. We generally plan for the PLL bandwidth to align with the VCO 1/f
> > phase noise corner, to pick up control where we need it. That
> > minimizes jitter.
>
> That slow op amp means it won't respond well to narrow pulses around
> zero.
>
> > But crosstalk to the vco can
> >>injection-lock the oscillator to the reference and make it seem you
> >>have no deadband.
> >>
> >>Worst possible combination you can have.
> >
> > Well, no.
>
> Well, yes.
>
> RC oscillators are very easy to injection-lock. It is much harder to
> injection-lock a LC oscillator.
>
> Phil had a revelation recently about using RC oscillators compared to LC
> oscillators in a PLL. From his post on Tue, 25 June:
>
> > I've used LC VCOs in similar situations. Really dramatically
> > better than a 4046's oscillator.
>
> > Cheers
>
> > Phil Hobbs
>
designed, back when I was about 21 and had been chucked into the deep
end--my first engineering job (with my brand-new B.Sc. in Astronomy and
Physics, plus a 10-year hobby background) gave me sole responsibility
for most of the timing and frequency control system for the first
commercial direct-broadcast satellite system (SpaceTel from AEL
Microtel, introduced in 1983). I'd heard of PLLs at that point, but
never actually seen one, let alone built one.
Very educational, and (between periods of panic) great fun as well.
(Also pretty sporting on Microtel's part.)
> The problem with an RC oscillator is it has no phase memory. You can
> change the phase instantaneously. A small amount of crosstalk can cause a
> step change in the phase of the oscillator.
equation, so there's no memory. If you dump some charge onto the tank
cap, unless you do it at the voltage peak, you'll change the oscillation
phase.
>
> This means the PLL loop now has an error, which will drive the oscillator
> back to zero error. It returns to the spot where it got in trouble in the
> first place, and crosstalk drives it away again.
>
> This sets up a limit cycle oscillation, which can be bad enough to render
> the loop useless.
can fix it by pulling the PFD a few nanoseconds off the zero
point--usually something like a 1M resistor to ground from the PD2
output is all you need.
>
> I have never built a PLL using a RC oscillator that you can't find a
> limit cycle oscillation somewhere in the loop range. However, it is much
> harder to do a step change in phase in an LC oscillator, since the tank
> provides a flywheel effect that remembers the phase of the previous
> cycles.
you can change the instantaneous frequency of the LC in a time much less
than Q/f0, precisely because it has no memory. Systems with memory
require integral equations to represent them, but differential equations
relate instantaneous quantities.
That works for mechanical systems too--a friend of mine from grad
school, Tom Albrecht, sped up the response of atomic force microscopes
by a factor of about 100 by running the cantilever as an oscillator, and
looking at the FM caused by the presence of the sample. The force
gradient looks just like a change in the spring constant, so the
resonant frequency responds in much less than 1 cycle. If you do it the
old way, by using a constant excitation frequency and looking at the
amplitude and phase of the cantilever's response, you're stuck with the
Q/f0 speed limit.
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics
160 North State Road #203
Briarcliff Manor NY 10510 USA
+1 845 480 2058
hobbs at electrooptical dot net
http://electrooptical.net
Phil Hobbs
Jul 1, 2013, 1:57:53 PM7/1/13
to
going to be fast, but that's the only real subtlety. (It's a quarter
cycle for an XOR and half a cycle for a PFD--the average time before a
phase perturbation can show up in the PD output.) The nonlinear dynamics
aren't quite captured by this, but it's pretty close.
> The ECL bangbang PLL, the one we did for NIF, also works great. It has a ps or
> so of RMS jitter and temperature drift below 1 ps/degC. It was designed with
> Bode plots, never simulated.
>
> >
> >You described the phase detector verbally and the changes you had to
> >make. The PFD I posted is the standard Dual-D with NAND feedback. It
> >should operate exactly the same as yours, if it is a standard
> >frequency/phase detector.
>
> We rolled our own no-deadband PFD in an FPGA. Rob did the PFD, in VHDL, and I
> did the diode-amplifier thing I posted, pencil on vellum. I think it was my
> suggestion to go with hard outputs, instead of a charge pump, when Rob started
> describing the risks of using FPGA tri-states to make a charge pump. I never
> liked charge pumps anyhow.
>
> The other zero-deadband loop that would be easy is to make a hybrid, a circuit
> that's a frequency error detector out of lock and an XOR close in, sort of like
> the AD9901. Their logic diagram is on their data sheet. It looks like hell when
> it's out of lock, but it works. The loop filter could be a single RC into the
> VCO.
>
> FPGAs can use counters and stuff to do the coarse lock, too.
>
phase detector. You typically need to generate the quadrature phase
anyway, for a decent lock detector, so you just run the 4046 off that.
(I generally use divide-by-4 Johnson counters, like most other folks.)
Then the 4046's PD1 is the lock detector, PD2 is the acquisition aid,
and the diode bridge does the actual work.
The other cute method for acquisition is to put a little positive
feedback around the loop integrator. When the loop is out of lock, the
phase detector gain goes to zero, so it makes a (very) slow triangle
wave sweep of the whole VCO tuning range. When it goes through the
right frequency, the phase detector takes over and pulls in. (I
thought I was the first to use this, in 1981, but later discovered it
had been invented by somebody else a few years earlier. Cute circuit,
regardless of whose it is.)
Jim Thompson
Jul 1, 2013, 2:05:51 PM7/1/13
to
On Mon, 01 Jul 2013 13:57:53 -0400, Phil Hobbs
<pcdhSpamM...@electrooptical.net> wrote:
[snip]
>>
>
>I've sometimes used a 4046 as an acquisition aid for a diode-bridge
>phase detector. You typically need to generate the quadrature phase
>anyway, for a decent lock detector, so you just run the 4046 off that.
>(I generally use divide-by-4 Johnson counters, like most other folks.)
>
>Then the 4046's PD1 is the lock detector, PD2 is the acquisition aid,
>and the diode bridge does the actual work.
>
>The other cute method for acquisition is to put a little positive
>feedback around the loop integrator. When the loop is out of lock, the
>phase detector gain goes to zero, so it makes a (very) slow triangle
>wave sweep of the whole VCO tuning range. When it goes through the
>right frequency, the phase detector takes over and pulls in. (I
>thought I was the first to use this, in 1981, but later discovered it
>had been invented by somebody else a few years earlier. Cute circuit,
>regardless of whose it is.)
>
>Cheers
>
>Phil Hobbs
Phil, Your talking of dealing with an analog input signal, correct?
There was some scheme called (IIRC) "tanlock" that gave a wider range
and better acquisition, but I can't find my book at the moment :-(
<pcdhSpamM...@electrooptical.net> wrote:
[snip]
>>
>
>I've sometimes used a 4046 as an acquisition aid for a diode-bridge
>phase detector. You typically need to generate the quadrature phase
>anyway, for a decent lock detector, so you just run the 4046 off that.
>(I generally use divide-by-4 Johnson counters, like most other folks.)
>
>Then the 4046's PD1 is the lock detector, PD2 is the acquisition aid,
>and the diode bridge does the actual work.
>
>The other cute method for acquisition is to put a little positive
>feedback around the loop integrator. When the loop is out of lock, the
>phase detector gain goes to zero, so it makes a (very) slow triangle
>wave sweep of the whole VCO tuning range. When it goes through the
>right frequency, the phase detector takes over and pulls in. (I
>thought I was the first to use this, in 1981, but later discovered it
>had been invented by somebody else a few years earlier. Cute circuit,
>regardless of whose it is.)
>
>Cheers
>
>Phil Hobbs
There was some scheme called (IIRC) "tanlock" that gave a wider range
and better acquisition, but I can't find my book at the moment :-(
John Larkin
Jul 1, 2013, 3:39:11 PM7/1/13
to
On Mon, 01 Jul 2013 10:02:15 -0700, Jim Thompson
There aren't that many knobs to turn in a PLL. You get the damping
right and optimize the loop bandwidth for minimum phase noise or
jitter. Those things are done by design, not by simulation. We don't
usually care about acquisition time, which can involve some truly
intimidating math.
I never said that you can't, or haven't, designed working linear ICs.
You keep saying that I can't design board-level electronics, which is
idiotic.
--
John Larkin Highland Technology, Inc
jlarkin at highlandtechnology dot com
http://www.highlandtechnology.com
Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Custom laser drivers and controllers
right and optimize the loop bandwidth for minimum phase noise or
jitter. Those things are done by design, not by simulation. We don't
usually care about acquisition time, which can involve some truly
intimidating math.
You keep saying that I can't design board-level electronics, which is
idiotic.
--
John Larkin Highland Technology, Inc
jlarkin at highlandtechnology dot com
Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Photonics and fiberoptic TTL data links
VME thermocouple, LVDT, synchro acquisition and simulation
John Larkin
Jul 1, 2013, 3:48:37 PM7/1/13
to
be pretty much invisible. Most VCXOs have an (often unspecified) RC
lowpass filter before the varicap, low 10s of KHz modulation bandwidth
typical. Loop analysis should take that into account, too.
The PLL we use in our digital delay generators drives an LC oscillator
that tunes very fast. We need it to lock to within picoseconds in a
few hundred ns, tens of cycles. I simulated that in PowerBasic, with
all the delays. There are ADCs and DACs in the loop, and algorithms,
so it would be awkward in Spice. Maybe something like Matlab would
work.
sweep-search things.
--
John Larkin Highland Technology, Inc
jlarkin at highlandtechnology dot com
http://www.highlandtechnology.com
Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Photonics and fiberoptic TTL data links
Jim Thompson
Jul 1, 2013, 4:02:26 PM7/1/13
to
On Mon, 01 Jul 2013 12:39:11 -0700, John Larkin
<jla...@highlandtechnology.com> wrote:
>On Mon, 01 Jul 2013 10:02:15 -0700, Jim Thompson
><To-Email-Use-Th...@On-My-Web-Site.com> wrote:
>
>>On Mon, 01 Jul 2013 09:36:27 -0700, John Larkin
>><jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>>
>>>On Mon, 01 Jul 2013 09:13:03 -0700, Jim Thompson
>>><To-Email-Use-Th...@On-My-Web-Site.com> wrote:
>>>
>>>>On Mon, 01 Jul 2013 08:43:14 -0700, John Larkin
>>>><jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>>>>
>>>>>On Sun, 30 Jun 2013 23:07:21 -0700, Jim Thompson
>>>>><To-Email-Use-Th...@On-My-Web-Site.com> wrote:
>>>>>
>>>>>>On Sun, 30 Jun 2013 22:44:41 -0700, John Larkin
>>>>>><jjla...@highNOTlandTHIStechnologyPART.com> wrote:
[snip]
>>>>
<jla...@highlandtechnology.com> wrote:
>On Mon, 01 Jul 2013 10:02:15 -0700, Jim Thompson
><To-Email-Use-Th...@On-My-Web-Site.com> wrote:
>
>>On Mon, 01 Jul 2013 09:36:27 -0700, John Larkin
>><jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>>
>>>On Mon, 01 Jul 2013 09:13:03 -0700, Jim Thompson
>>><To-Email-Use-Th...@On-My-Web-Site.com> wrote:
>>>
>>>>On Mon, 01 Jul 2013 08:43:14 -0700, John Larkin
>>>><jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>>>>
>>>>>On Sun, 30 Jun 2013 23:07:21 -0700, Jim Thompson
>>>>><To-Email-Use-Th...@On-My-Web-Site.com> wrote:
>>>>>
>>>>>>On Sun, 30 Jun 2013 22:44:41 -0700, John Larkin
>>>>>><jjla...@highNOTlandTHIStechnologyPART.com> wrote:
[snip]
>>>>
>>>>It shows... or more accurately, as JK showed you up ;-)
>>>
>>>We've sold megabucks of gear with our PLLs inside. They all work.
>>>
>>
>>Do they work as well as they could, or only as good as you iterated
>>but didn't move the right variable?
>
>There aren't that many knobs to turn in a PLL. You get the damping
>right and optimize the loop bandwidth for minimum phase noise or
>jitter. Those things are done by design, not by simulation. We don't
>usually care about acquisition time, which can involve some truly
>intimidating math.
Well, duh! Posted here _10_ years ago...
>>>
>>>We've sold megabucks of gear with our PLLs inside. They all work.
>>>
>>
>>Do they work as well as they could, or only as good as you iterated
>>but didn't move the right variable?
>
>There aren't that many knobs to turn in a PLL. You get the damping
>right and optimize the loop bandwidth for minimum phase noise or
>jitter. Those things are done by design, not by simulation. We don't
>usually care about acquisition time, which can involve some truly
>intimidating math.
http://www.analog-innovations.com/SED/PhaseLockedLoopAnalysis.pdf
I've been doing such analyses since I was a kid.
>
>
>>
>>[snip]
>>>
>>>You can't help turning technical posts personal. You can't help, period.
>>
>>Do you have any idea how ridiculous that statement sounds? You used
>>terms like "moron" and "Have I mentioned lately that you're an idiot?"
>>in response to my technical issues.
>>
>>>>
>>>>Designed anything properly recently...
>>>
>>>
>>>Just recently?
>>>
>>>24-channel LVDT/Synchro acquisition/simulation board.
>>>
>>>Several multichannel ARBs
>>>
>>>Several laser drivers, some picoseconds, some hundreds of amps
>>>
>>>VME digital i/o board
>>>
>>>Parts of a couple of PCI Express controllers.
>>>
>>>Bunch of picosecond timing and fiberoptic things
>>>
>>>Controller and several i/o boxes for an EUV lithography source.
>>>
>>>Another NMR gradient driver
>>>
>>>Another magnetic field mapping system
>>>
>>>All stuff that you couldn't do.
You forget I spent quite a few years doing "box" designs for GenRad
>>>You can't help turning technical posts personal. You can't help, period.
>>
>>Do you have any idea how ridiculous that statement sounds? You used
>>terms like "moron" and "Have I mentioned lately that you're an idiot?"
>>in response to my technical issues.
>>
>>>>
>>>>Designed anything properly recently...
>>>
>>>
>>>Just recently?
>>>
>>>24-channel LVDT/Synchro acquisition/simulation board.
>>>
>>>Several multichannel ARBs
>>>
>>>Several laser drivers, some picoseconds, some hundreds of amps
>>>
>>>VME digital i/o board
>>>
>>>Parts of a couple of PCI Express controllers.
>>>
>>>Bunch of picosecond timing and fiberoptic things
>>>
>>>Controller and several i/o boxes for an EUV lithography source.
>>>
>>>Another NMR gradient driver
>>>
>>>Another magnetic field mapping system
>>>
>>>All stuff that you couldn't do.
(and others). "Analog" is quite an encompassing art form. I even
designed a 5V/400A switching power supply once ;-)
>>>
>>
>>Anything you "built" that has ECL/PECL or LVDS in it... I probably
>>designed the chip that you are using. And who knows what other
>>chips... I've designed so many I lose track of all the functions I've
>>done.
>
>I never said that you can't, or haven't, designed working linear ICs.
>You keep saying that I can't design board-level electronics, which is
>idiotic.
certainly can't cope with any criticism, and switch to name-calling
and your standard crap line... "What have you designed recently?"
Do us all a favor and grow up.
Phil Hobbs
Jul 1, 2013, 4:10:45 PM7/1/13
to
Jim Thompson wrote:
>
> On Mon, 01 Jul 2013 13:57:53 -0400, Phil Hobbs
> <pcdhSpamM...@electrooptical.net> wrote:
>
> [snip]
>
> >>
> >
> >I've sometimes used a 4046 as an acquisition aid for a diode-bridge
> >phase detector. You typically need to generate the quadrature phase
> >anyway, for a decent lock detector, so you just run the 4046 off that.
> >(I generally use divide-by-4 Johnson counters, like most other folks.)
> >
> >Then the 4046's PD1 is the lock detector, PD2 is the acquisition aid,
> >and the diode bridge does the actual work.
> >
> >The other cute method for acquisition is to put a little positive
> >feedback around the loop integrator. When the loop is out of lock, the
> >phase detector gain goes to zero, so it makes a (very) slow triangle
> >wave sweep of the whole VCO tuning range. When it goes through the
> >right frequency, the phase detector takes over and pulls in. (I
> >thought I was the first to use this, in 1981, but later discovered it
> >had been invented by somebody else a few years earlier. Cute circuit,
> >regardless of whose it is.)
> >
> >Cheers
> >
> >Phil Hobbs
>
> Phil, Your talking of dealing with an analog input signal, correct?
>
> There was some scheme called (IIRC) "tanlock" that gave a wider range
> and better acquisition, but I can't find my book at the moment :-(
I remember that one--it used an analog divider or something to stretch
>
> On Mon, 01 Jul 2013 13:57:53 -0400, Phil Hobbs
> <pcdhSpamM...@electrooptical.net> wrote:
>
> [snip]
>
> >>
> >
> >I've sometimes used a 4046 as an acquisition aid for a diode-bridge
> >phase detector. You typically need to generate the quadrature phase
> >anyway, for a decent lock detector, so you just run the 4046 off that.
> >(I generally use divide-by-4 Johnson counters, like most other folks.)
> >
> >Then the 4046's PD1 is the lock detector, PD2 is the acquisition aid,
> >and the diode bridge does the actual work.
> >
> >The other cute method for acquisition is to put a little positive
> >feedback around the loop integrator. When the loop is out of lock, the
> >phase detector gain goes to zero, so it makes a (very) slow triangle
> >wave sweep of the whole VCO tuning range. When it goes through the
> >right frequency, the phase detector takes over and pulls in. (I
> >thought I was the first to use this, in 1981, but later discovered it
> >had been invented by somebody else a few years earlier. Cute circuit,
> >regardless of whose it is.)
> >
> >Cheers
> >
> >Phil Hobbs
>
> Phil, Your talking of dealing with an analog input signal, correct?
>
> There was some scheme called (IIRC) "tanlock" that gave a wider range
> and better acquisition, but I can't find my book at the moment :-(
the sinusoidal PD output into a more sawtoothy sort of thing. I
remember reading about it in Gardner but never used one. It was easier
to use trapezoids (really clipped sinusoids) going into the diode
bridge, which gave almost exactly the same effect.
Gerhard Hoffmann
Jul 1, 2013, 4:51:40 PM7/1/13
to
Am 01.07.2013 22:10, schrieb Phil Hobbs:
<
http://www.amazon.de/Digital-Phase-Lock-Loops-Architectures/dp/0387328637/ref=sr_1_1?ie=UTF8&qid=1372710309&sr=8-1&keywords=digital+phase+locked+loops+Springer
>
Sorry for Amazon.de, but Amazon seem to know me.
The book covers the "normal" tanlock loop, but it is really
about a version that replaces the Hilbert transformer by
a cheap delay and seems to live quite well with the resulting
imperfections.
IIRC, the main advantage of the tanlock loop was a certain
insensitivity to input level variations. Since I had AGC anyway,
I did stay with more mainstream PLLs/Costas etc.
(And since I had a DDS upstream, sin + cos came nearly for free
and the Hilbert was no problem.)
regards, Gerhard
The Amazon pricing is funny: the cheap used pocket book costs most.
:-)
> Jim Thompson wrote:
>> Phil, Your talking of dealing with an analog input signal, correct?
>>
>> There was some scheme called (IIRC) "tanlock" that gave a wider range
>> and better acquisition, but I can't find my book at the moment :-(
>
> I remember that one--it used an analog divider or something to stretch
> the sinusoidal PD output into a more sawtoothy sort of thing. I
> remember reading about it in Gardner but never used one. It was easier
> to use trapezoids (really clipped sinusoids) going into the diode
> bridge, which gave almost exactly the same effect.
Ok, the digital version:
>> Phil, Your talking of dealing with an analog input signal, correct?
>>
>> There was some scheme called (IIRC) "tanlock" that gave a wider range
>> and better acquisition, but I can't find my book at the moment :-(
>
> I remember that one--it used an analog divider or something to stretch
> the sinusoidal PD output into a more sawtoothy sort of thing. I
> remember reading about it in Gardner but never used one. It was easier
> to use trapezoids (really clipped sinusoids) going into the diode
> bridge, which gave almost exactly the same effect.
<
http://www.amazon.de/Digital-Phase-Lock-Loops-Architectures/dp/0387328637/ref=sr_1_1?ie=UTF8&qid=1372710309&sr=8-1&keywords=digital+phase+locked+loops+Springer
>
Sorry for Amazon.de, but Amazon seem to know me.
The book covers the "normal" tanlock loop, but it is really
about a version that replaces the Hilbert transformer by
a cheap delay and seems to live quite well with the resulting
imperfections.
IIRC, the main advantage of the tanlock loop was a certain
insensitivity to input level variations. Since I had AGC anyway,
I did stay with more mainstream PLLs/Costas etc.
(And since I had a DDS upstream, sin + cos came nearly for free
and the Hilbert was no problem.)
regards, Gerhard
The Amazon pricing is funny: the cheap used pocket book costs most.
:-)
Message has been deleted
Message has been deleted
Jim Thompson
Jul 1, 2013, 5:59:04 PM7/1/13
to
On Mon, 01 Jul 2013 14:26:44 -0700, Fred Abse
<excret...@invalid.invalid> wrote:
>On Sun, 30 Jun 2013 19:46:23 -0700, Jim Thompson wrote:
>
>> Why is it "impossible to use it in LTspice"?
>
>It isn't, of course.
>
>It's the BV that caused the problem. I've just noticed that none of the
>LTspice-supplied diode models have breakdown voltages - apart from those
>characterized as zeners. UGH!
>
>Moral: use manufacturer's models.
Yep. LTspice plays fast and loose with models that speed things up,
hide instabilities, and are rarely more than sloppy approximations to
real life. But it's fast ;-)
>
>As to behavioral models, what really screws things is people trying
>to extrapolate fitted polynomials into no-man's-land.
Thus my many posts/inquiries on the LTspice list regarding smooth
fits.
Right now I pretty much make TANH-based bounding functions, but I am
investigating "splines".
I suspect our resident "expert" designer is being had by PhD modeling
jerks who use the LIMIT function without regard to the consequences
;-)
<excret...@invalid.invalid> wrote:
>On Sun, 30 Jun 2013 19:46:23 -0700, Jim Thompson wrote:
>
>> Why is it "impossible to use it in LTspice"?
>
>
>>
>> The Spice parameters are in the data sheet...
>>
>> Table 3. SPICE Model Parameters SMS7621-060:
>>
>> IS = 2.6459E-8
>> RS = 12.5
>> N = 1.01
>> TT = 1E-11
>> CJO = 0.13pF
>> M = 0.35
>> EG = 0.69
>> XTI = 2
>> FC = 0.5
>> BV = 3
>> IBV = 1E-5
>> VJ = 0.51
>
>2 volt rated mixer diode. Ok inside its ratings.
>>
>> The Spice parameters are in the data sheet...
>>
>> Table 3. SPICE Model Parameters SMS7621-060:
>>
>> IS = 2.6459E-8
>> RS = 12.5
>> N = 1.01
>> TT = 1E-11
>> CJO = 0.13pF
>> M = 0.35
>> EG = 0.69
>> XTI = 2
>> FC = 0.5
>> BV = 3
>> IBV = 1E-5
>> VJ = 0.51
>
>
>It's the BV that caused the problem. I've just noticed that none of the
>LTspice-supplied diode models have breakdown voltages - apart from those
>characterized as zeners. UGH!
>
>Moral: use manufacturer's models.
Yep. LTspice plays fast and loose with models that speed things up,
hide instabilities, and are rarely more than sloppy approximations to
real life. But it's fast ;-)
>
>As to behavioral models, what really screws things is people trying
>to extrapolate fitted polynomials into no-man's-land.
Thus my many posts/inquiries on the LTspice list regarding smooth
fits.
Right now I pretty much make TANH-based bounding functions, but I am
investigating "splines".
I suspect our resident "expert" designer is being had by PhD modeling
jerks who use the LIMIT function without regard to the consequences
;-)
Jim Thompson
Jul 1, 2013, 6:00:34 PM7/1/13
to
On Mon, 01 Jul 2013 14:26:42 -0700, Fred Abse
<excret...@invalid.invalid> wrote:
>On Mon, 01 Jul 2013 02:35:09 +0000, John K wrote:
>
>> I have been following the thread "Boost Converter Efficiency Improvements"
>> and the struggle to improve the analysis speed using the SMS7621.
>
>It wasn't an attempt to improve the speed. What happened was that John L's
>simulation ran reasonably fast for him, but stalled for me. It turns out
>that John has been using a model for the 7621 that isn't the official one.
>I was using the Skyworks-supplied model, with a BV of 3 volts, which just
>breaks down with the reverse voltage it gets in that circuit. Substituting
>a diode with sensible reverse breakdown for the application made things
>run fine.
>
>The SMS7621 is a perfectly good *2 VOLT RATED* mixer diode, and the
>official model is good in Spice, when it's used within its ratings.
>
>I've not seen John's 7621 model ,but I'd like to. He claims to use it up
>to 8 volts, but that's way out of ratings.
The "model" probably makes it to 8V, nevermind reality ;-)
<excret...@invalid.invalid> wrote:
>On Mon, 01 Jul 2013 02:35:09 +0000, John K wrote:
>
>> I have been following the thread "Boost Converter Efficiency Improvements"
>> and the struggle to improve the analysis speed using the SMS7621.
>
>simulation ran reasonably fast for him, but stalled for me. It turns out
>that John has been using a model for the 7621 that isn't the official one.
>I was using the Skyworks-supplied model, with a BV of 3 volts, which just
>breaks down with the reverse voltage it gets in that circuit. Substituting
>a diode with sensible reverse breakdown for the application made things
>run fine.
>
>The SMS7621 is a perfectly good *2 VOLT RATED* mixer diode, and the
>official model is good in Spice, when it's used within its ratings.
>
>I've not seen John's 7621 model ,but I'd like to. He claims to use it up
>to 8 volts, but that's way out of ratings.
The "model" probably makes it to 8V, nevermind reality ;-)
George Herold
Jul 1, 2013, 8:11:16 PM7/1/13
to
> liked charge pumps anyhow.
> The other zero-deadband loop that would be easy is to make a hybrid, a circuit
> that's a frequency error detector out of lock and an XOR close in, sort of like
Nice thread! (I'm enjoying it much more than politcial..stuff.)
> The other zero-deadband loop that would be easy is to make a hybrid, a circuit
> that's a frequency error detector out of lock and an XOR close in, sort of like
So, I've never done a PLL, but lots of control loops.
The dead band reminds me of the cross-over error you run into if you've got a
push-pull power stage in the loop.
(There's some place the thing might 'wig out' if set too tightly.)
(Class A is my only solution to crossover.)
George H.
John Larkin
Jul 1, 2013, 8:12:36 PM7/1/13
to
On Mon, 01 Jul 2013 14:26:42 -0700, Fred Abse
<excret...@invalid.invalid> wrote:
>On Mon, 01 Jul 2013 02:35:09 +0000, John K wrote:
>
>> I have been following the thread "Boost Converter Efficiency Improvements"
>> and the struggle to improve the analysis speed using the SMS7621.
>
>It wasn't an attempt to improve the speed. What happened was that John L's
>simulation ran reasonably fast for him, but stalled for me. It turns out
>that John has been using a model for the 7621 that isn't the official one.
>I was using the Skyworks-supplied model, with a BV of 3 volts, which just
>breaks down with the reverse voltage it gets in that circuit. Substituting
>a diode with sensible reverse breakdown for the application made things
>run fine.
>
>The SMS7621 is a perfectly good *2 VOLT RATED* mixer diode, and the
>official model is good in Spice, when it's used within its ratings.
>
>I've not seen John's 7621 model ,but I'd like to. He claims to use it up
>to 8 volts, but that's way out of ratings.
The actual reverse current is about 1 uA at 4 volts, 5 uA at 6 volts.
>simulation ran reasonably fast for him, but stalled for me. It turns out
>that John has been using a model for the 7621 that isn't the official one.
>I was using the Skyworks-supplied model, with a BV of 3 volts, which just
>breaks down with the reverse voltage it gets in that circuit. Substituting
>a diode with sensible reverse breakdown for the application made things
>run fine.
>
>The SMS7621 is a perfectly good *2 VOLT RATED* mixer diode, and the
>official model is good in Spice, when it's used within its ratings.
>
>I've not seen John's 7621 model ,but I'd like to. He claims to use it up
>to 8 volts, but that's way out of ratings.
These kinds of diodes don't have a hard knee... they just leak more as
reverse voltage goes up. I use them up to 3.3 volts or so, no
problems. I wouldn't use one at anything like 8 volts; it would be
very leaky.
In my little self-charging schmitt soft-start, the diode never sees
more than about 1 volt reverse, essentially the schmitt hysteresis
voltage.
--
John Larkin Highland Technology, Inc
jlarkin at highlandtechnology dot com
http://www.highlandtechnology.com
Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Photonics and fiberoptic TTL data links
John Larkin
Jul 1, 2013, 8:18:23 PM7/1/13
to
On Mon, 01 Jul 2013 13:02:26 -0700, Jim Thompson
You've said it many, many times. It's clearly stupid.
This is just one of your quotes, in this very thread:
--------------
You said, in another post, "It take some actual skill to design a
PLL."
So show us something technical about PLL's... something other than
your standard drivel.
You can't. You're a fraud.
-------------
And I did post my diode-error amp/delta-sigma thing, you idiot.
But you
>certainly can't cope with any criticism, and switch to name-calling
>and your standard crap line... "What have you designed recently?"
It's a reasonable question to ask obnoxious lurkers who pop up with
off-topic trash. They usually don't/can't answer.
This is an electronics design group.
As usual, we have technical discussions and you break
personal/obnoxious. You did it here again.
This is just one of your quotes, in this very thread:
--------------
You said, in another post, "It take some actual skill to design a
PLL."
So show us something technical about PLL's... something other than
your standard drivel.
You can't. You're a fraud.
-------------
And I did post my diode-error amp/delta-sigma thing, you idiot.
But you
>certainly can't cope with any criticism, and switch to name-calling
>and your standard crap line... "What have you designed recently?"
off-topic trash. They usually don't/can't answer.
This is an electronics design group.
As usual, we have technical discussions and you break
personal/obnoxious. You did it here again.
George Herold
Jul 1, 2013, 8:23:33 PM7/1/13
to
> cap, unless you do it at the voltage peak, you'll change the oscillation
> phase.
Excellent, I wanted to say this but didn't know how.
> phase.
If you change something in an LCR circuit the change shows up right away.
(I'm still getting use to this idea.)
So injecting charge at the voltage peak just means the amplitude of the next cycle will be bigger.
And it takes ~Q cycles for the transient to die down. (?correct me if wrong?)
George H.
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