STEP file, which viewer?

[Joerg]

Folks,

Got a file in "STEP" format from a client. Yet another drawing format
... <sigh>

So how can I make this visible on a Windows PC? There seem to be a
gazillion viewers. Which one is good and, most of all, clean. Clean as
in no viruses, nasty nagware, low intrusiveness, reasonable footprint.

--
Regards, Joerg

http://www.analogconsultants.com/

[Jim Thompson]

On Fri, 21 Mar 2014 07:28:53 -0700, Joerg <inv...@invalid.invalid>
wrote:

>Folks,
>
>Got a file in "STEP" format from a client. Yet another drawing format
>... <sigh>
>
>So how can I make this visible on a Windows PC? There seem to be a
>gazillion viewers. Which one is good and, most of all, clean. Clean as
>in no viruses, nasty nagware, low intrusiveness, reasonable footprint.

Had the same problem on March 4. It's some kind of mechanical
drawing. Since the client wanted an IBIS model, which you don't do
with a mechanical drawing, I tossed it back. But several people here
referred me to viewers I didn't save that info :-(

I'm sure they'll come forth.

...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| San Tan Valley, AZ 85142 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

[John Larkin]

On Fri, 21 Mar 2014 07:28:53 -0700, Joerg <inv...@invalid.invalid> wrote:

>Folks,
>
>Got a file in "STEP" format from a client. Yet another drawing format
>... <sigh>
>
>So how can I make this visible on a Windows PC? There seem to be a
>gazillion viewers. Which one is good and, most of all, clean. Clean as
>in no viruses, nasty nagware, low intrusiveness, reasonable footprint.

eDrawings, free download from SolidWorks. Views Autocad files, too.

It's fun to play with, 3D rotations and stuff. Unlike the full SolidWorks, it
only lets you look at an object from outside, although you can sometimes peek
inside through windows or holes.


--

John Larkin Highland Technology Inc
www.highlandtechnology.com jlarkin at highlandtechnology dot com

Precision electronic instrumentation

[Joerg]

John Larkin wrote:
> On Fri, 21 Mar 2014 07:28:53 -0700, Joerg <inv...@invalid.invalid> wrote:
>
>> Folks,
>>
>> Got a file in "STEP" format from a client. Yet another drawing format
>> ... <sigh>
>>
>> So how can I make this visible on a Windows PC? There seem to be a
>> gazillion viewers. Which one is good and, most of all, clean. Clean as
>> in no viruses, nasty nagware, low intrusiveness, reasonable footprint.
>
> eDrawings, free download from SolidWorks. Views Autocad files, too.
>

I have that. Result: Unsupported File Type :-(

Clicking on "check for updates" it says that I've got the newest
version. Can you check yours under the tabs Help -> About? I have
10.2.0.122 from Dassault.

> It's fun to play with, 3D rotations and stuff. Unlike the full SolidWorks, it
> only lets you look at an object from outside, although you can sometimes peek
> inside through windows or holes.
>

It sure is fun but so far it's only worked with SolidWorks files. For
the other stuff I bought a 3D CAD program but that can't read *.step
files either.

[Klaus Bahner]

On 21-03-2014 15:28, Joerg wrote:
> Folks,
>
> Got a file in "STEP" format from a client. Yet another drawing format
> ... <sigh>

STEP is kind of universal mechanical data exchange file format. Actually
an ISO standard.
I find it surprising that eDrawings and your other CAD program can't
read them.
I would consider whether the files might be corrupted. Or ask the client
whether he/she is sure that the files are really in a step format.

>
> So how can I make this visible on a Windows PC? There seem to be a
> gazillion viewers. Which one is good and, most of all, clean. Clean as
> in no viruses, nasty nagware, low intrusiveness, reasonable footprint.
>

As already suggested eDrawings should do the trick. Any fully featured
CAD program should also be able to read them, if it really is a STEP file.
Regarding a dedicated STEP viewer, judging from hearsay (never used it
myself) STP Viewer is recommended.

Kind regards,
Klaus Bahner

[John Larkin]

Oops, sorry, that views Solidworks but not STEP.

We have SolidWorks. Send me your file and I'll convert it.

[Joe Chisolm]

On Fri, 21 Mar 2014 07:28:53 -0700, Joerg wrote:

> Folks,
>
> Got a file in "STEP" format from a client. Yet another drawing format
> ... <sigh>
>
> So how can I make this visible on a Windows PC? There seem to be a
> gazillion viewers. Which one is good and, most of all, clean. Clean as
> in no viruses, nasty nagware, low intrusiveness, reasonable footprint.

I think I have used IDA-Step in the past. There are some others I
tried but I'd have to fire up my windows box and look. Maybe
stp viewer. No time right now.

duckduckgo free step file viewer


--
Chisolm
Republic of Texas

[Rich Webb]

On Fri, 21 Mar 2014 07:28:53 -0700, Joerg <inv...@invalid.invalid>
wrote:

>Folks,
>
>Got a file in "STEP" format from a client. Yet another drawing format
>... <sigh>
>
>So how can I make this visible on a Windows PC? There seem to be a
>gazillion viewers. Which one is good and, most of all, clean. Clean as
>in no viruses, nasty nagware, low intrusiveness, reasonable footprint.

Try CAD Exchanger from http://www.cadexchanger.com/index.html. The
basic GUI version is (so far, still) free; he does charge for the SDK
to integrate into other products. It won't do mesh-to-solid conversion
(e.g., STL to ACIS) and it doesn't include dimensioning tools but it's
a pretty decent viewer.

[Fred Bartoli]

Le Fri, 21 Mar 2014 07:28:53 -0700, Joerg a écrit:

> Folks,
>
> Got a file in "STEP" format from a client. Yet another drawing format
> ... <sigh>
>
> So how can I make this visible on a Windows PC? There seem to be a
> gazillion viewers. Which one is good and, most of all, clean. Clean as
> in no viruses, nasty nagware, low intrusiveness, reasonable footprint.

Well, save the gazillion+1 sofware install...
When I face such things and don't have to work with the file (other than
have a look/print) I just ask them to make a pdf.

Isn't that supposed to be 'the' tool after all?


--
Thanks,
Fred.

[JM]

stlviewer (from sourceforge) - nice small footprint.

[John Devereux]

John Larkin <jjla...@highNOTlandTHIStechnologyPART.com> writes:

> On Fri, 21 Mar 2014 07:28:53 -0700, Joerg <inv...@invalid.invalid> wrote:
>
>>Folks,
>>
>>Got a file in "STEP" format from a client. Yet another drawing format
>>... <sigh>
>>
>>So how can I make this visible on a Windows PC? There seem to be a
>>gazillion viewers. Which one is good and, most of all, clean. Clean as
>>in no viruses, nasty nagware, low intrusiveness, reasonable footprint.
>
> eDrawings, free download from SolidWorks. Views Autocad files, too.
>
> It's fun to play with, 3D rotations and stuff. Unlike the full SolidWorks, it
> only lets you look at an object from outside, although you can sometimes peek
> inside through windows or holes.

Are you sure?

In my experience you can look inside, hide some parts in an assembly,
make parts transparent, take cross sections, make measurements. All with
the free viewer.

This is when viewing solidworks .EASM files, don't know about other
formats.


--

John Devereux

[Spehro Pefhany]

On Fri, 21 Mar 2014 07:28:53 -0700, Joerg <inv...@invalid.invalid>
wrote:

>Folks,
>
>Got a file in "STEP" format from a client. Yet another drawing format
>... <sigh>
>
>So how can I make this visible on a Windows PC? There seem to be a
>gazillion viewers. Which one is good and, most of all, clean. Clean as
>in no viruses, nasty nagware, low intrusiveness, reasonable footprint.

I have sent at least one person to
http://stpviewer.com/Download/Default.aspx and they've been happy.

Watch out for the sponsored ad fake download buttons on the site.

Most of the good free 3D model viewer programs are tied to the native
file format of an MCAD system like eDrawings (SolidWorks) or Inventor
Viewer (AutoCad Inventor).

For one-shot use, I tend to scan for malware (upload to
https://www.virustotal.com) but I think that file's too big, and
install on a VMWARE virtual machine.

--sp

[John Larkin]

"Section" slices a thing in half, but it seems to still view from
outside. It would be cool to go inside and look around. I don't know
how to do that.


--

John Larkin Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

[Mark Storkamp]

In article <bp30la...@mid.individual.net>,

Joerg <inv...@invalid.invalid> wrote:

> Folks,
>
> Got a file in "STEP" format from a client. Yet another drawing format
> ... <sigh>
>
> So how can I make this visible on a Windows PC? There seem to be a
> gazillion viewers. Which one is good and, most of all, clean. Clean as
> in no viruses, nasty nagware, low intrusiveness, reasonable footprint.

Rhino3D has a free trial version.

[Spehro Pefhany]

STL |= STP does it do both?

[JM]

My mistake - it's STL only. I use Rhino for STEP.

[Joerg]

Joerg wrote:
> Folks,
>
> Got a file in "STEP" format from a client. Yet another drawing format
> ... <sigh>
>
> So how can I make this visible on a Windows PC? There seem to be a
> gazillion viewers. Which one is good and, most of all, clean. Clean as
> in no viruses, nasty nagware, low intrusiveness, reasonable footprint.
>

Thanks for all responses. I've tried IDA and another. Won't work. IDA
doesn't even have a proper file open menu, just some obscure import
thingie that doesn't seem to function. Time to ditch this STEP stuff and
I asked them what Fred said, to send the stuff in a more common format.

I have no idea why on earth we need new file formats all the time. PDF,
Gerber, DOC and DXF is all the EE world really needs.

[Maynard A. Philbrook Jr.]

In article <bp417t...@mid.individual.net>, inv...@invalid.invalid
says...

And you have tried this?

http://stpviewer.com/

Jamie

[Joerg]

I am not going to try any more, unless I really, really have to :-)

[Maynard A. Philbrook Jr.]

In article <bp44fe...@mid.individual.net>, inv...@invalid.invalid
says...

Oh, you give up way to easy!

Oh Wait, don't you use linux ? :)

Jamie

[Paul E Bennett]

Joerg wrote:

> Folks,
>
> Got a file in "STEP" format from a client. Yet another drawing format
> ... <sigh>
>
> So how can I make this visible on a Windows PC? There seem to be a
> gazillion viewers. Which one is good and, most of all, clean. Clean as
> in no viruses, nasty nagware, low intrusiveness, reasonable footprint.

I would use the VariCAD viewer. The viewer is a free to download and use
product that handles a range of the 3D formats. Versions available for Linux
and Windows (see <http://www.varicad.com/en/home/>).

I use the full CAD package as well and both the viewer and CAD package
always behaved very well. The VariCAD software is also reasonably priced for
so capable a package.


--
********************************************************************
Paul E. Bennett IEng MIET.....<email://Paul_E....@topmail.co.uk>
Forth based HIDECS Consultancy.............<http://www.hidecs.co.uk>
Mob: +44 (0)7811-639972
Tel: +44 (0)1235-510979
Going Forth Safely ..... EBA. www.electric-boat-association.org.uk..
********************************************************************

[Joerg]

No, Windows. I just don't see the point why things like a layout have to
be sent in yet another new "standard" file format when the old ones
worked very well. So I asked for the old ones. Which needs to be
available anyhow to make boards.

Maybe it's just one more of those designed-by-committee file formats
like ODF that never really goes anywhere in market share.

[Joerg]

Paul E Bennett wrote:
> Joerg wrote:
>
>> Folks,
>>
>> Got a file in "STEP" format from a client. Yet another drawing format
>> ... <sigh>
>>
>> So how can I make this visible on a Windows PC? There seem to be a
>> gazillion viewers. Which one is good and, most of all, clean. Clean as
>> in no viruses, nasty nagware, low intrusiveness, reasonable footprint.
>
> I would use the VariCAD viewer. The viewer is a free to download and use
> product that handles a range of the 3D formats. Versions available for Linux
> and Windows (see <http://www.varicad.com/en/home/>).
>
> I use the full CAD package as well and both the viewer and CAD package
> always behaved very well. The VariCAD software is also reasonably priced for
> so capable a package.
>

Thanks, Paul. Maybe I'll do that some day. But not right now where I
even have to work the weekend instead of going mountain biking. Life is
too short for spending too much time with new file formats that the
world doesn't really need.

[John Larkin]

What I see lately is MEs that want to assemble an entire instrument in
SolidWorks (or something even more expensive) so they need a STEP file of our
board... every hole, part, connector, heat sink all 3D modeled.

[Joerg]

Can you easily put a board layout into a STEP file?

And why do they need a STEP file? Whenever one of my clients did an
entire instrument in SolidWorks they used the Solidworks file format
(*.sldxxx, I think).

[John Larkin]

We use an older version of PADS. What we do (when we have to) is have PADS dump
a 2D DXF file, import that into SolidWorks, add the 3rd dimension, and export as
SLDASM or STEP. If we're lucky, we can get models of connectors and heatsinks
from the manufacturers, and not have to make them ourselves. Most parts, like
r's and c's and ICs, we just expand to simple bricks, enough to check for
interferances.

>
>And why do they need a STEP file? Whenever one of my clients did an
>entire instrument in SolidWorks they used the Solidworks file format
>(*.sldxxx, I think).

Some people use the higher-end 3D cad stuff, $50K per seat instead of the $5K
for Solidworks. They ask us for STEP files. The STEP files are verbose ASCII,
and can be 10s of megabytes. They zip down nicely for emailing.

[Joerg]

3D is cool. I never use the layout part of my CAD (Eagle) but it has
some sort of extender that can show the board in 3D if you have or
create the models. POV-Ray or something like that, it even shows the
shadows from fake light sources. Occasionally I get one of those files
for checking someone else's work. To my surprise an increasing number of
clients is using Eagle even though it has no hierarchical sheet
structure (which really holds this product back in the marketplace).

They get very close when it comes to model versus the real thing:

http://makezineblog.files.wordpress.com/2008/03/eagle3d_comparison.jpg?w=500&h=185

>> And why do they need a STEP file? Whenever one of my clients did an
>> entire instrument in SolidWorks they used the Solidworks file format
>> (*.sldxxx, I think).
>
> Some people use the higher-end 3D cad stuff, $50K per seat instead of the $5K
> for Solidworks. They ask us for STEP files. The STEP files are verbose ASCII,
> and can be 10s of megabytes. They zip down nicely for emailing.
>

Same here, over 30MB. But when checking a design I prefer to have the
very files that will be sent to the PCB fab house. Seen too much grief
in the past, like when a conversion was done and all the high-power vias
defaulted back to thermal reliefs.

[John Larkin]

I hate hierarchical schematics!

>
>They get very close when it comes to model versus the real thing:
>
>http://makezineblog.files.wordpress.com/2008/03/eagle3d_comparison.jpg?w=500&h=185
>
>
>>> And why do they need a STEP file? Whenever one of my clients did an
>>> entire instrument in SolidWorks they used the Solidworks file format
>>> (*.sldxxx, I think).
>>
>> Some people use the higher-end 3D cad stuff, $50K per seat instead of the $5K
>> for Solidworks. They ask us for STEP files. The STEP files are verbose ASCII,
>> and can be 10s of megabytes. They zip down nicely for emailing.
>>
>
>Same here, over 30MB. But when checking a design I prefer to have the
>very files that will be sent to the PCB fab house. Seen too much grief
>in the past, like when a conversion was done and all the high-power vias
>defaulted back to thermal reliefs.

Sometimes we add copper patches to make sure we have flood-overs.

[k...@attt.bizz]

I *love* 'em (but it's rare to see software that properly supports
them). I hate copy-n-paste. Too easy to make a mistake somewhere
down the path.

[Spehro Pefhany]

On Sat, 22 Mar 2014 10:04:32 -0700, the renowned Joerg
<inv...@invalid.invalid> wrote:

>
>
>Can you easily put a board layout into a STEP file?

You have to create (my preference) or find a 3D model for every
important component, once, preferably when you make the footprint, and
then it's as easy as any other board layout. Plunk it down and the
model appears.

It's great when you want to look for interference with irregular
molded or extruded structures, or (going the other way) create a board
outline that fits within an irregular custom injection molding for a
volume prodcut. I use it all the time for all but the very simplest of
designs.

As a bonus, you can use it for high-quality documentation. The
rendering is derived directly from the file used to create the PCB.

>And why do they need a STEP file? Whenever one of my clients did an
>entire instrument in SolidWorks they used the Solidworks file format
>(*.sldxxx, I think).

Step files are a lingua franca.. every CAD program of note can import
them. Kind of the Esperanto of the MCAD world. IGES is another option.

The other files retain the 'tree' structure of the original parametric
modelling but you can't even open them in older versions of the *same*
software let alone in a competing program. That's right.. SolidWorks
2012 won't open a file saved in SolidWorks 2013. Naughty of them.



Best regards,
Spehro Pefhany
--
"it's the network..." "The Journey is the reward"
sp...@interlog.com Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog Info for designers: http://www.speff.com

[Spehro Pefhany]

On Sat, 22 Mar 2014 08:03:09 -0700, the renowned Joerg
<inv...@invalid.invalid> wrote:

>
>
>Maybe it's just one more of those designed-by-committee file formats
>like ODF that never really goes anywhere in market share.

Actually I think it and IGES have almost all the share for what they
do (MCAD interchange format).

http://en.wikipedia.org/wiki/CAD_data_exchange


Here's what McMaster offers in the way of 3D models for one product

3-D Models

3-D EDRW <--- edrawing view only
3-D IGES <--- interchange format
3-D PDF <--- view only
3-D SAT <--- interchange format
3-D Solidworks <--- native 3D format
3-D STEP <--- interchange format

Grabcad

STEP, Solidworks, STL <--- faceted polyhedral rendering

Digikey (Molex Backplane connector 0755615000)

STEP

[Tim Williams]

"Joerg" <inv...@invalid.invalid> wrote in message
news:bp5u57...@mid.individual.net...

> Can you easily put a board layout into a STEP file?

In Altium, it's about four clicks. Includes whatever models you may have
in the layout already (Altium can link or import STEP and such).

Tim

--
Seven Transistor Labs
Electrical Engineering Consultation
Website: http://seventransistorlabs.com

[Joerg]

Many projects can't be done any other way. Imagine a medical high-end
ultrasound system. 8-10 cards, each the size of a family pizza but
square. Some of those have sections that repeat 64, 128 or 256 time. In
a flat sheet structure that would be a hopeless mess.

>
>> They get very close when it comes to model versus the real thing:
>>
>> http://makezineblog.files.wordpress.com/2008/03/eagle3d_comparison.jpg?w=500&h=185
>>
>>
>>>> And why do they need a STEP file? Whenever one of my clients did an
>>>> entire instrument in SolidWorks they used the Solidworks file format
>>>> (*.sldxxx, I think).
>>> Some people use the higher-end 3D cad stuff, $50K per seat instead of the $5K
>>> for Solidworks. They ask us for STEP files. The STEP files are verbose ASCII,
>>> and can be 10s of megabytes. They zip down nicely for emailing.
>>>
>> Same here, over 30MB. But when checking a design I prefer to have the
>> very files that will be sent to the PCB fab house. Seen too much grief
>> in the past, like when a conversion was done and all the high-power vias
>> defaulted back to thermal reliefs.
>
> Sometimes we add copper patches to make sure we have flood-overs.
>

Then the PCB house "corrects" them because they look out of place. I
rather review the final stuff that goes out for fab.

[Joerg]

Spehro Pefhany wrote:
> On Sat, 22 Mar 2014 10:04:32 -0700, the renowned Joerg
> <inv...@invalid.invalid> wrote:
>
>>
>> Can you easily put a board layout into a STEP file?
>
> You have to create (my preference) or find a 3D model for every
> important component, once, preferably when you make the footprint, and
> then it's as easy as any other board layout. Plunk it down and the
> model appears.
>
> It's great when you want to look for interference with irregular
> molded or extruded structures, or (going the other way) create a board
> outline that fits within an irregular custom injection molding for a
> volume prodcut. I use it all the time for all but the very simplest of
> designs.
>
> As a bonus, you can use it for high-quality documentation. The
> rendering is derived directly from the file used to create the PCB.
>

For me that would be a pain because I deal with custom parts and odd new
form factors all the time. But I don't do layouts anyhow, other than
prescribing the really critical stuff.

>> And why do they need a STEP file? Whenever one of my clients did an
>> entire instrument in SolidWorks they used the Solidworks file format
>> (*.sldxxx, I think).
>
> Step files are a lingua franca.. every CAD program of note can import
> them. Kind of the Esperanto of the MCAD world. IGES is another option.
>

Yeah, but Esperanto (predictably) fizzled. If even eDrawings can't read
STEP then it must not have been all that successful in the marketplace.

> The other files retain the 'tree' structure of the original parametric
> modelling but you can't even open them in older versions of the *same*
> software let alone in a competing program. That's right.. SolidWorks
> 2012 won't open a file saved in SolidWorks 2013. Naughty of them.
>

That's the age-old trick to force people to fork over the maintenance
fees and buy upgrades. I do not play this game. My mech CAD is at least
five years old and all I use it for is to look at DXF files. That's the
de facto standard. My schematic CAD is around 10 years old and works
just fine. I will upgrade some day but only if they improve some major
item on the wish list such as the missing hierarchy.

[Joerg]

Spehro Pefhany wrote:
> On Sat, 22 Mar 2014 08:03:09 -0700, the renowned Joerg
> <inv...@invalid.invalid> wrote:
>
>>
>> Maybe it's just one more of those designed-by-committee file formats
>> like ODF that never really goes anywhere in market share.
>
> Actually I think it and IGES have almost all the share for what they
> do (MCAD interchange format).
>
> http://en.wikipedia.org/wiki/CAD_data_exchange
>

I have about a dozen active clients at most times and never seen it
being used. Except now at a contract manufacturer.

>
> Here's what McMaster offers in the way of 3D models for one product
>
> 3-D Models
>
> 3-D EDRW <--- edrawing view only
> 3-D IGES <--- interchange format
> 3-D PDF <--- view only
> 3-D SAT <--- interchange format
> 3-D Solidworks <--- native 3D format
> 3-D STEP <--- interchange format
>
> Grabcad
>
> STEP, Solidworks, STL <--- faceted polyhedral rendering
>
> Digikey (Molex Backplane connector 0755615000)
>
> STEP
>

Hmm, maybe it's coming, some day. With the major brands such as TE
Connectivity it's PDF even at Digikey.

http://www.digikey.com/product-detail/en/5787422-1/5787422-1-ND/2258868

[Neon John]

On Sat, 22 Mar 2014 16:55:29 -0700, John Larkin
<jjla...@highNOTlandTHIStechnologyPART.com> wrote:

>I hate hierarchical schematics!

AMEN to that. Despise 'em.

John
John DeArmond
http://www.neon-john.com
http://www.fluxeon.com
Tellico Plains, Occupied TN
See website for email address

[k...@attt.bizz]

On Sun, 23 Mar 2014 10:37:44 -0400, Neon John <n...@never.com> wrote:

>On Sat, 22 Mar 2014 16:55:29 -0700, John Larkin
><jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>
>
>>I hate hierarchical schematics!
>
>AMEN to that. Despise 'em.

So you would instantiate every transistor in a microprocessor?

[Joerg]

D2751 is on sheet 182 and its cathode, now where does that go to, ah, to
Q1395 on sheet 275. Now wait, it also goes to ...

[John Larkin]

If any PCB house changes the copper patterns from our Gerbers, we wouldn't pay
for the boards.

[John Larkin]

I've only designed one uP in my career, and I did show every chip on the
schematic.

[k...@attt.bizz]

On Sun, 23 Mar 2014 08:17:35 -0700, Joerg <inv...@invalid.invalid>
wrote:

>k...@attt.bizz wrote:
>> On Sun, 23 Mar 2014 10:37:44 -0400, Neon John <n...@never.com> wrote:
>>
>>> On Sat, 22 Mar 2014 16:55:29 -0700, John Larkin
>>> <jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>>>
>>>
>>>> I hate hierarchical schematics!
>>> AMEN to that. Despise 'em.
>>
>> So you would instantiate every transistor in a microprocessor?
>
>
>D2751 is on sheet 182 and its cathode, now where does that go to, ah, to
>Q1395 on sheet 275. Now wait, it also goes to ...

That's precisely why hierarchy is *needed*. The comesfrom and goesta
are easily found by the interfaces.

[jeroen Belleman]

On 23/03/14 16:17, Joerg wrote:
> k...@attt.bizz wrote:
>> On Sun, 23 Mar 2014 10:37:44 -0400, Neon John <n...@never.com> wrote:
>>
>>> On Sat, 22 Mar 2014 16:55:29 -0700, John Larkin
>>> <jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>>>
>>>
>>>> I hate hierarchical schematics!
>>> AMEN to that. Despise 'em.
>>
>> So you would instantiate every transistor in a microprocessor?
>
>
> D2751 is on sheet 182 and its cathode, now where does that go to, ah, to
> Q1395 on sheet 275. Now wait, it also goes to ...
>

That's not a hierarchy. That's a mess. You can make
a mess of a single flat schematic too.

I suppose even you use single symbols for composite
things like opamps or logic.

Jeroen Belleman

[k...@attt.bizz]

On Sun, 23 Mar 2014 08:40:55 -0700, John Larkin

<jjla...@highNOTlandTHIStechnologyPART.com> wrote:

>On Sun, 23 Mar 2014 10:57:42 -0400, k...@attt.bizz wrote:
>
>>On Sun, 23 Mar 2014 10:37:44 -0400, Neon John <n...@never.com> wrote:
>>
>>>On Sat, 22 Mar 2014 16:55:29 -0700, John Larkin
>>><jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>>>
>>>
>>>>I hate hierarchical schematics!
>>>
>>>AMEN to that. Despise 'em.
>>
>>So you would instantiate every transistor in a microprocessor?
>
>I've only designed one uP in my career, and I did show every chip on the
>schematic.

So you do use hierarchy. ;-)

Try it with a modern uP, even something as simple as an M0.

[Joerg]

k...@attt.bizz wrote:
> On Sun, 23 Mar 2014 08:17:35 -0700, Joerg <inv...@invalid.invalid>
> wrote:
>
>> k...@attt.bizz wrote:
>>> On Sun, 23 Mar 2014 10:37:44 -0400, Neon John <n...@never.com> wrote:
>>>
>>>> On Sat, 22 Mar 2014 16:55:29 -0700, John Larkin
>>>> <jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>>>>
>>>>
>>>>> I hate hierarchical schematics!
>>>> AMEN to that. Despise 'em.
>>> So you would instantiate every transistor in a microprocessor?
>>
>> D2751 is on sheet 182 and its cathode, now where does that go to, ah, to
>> Q1395 on sheet 275. Now wait, it also goes to ...
>
> That's precisely why hierarchy is *needed*. The comesfrom and goesta
> are easily found by the interfaces.

Yup. That's why I am trying to convince Cadsoft for year. So far they
don't get it how important a hierarchy is :-(

[Joerg]

John Larkin wrote:
> On Sun, 23 Mar 2014 07:04:59 -0700, Joerg <inv...@invalid.invalid> wrote:
>
>> John Larkin wrote:
>>> On Sat, 22 Mar 2014 10:55:37 -0700, Joerg <inv...@invalid.invalid> wrote:
>>>
>>>> John Larkin wrote:
>>>>> On Sat, 22 Mar 2014 10:04:32 -0700, Joerg <inv...@invalid.invalid> wrote:
>>>>>

[...]

>>>>>> And why do they need a STEP file? Whenever one of my clients did an
>>>>>> entire instrument in SolidWorks they used the Solidworks file format
>>>>>> (*.sldxxx, I think).
>>>>> Some people use the higher-end 3D cad stuff, $50K per seat instead of the $5K
>>>>> for Solidworks. They ask us for STEP files. The STEP files are verbose ASCII,
>>>>> and can be 10s of megabytes. They zip down nicely for emailing.
>>>>>
>>>> Same here, over 30MB. But when checking a design I prefer to have the
>>>> very files that will be sent to the PCB fab house. Seen too much grief
>>>> in the past, like when a conversion was done and all the high-power vias
>>>> defaulted back to thermal reliefs.
>>> Sometimes we add copper patches to make sure we have flood-overs.
>>>
>> Then the PCB house "corrects" them because they look out of place. I
>> rather review the final stuff that goes out for fab.
>
> If any PCB house changes the copper patterns from our Gerbers, we wouldn't pay
> for the boards.
>

My client didn't either and the PCB house threw in a rush order for
free. Like a car rental company that had to give me an all decked-out
Suburban after botching my compact car reservation.

[Joerg]

jeroen Belleman wrote:
> On 23/03/14 16:17, Joerg wrote:
>> k...@attt.bizz wrote:
>>> On Sun, 23 Mar 2014 10:37:44 -0400, Neon John <n...@never.com> wrote:
>>>
>>>> On Sat, 22 Mar 2014 16:55:29 -0700, John Larkin
>>>> <jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>>>>
>>>>
>>>>> I hate hierarchical schematics!
>>>> AMEN to that. Despise 'em.
>>>
>>> So you would instantiate every transistor in a microprocessor?
>>
>>
>> D2751 is on sheet 182 and its cathode, now where does that go to, ah, to
>> Q1395 on sheet 275. Now wait, it also goes to ...
>>
>
> That's not a hierarchy. That's a mess. You can make
> a mess of a single flat schematic too.
>

Flat sheet structures become a mess when the project is very large.
AFAIR the stack of schematics for the first ultrasound machine I worked
on contained over 200 sheets. That simply does not work in a flat structure.

> I suppose even you use single symbols for composite
> things like opamps or logic.
>

Yes, but not discrete filter blocks. Imagine 256 of them.

[Spehro Pefhany]

Ummm yeah, right <rant>
Hammond had that useless *crap* linked by Digikey, but it looks like
it's all igs and stp now, with dxf for 2D. Eg.
http://www.digikey.com/product-search/en?site=US&keywords=HM973-ND



Naturally, TE themselves have proper IGS, STP and DXF (2D) available
on their website (for the part number you mentioned):
http://www.te.com/catalog/pn/en/5787422-1



Apparently there *is* a way to export STP and IGS from 3D PDF but
maybe not if you don't cross Adobe's palm with about $500 worth of
silver (and only if it was created in a certain mode: U3D)- or some
other expensive progrm. That kind of stuff drives me up the wall.

They're just trying to insinuate themselves into another area, and
bloating their readers up with a full 3D viewer program so they can
make more money. Plus they probably want to extract license fees from
every MCAD company to allow them to open 3D PDF directly. SW 2013 does
*not*. Boycott this stuff.
<\rant>

Interchangable industry-standard file formats such as IGS and STP is
*the* way to go.

[John Larkin]

I have done some guard traces that just ended without a pad or via. The board
houses mostly seem to have software that checks for stuff like that, and they
usually call us to see if it's a mistake. That's fine.

[John Larkin]

Not on my schematics!

>
>Try it with a modern uP, even something as simple as an M0.

My processor was about 40 MSI chips, on two boards, for a shipboard data logger.
The next generation used a 6800.

But I don't design ICs; I put parts on boards. I can see, probe, and replace
those parts, which you can't do very well on an IC. It's different.

"U1517" doesn't fit on the silk very well.

[Fred Bartoli]

Yup, they probably target toy projects :-)


--
Thanks,
Fred.

[Fred Bartoli]

Le Sun, 23 Mar 2014 09:24:41 -0700, Joerg a écrit:

> jeroen Belleman wrote:
>> On 23/03/14 16:17, Joerg wrote:
>>> k...@attt.bizz wrote:
>>>> On Sun, 23 Mar 2014 10:37:44 -0400, Neon John <n...@never.com> wrote:
>>>>
>>>>> On Sat, 22 Mar 2014 16:55:29 -0700, John Larkin
>>>>> <jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>>>>>
>>>>>
>>>>>> I hate hierarchical schematics!
>>>>> AMEN to that. Despise 'em.
>>>>
>>>> So you would instantiate every transistor in a microprocessor?
>>>
>>>
>>> D2751 is on sheet 182 and its cathode, now where does that go to, ah,
>>> to Q1395 on sheet 275. Now wait, it also goes to ...
>>>
>>>
>> That's not a hierarchy. That's a mess. You can make a mess of a single
>> flat schematic too.
>>
>>
>
> Flat sheet structures become a mess when the project is very large.
> AFAIR the stack of schematics for the first ultrasound machine I worked
> on contained over 200 sheets. That simply does not work in a flat
> structure.
>
>

Same for the last project here. Counting 200 pages, with 10 blocks of 5
identical channels. The board is so cluttered that layout time schematic
optimization is mandatory... and I'd hate mod the channel schematic 50
times in a row at each iteration...


--
Thanks,
Fred.

[Joerg]

I don't like Adobe much because of the poor quality of their reader. But
I have to say that the 3D stuff works well. We exchange 3D renderings
that way in a group.

[k...@attt.bizz]

On Sun, 23 Mar 2014 09:20:34 -0700, Joerg <inv...@invalid.invalid>

wrote:

>k...@attt.bizz wrote:
>> On Sun, 23 Mar 2014 08:17:35 -0700, Joerg <inv...@invalid.invalid>
>> wrote:
>>
>>> k...@attt.bizz wrote:
>>>> On Sun, 23 Mar 2014 10:37:44 -0400, Neon John <n...@never.com> wrote:
>>>>
>>>>> On Sat, 22 Mar 2014 16:55:29 -0700, John Larkin
>>>>> <jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>>>>>
>>>>>
>>>>>> I hate hierarchical schematics!
>>>>> AMEN to that. Despise 'em.
>>>> So you would instantiate every transistor in a microprocessor?
>>>
>>> D2751 is on sheet 182 and its cathode, now where does that go to, ah, to
>>> Q1395 on sheet 275. Now wait, it also goes to ...
>>
>> That's precisely why hierarchy is *needed*. The comesfrom and goesta
>> are easily found by the interfaces.
>
>
>Yup. That's why I am trying to convince Cadsoft for year. So far they
>don't get it how important a hierarchy is :-(

Apparently few here do, either.

It only took OrCAD twenty years to get theirs working. Their solution
isn't so great, either. Reference designators are still a PITA (well,
they were last time I checked - haven't used OrCAD in three years).

[k...@attt.bizz]

On 23 Mar 2014 18:26:39 GMT, Fred Bartoli

..and guarantee that all of them are kept in sync.

[k...@attt.bizz]

On Sun, 23 Mar 2014 10:23:52 -0700, John Larkin

<jjla...@highNOTlandTHIStechnologyPART.com> wrote:

>On Sun, 23 Mar 2014 11:48:26 -0400, k...@attt.bizz wrote:
>
>>On Sun, 23 Mar 2014 08:40:55 -0700, John Larkin
>><jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>>
>>>On Sun, 23 Mar 2014 10:57:42 -0400, k...@attt.bizz wrote:
>>>
>>>>On Sun, 23 Mar 2014 10:37:44 -0400, Neon John <n...@never.com> wrote:
>>>>
>>>>>On Sat, 22 Mar 2014 16:55:29 -0700, John Larkin
>>>>><jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>>>>>
>>>>>
>>>>>>I hate hierarchical schematics!
>>>>>
>>>>>AMEN to that. Despise 'em.
>>>>
>>>>So you would instantiate every transistor in a microprocessor?
>>>
>>>I've only designed one uP in my career, and I did show every chip on the
>>>schematic.
>>
>>So you do use hierarchy. ;-)
>
>Not on my schematics!

You drew every transistor in the "chips"?

>>
>>Try it with a modern uP, even something as simple as an M0.
>
>My processor was about 40 MSI chips, on two boards, for a shipboard data logger.
>The next generation used a 6800.

40 parts is simple stuff. There was probably very little that could
have been put in a hierarchy. Try flattening a dozen processing units
of 30-40 files of 1K to 5K lines of hierarchical VHDL, each.

>But I don't design ICs; I put parts on boards. I can see, probe, and replace
>those parts, which you can't do very well on an IC. It's different.

It not different. Just a matter of scale.

>"U1517" doesn't fit on the silk very well.

If you have more than 1000 like parts on a schematic, you're going to
need four digits, in any case[*]. But you don't necessarily need four
digits. I've done hierarchical schematics with three. It took a
little planning but even with software as dumb as OrCAD it wasn't
impossible. Though, if it weren't so dumb it would have been a lot
easier. It was a *lot* easier to control than repetition, over the
long haul.

[Spehro Pefhany]

Do you create them?

[John Larkin]

On Sun, 23 Mar 2014 18:26:27 -0400, k...@attt.bizz wrote:

>On Sun, 23 Mar 2014 10:23:52 -0700, John Larkin
><jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>
>>On Sun, 23 Mar 2014 11:48:26 -0400, k...@attt.bizz wrote:
>>
>>>On Sun, 23 Mar 2014 08:40:55 -0700, John Larkin
>>><jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>>>
>>>>On Sun, 23 Mar 2014 10:57:42 -0400, k...@attt.bizz wrote:
>>>>
>>>>>On Sun, 23 Mar 2014 10:37:44 -0400, Neon John <n...@never.com> wrote:
>>>>>
>>>>>>On Sat, 22 Mar 2014 16:55:29 -0700, John Larkin
>>>>>><jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>>>>>>
>>>>>>
>>>>>>>I hate hierarchical schematics!
>>>>>>
>>>>>>AMEN to that. Despise 'em.
>>>>>
>>>>>So you would instantiate every transistor in a microprocessor?
>>>>
>>>>I've only designed one uP in my career, and I did show every chip on the
>>>>schematic.
>>>
>>>So you do use hierarchy. ;-)
>>
>>Not on my schematics!
>
>You drew every transistor in the "chips"?

I didn't have schematics of the chips, and I didn't design the chips.

If you use standard chips on a PCB, do you include THEIR internal
schematics in your hierarchal board schematic? Why not?

>>>
>>>Try it with a modern uP, even something as simple as an M0.
>>
>>My processor was about 40 MSI chips, on two boards, for a shipboard data logger.
>>The next generation used a 6800.
>
>40 parts is simple stuff. There was probably very little that could
>have been put in a hierarchy. Try flattening a dozen processing units
>of 30-40 files of 1K to 5K lines of hierarchical VHDL, each.

I don't program PCB layouts in VHDL, and I hope I never will. My brain
is more visual than verbal (almost flunked out of high school over
French) so I like schematics.

I guess some board-level design has been done in a programming
language, and not as a schematic. Somewhere.

There was an analog IC VHDL or Verilog or something, don't know if
it's popular. I guess it's not an "RTL" if it doesn't have registers.

>
>>But I don't design ICs; I put parts on boards. I can see, probe, and replace
>>those parts, which you can't do very well on an IC. It's different.
>
>It not different. Just a matter of scale.
>
>>"U1517" doesn't fit on the silk very well.
>
>If you have more than 1000 like parts on a schematic, you're going to
>need four digits, in any case[*]. But you don't necessarily need four
>digits. I've done hierarchical schematics with three. It took a
>little planning but even with software as dumb as OrCAD it wasn't
>impossible. Though, if it weren't so dumb it would have been a lot
>easier. It was a *lot* easier to control than repetition, over the
>long haul.

The densest board we've done was a VME module with about 1100 parts,
stuff on both sides. Horrible. But we got by with 3-digit designators.
We like reference designators, but they get dicey with dense boards
and 0603 parts.


--

John Larkin Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

[Tim Williams]

"Joerg" <inv...@invalid.invalid> wrote in message
news:bp8g6h...@mid.individual.net...

>>> D2751 is on sheet 182 and its cathode, now where does that go to, ah,
>>> to
>>> Q1395 on sheet 275. Now wait, it also goes to ...
>>>
>>
>> That's not a hierarchy. That's a mess. You can make
>> a mess of a single flat schematic too.
>>
>
>
> Flat sheet structures become a mess when the project is very large.
> AFAIR the stack of schematics for the first ultrasound machine I worked
> on contained over 200 sheets. That simply does not work in a flat
> structure.

All of you need to stop your bickering and buy Multisim. It does
hierarchical subsheets and all that. But each instance of a sheet is
auto-generated a new (sequential, if available) set of refdes. So good
luck trying to specify component names, or use multi-part components (like
gates) across subsheets. Also, when you go to print, it prints off a
sheet for each instance, so you can do the hierarchy, and still point to
refdes so-and-so on page something-or-other. (The forward annotation
netlist is flat, but you can specify groups of components to
place-as-template in Ultiboard.)

Tim

--
Seven Transistor Labs
Electrical Engineering Consultation
Website: http://seventransistorlabs.com

[k...@attt.bizz]

On Sun, 23 Mar 2014 16:09:19 -0700, John Larkin
<jla...@highlandtechnology.com> wrote:

>On Sun, 23 Mar 2014 18:26:27 -0400, k...@attt.bizz wrote:
>
>>On Sun, 23 Mar 2014 10:23:52 -0700, John Larkin
>><jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>>
>>>On Sun, 23 Mar 2014 11:48:26 -0400, k...@attt.bizz wrote:
>>>
>>>>On Sun, 23 Mar 2014 08:40:55 -0700, John Larkin
>>>><jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>>>>
>>>>>On Sun, 23 Mar 2014 10:57:42 -0400, k...@attt.bizz wrote:
>>>>>
>>>>>>On Sun, 23 Mar 2014 10:37:44 -0400, Neon John <n...@never.com> wrote:
>>>>>>
>>>>>>>On Sat, 22 Mar 2014 16:55:29 -0700, John Larkin
>>>>>>><jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>>>>>>>
>>>>>>>
>>>>>>>>I hate hierarchical schematics!
>>>>>>>
>>>>>>>AMEN to that. Despise 'em.
>>>>>>
>>>>>>So you would instantiate every transistor in a microprocessor?
>>>>>
>>>>>I've only designed one uP in my career, and I did show every chip on the
>>>>>schematic.
>>>>
>>>>So you do use hierarchy. ;-)
>>>
>>>Not on my schematics!
>>
>>You drew every transistor in the "chips"?
>
>I didn't have schematics of the chips, and I didn't design the chips.
>
>If you use standard chips on a PCB, do you include THEIR internal
>schematics in your hierarchal board schematic? Why not?

I guess you missed the smiley.

>>>>
>>>>Try it with a modern uP, even something as simple as an M0.
>>>
>>>My processor was about 40 MSI chips, on two boards, for a shipboard data logger.
>>>The next generation used a 6800.
>>
>>40 parts is simple stuff. There was probably very little that could
>>have been put in a hierarchy. Try flattening a dozen processing units
>>of 30-40 files of 1K to 5K lines of hierarchical VHDL, each.
>
>I don't program PCB layouts in VHDL, and I hope I never will. My brain
>is more visual than verbal (almost flunked out of high school over
>French) so I like schematics.

Schematics are great for dataflow, not so much for control logic. You
quickly get to appreciate hierarchy, though.

>
>I guess some board-level design has been done in a programming
>language, and not as a schematic. Somewhere.

It is.

>There was an analog IC VHDL or Verilog or something, don't know if
>it's popular. I guess it's not an "RTL" if it doesn't have registers.

VHDL will accommodate analog but, no, I don't know anyone using it for
analog. Analog isn't the entire world, though.

>>
>>>But I don't design ICs; I put parts on boards. I can see, probe, and replace
>>>those parts, which you can't do very well on an IC. It's different.
>>
>>It not different. Just a matter of scale.
>>
>>>"U1517" doesn't fit on the silk very well.
>>
>>If you have more than 1000 like parts on a schematic, you're going to
>>need four digits, in any case[*]. But you don't necessarily need four
>>digits. I've done hierarchical schematics with three. It took a
>>little planning but even with software as dumb as OrCAD it wasn't
>>impossible. Though, if it weren't so dumb it would have been a lot
>>easier. It was a *lot* easier to control than repetition, over the
>>long haul.
>
>The densest board we've done was a VME module with about 1100 parts,
>stuff on both sides. Horrible. But we got by with 3-digit designators.
>We like reference designators, but they get dicey with dense boards
>and 0603 parts.

My last couple of boards are in the few hundreds of components but
before that the average was ~1200, with two at 1500. I tend to use
reference designators to mean something, at least in the design phase
(900s being optional and debug stuff, 800s power supplies, 1000s new
stuff since the last rev, etc.). Of course, that goes out the window
if there are >1000 capacitors. ;-)

On the more dense boards, I sometimes have the CAD guy renumber them
from side to side starting at 1 on the top and 500 on the bottom. That
has its issues, too.

BTW, 0402 is the standard size, though I will use 0603s in places
where changes are expected/planned. 0402s fit in nice lines next to
QFPs (two 0402s resistors with a 0603 cap (resistor) across makes a
nice tight filter (or pad) on a differential analog output of a DAC,
for instance. We don't do 0201s, yet (and likely not in the time I
expect to be there).

[Joerg]

Not really. Orcad-SDT did the hierarchy beautifully. I still miss that
software. Well, I still have the license.

[Joerg]

Spehro Pefhany wrote:
> On Sun, 23 Mar 2014 13:31:24 -0700, the renowned Joerg
> <inv...@invalid.invalid> wrote:
>
>> I don't like Adobe much because of the poor quality of their reader. But
>> I have to say that the 3D stuff works well. We exchange 3D renderings
>> that way in a group.
>
> Do you create them?
>

The ME I work with does.

[John Larkin]

We always resequence. It makes the parts easier to find on the board.

[Spehro Pefhany]

How can you do sensiblly annotated multichannel design without
hierarchy in the schematic?

Or do you consider that a special acceptable case?

--sp

[John Larkin]

On Mon, 24 Mar 2014 14:01:52 -0400, Spehro Pefhany
<spef...@interlogDOTyou.knowwhat> wrote:

>On Mon, 24 Mar 2014 10:01:56 -0700, John Larkin
><jla...@highlandtechnology.com> wrote:
>
>>On Sun, 23 Mar 2014 20:28:01 -0400, k...@attt.bizz wrote:
>>
>
>>>
>>>On the more dense boards, I sometimes have the CAD guy renumber them
>>>from side to side starting at 1 on the top and 500 on the bottom. That
>>>has its issues, too.
>>
>>We always resequence. It makes the parts easier to find on the board.
>
>How can you do sensiblly annotated multichannel design without
>hierarchy in the schematic?

If there are 48 channels, all 48 channels appear on the schematic.
Nice and flat. Every net has a unique net name, and every part has a
unique refdes, which is handy.

What do you mean by "sensibly annotated"?

Parts have ref designators on the schematic and the board. Last part
of the layout, they are geometrically resequenced on the PCB for ease
of physical location, and back annotated to the schematic.

Seems to work.

>
>Or do you consider that a special acceptable case?
>
>--sp

[Spehro Pefhany]

On Mon, 24 Mar 2014 12:04:08 -0700, John Larkin

<jla...@highlandtechnology.com> wrote:

>On Mon, 24 Mar 2014 14:01:52 -0400, Spehro Pefhany
><spef...@interlogDOTyou.knowwhat> wrote:
>
>>On Mon, 24 Mar 2014 10:01:56 -0700, John Larkin
>><jla...@highlandtechnology.com> wrote:
>>
>>>On Sun, 23 Mar 2014 20:28:01 -0400, k...@attt.bizz wrote:
>>>
>>
>>>>
>>>>On the more dense boards, I sometimes have the CAD guy renumber them
>>>>from side to side starting at 1 on the top and 500 on the bottom. That
>>>>has its issues, too.
>>>
>>>We always resequence. It makes the parts easier to find on the board.
>>
>>How can you do sensiblly annotated multichannel design without
>>hierarchy in the schematic?
>
>If there are 48 channels, all 48 channels appear on the schematic.
>Nice and flat. Every net has a unique net name, and every part has a
>unique refdes, which is handy.
>
>What do you mean by "sensibly annotated"?

I use something like R70A R70B R70C for the part that does the same
thing in Channel A, Channel B, Channel C. Altium accomodates that,
automatically though their default is something more general, much
longer and much less desirable for small numbers of channels.

Of course my favorite scheme runs out of gas at Channel Zed (26), but
so far it's been enough.

--sp

[Joerg]

John Larkin wrote:
> On Mon, 24 Mar 2014 14:01:52 -0400, Spehro Pefhany
> <spef...@interlogDOTyou.knowwhat> wrote:
>
>> On Mon, 24 Mar 2014 10:01:56 -0700, John Larkin
>> <jla...@highlandtechnology.com> wrote:
>>
>>> On Sun, 23 Mar 2014 20:28:01 -0400, k...@attt.bizz wrote:
>>>
>>>> On the more dense boards, I sometimes have the CAD guy renumber them
>>> >from side to side starting at 1 on the top and 500 on the bottom. That
>>>> has its issues, too.
>>> We always resequence. It makes the parts easier to find on the board.
>> How can you do sensiblly annotated multichannel design without
>> hierarchy in the schematic?
>
> If there are 48 channels, all 48 channels appear on the schematic.

Yikes. That's why there are no trees left around San Francisco :-)

[...]

[John Larkin]

On Mon, 24 Mar 2014 16:44:38 -0400, Spehro Pefhany

R70A through R70D are sections ("gates" to PADS) of a 1206 quad
resistor pack!.

[John Larkin]

On Mon, 24 Mar 2014 13:37:08 -0700, Joerg <inv...@invalid.invalid>
wrote:

The gadget in layout now has 48 channels of isolated digital inputs,
with amazingly clever front-end self-test. The schematic is 19 sheets.
The way things are partitioned, a true hierarchical design would be
messy and (to my tiny mind) confusing.

A 16-channel thermocouple simulator module ran to 24 sheets, half of
which are the channels. If the channels were blocks, each would have
the i/o connector pins, power supplies, FPGA pins, test bus, and a few
more things sticking out of each block. Mysterious albino porcupines.

[Joerg]

That's all still fairly low channel numbers. The biggest schematic I had
to deal with was a 256-channel system where the channels were busy
analog circuits. You could have crammed two onto a page if resorting to
Japanese-style circuit drawings but even that would have been 128
sheets. Instead, we had only one for all those channel sections and it
was nice and spacious. The rest of the board was another couple dozen or
so sheets.

Some of the reviews clients want me to do would be next to impossible
without a hierarchical set of schematics.

[k...@attt.bizz]

On Mon, 24 Mar 2014 10:01:56 -0700, John Larkin

Sometimes. Not always. There's often other reasons not to renumber.
"Always" rules always get in the way.

[k...@attt.bizz]

On Mon, 24 Mar 2014 12:04:08 -0700, John Larkin

<jla...@highlandtechnology.com> wrote:

>On Mon, 24 Mar 2014 14:01:52 -0400, Spehro Pefhany
><spef...@interlogDOTyou.knowwhat> wrote:
>
>>On Mon, 24 Mar 2014 10:01:56 -0700, John Larkin
>><jla...@highlandtechnology.com> wrote:
>>
>>>On Sun, 23 Mar 2014 20:28:01 -0400, k...@attt.bizz wrote:
>>>
>>
>>>>
>>>>On the more dense boards, I sometimes have the CAD guy renumber them
>>>>from side to side starting at 1 on the top and 500 on the bottom. That
>>>>has its issues, too.
>>>
>>>We always resequence. It makes the parts easier to find on the board.
>>
>>How can you do sensiblly annotated multichannel design without
>>hierarchy in the schematic?
>
>If there are 48 channels, all 48 channels appear on the schematic.
>Nice and flat.

Ick. How do you guarantee that any changes make it into all 48?

>Every net has a unique net name, and every part has a
>unique refdes, which is handy.

Hierarchy doesn't preclude any of the above, in any way.

>What do you mean by "sensibly annotated"?
>
>Parts have ref designators on the schematic and the board. Last part
>of the layout, they are geometrically resequenced on the PCB for ease
>of physical location, and back annotated to the schematic.
>
>Seems to work.
>

Except when it doesn't.

[John Larkin]

"Sometimes" rules aren't rules!

[John Larkin]

On Mon, 24 Mar 2014 19:43:02 -0400, k...@attt.bizz wrote:

>On Mon, 24 Mar 2014 12:04:08 -0700, John Larkin
><jla...@highlandtechnology.com> wrote:
>
>>On Mon, 24 Mar 2014 14:01:52 -0400, Spehro Pefhany
>><spef...@interlogDOTyou.knowwhat> wrote:
>>
>>>On Mon, 24 Mar 2014 10:01:56 -0700, John Larkin
>>><jla...@highlandtechnology.com> wrote:
>>>
>>>>On Sun, 23 Mar 2014 20:28:01 -0400, k...@attt.bizz wrote:
>>>>
>>>
>>>>>
>>>>>On the more dense boards, I sometimes have the CAD guy renumber them
>>>>>from side to side starting at 1 on the top and 500 on the bottom. That
>>>>>has its issues, too.
>>>>
>>>>We always resequence. It makes the parts easier to find on the board.
>>>
>>>How can you do sensiblly annotated multichannel design without
>>>hierarchy in the schematic?
>>
>>If there are 48 channels, all 48 channels appear on the schematic.
>>Nice and flat.
>
>Ick. How do you guarantee that any changes make it into all 48?

We check things, like on all the other sheets of the schematic.

The vast majority of our first articles, Rev A, work and can be sold.
We don't prototype.

On this 48 channel thing, we share some parts between channels, like
some optoisolators and some pulse transformers. If the top level sch
had a block per channel, how would you share those parts? Pull them
out of the blocks?

>
>>Every net has a unique net name, and every part has a
>>unique refdes, which is handy.
>
>Hierarchy doesn't preclude any of the above, in any way.
>
>>What do you mean by "sensibly annotated"?
>>
>>Parts have ref designators on the schematic and the board. Last part
>>of the layout, they are geometrically resequenced on the PCB for ease
>>of physical location, and back annotated to the schematic.
>>
>>Seems to work.
>>
>Except when it doesn't.

Seems to work. I can't recall a case where we changed some channels
but forgot to change others.

[Fred Bartoli]

Nah, put a grouping property in your opto, then descend into each page of
your yeahrarchy and set the group property accordingly.
That's all.


--
Thanks,
Fred.