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Digital Frequency/Phase Comparator (DFPC) - better than 4046 PH.C. II ?
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Glenn
Jan 15, 2013, 8:14:31 AM1/15/13
to
Some time ago I found this on the www:
Atmel, Digital Frequency/Phase Comparator (DFPC):
http://www.zmitac.aei.polsl.pl/Electronics_Firm_Docs/ATMEL/Atmel/acrobat/doc0475.pdf
(with circuit schematic)
Is this DFPC (using 4000 or 74HC series logic) better that the phase
comparators used in e.g. 4046, 74HC7046, 74HC9046?
4046 schematic on page 5:
http://www.ti.com/general/docs/lit/getliterature.tsp?literatureNumber=scha002a&fileType=pdf
When was the DFPC invented? Is it free to the DFPC for any purpose?
Glenn
Atmel, Digital Frequency/Phase Comparator (DFPC):
http://www.zmitac.aei.polsl.pl/Electronics_Firm_Docs/ATMEL/Atmel/acrobat/doc0475.pdf
(with circuit schematic)
Is this DFPC (using 4000 or 74HC series logic) better that the phase
comparators used in e.g. 4046, 74HC7046, 74HC9046?
4046 schematic on page 5:
http://www.ti.com/general/docs/lit/getliterature.tsp?literatureNumber=scha002a&fileType=pdf
When was the DFPC invented? Is it free to the DFPC for any purpose?
Glenn
Jan Panteltje
Jan 15, 2013, 11:01:17 AM1/15/13
to
On a sunny day (Tue, 15 Jan 2013 14:14:31 +0100) it happened Glenn
<glen...@gmail.com> wrote in <50f55638$0$283$1472...@news.sunsite.dk>:
Yes I think it is better, as it goes to phase comparator mode after frequency lock.
The 4046 keeps switching back and forward.
Verilog example:
I dunno, but I impemented it in FPGA just a while back, with 2 diodes to drive a 1.5 GHz osc
in PLL mode.
I have seen it in many places...
http://control2.net/m/modeling-phase-locked-loops-using-verilog-w3598.html
<glen...@gmail.com> wrote in <50f55638$0$283$1472...@news.sunsite.dk>:
The 4046 keeps switching back and forward.
Verilog example:
I dunno, but I impemented it in FPGA just a while back, with 2 diodes to drive a 1.5 GHz osc
in PLL mode.
I have seen it in many places...
http://control2.net/m/modeling-phase-locked-loops-using-verilog-w3598.html
Phil Hobbs
Jan 15, 2013, 12:11:02 PM1/15/13
to
The two-output (Motorola) variant avoids the dead zone of the 4046 type
PFD, at the price of a bit of extra ripple.
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics
160 North State Road #203
Briarcliff Manor NY 10510
hobbs at electrooptical dot net
http://electrooptical.net
Jim Thompson
Jan 15, 2013, 12:15:23 PM1/15/13
to
On Tue, 15 Jan 2013 12:11:02 -0500, Phil Hobbs
<pcdhSpamM...@electrooptical.net> wrote:
>On 01/15/2013 08:14 AM, Glenn wrote:
>> Some time ago I found this on the www:
>>
>> Atmel, Digital Frequency/Phase Comparator (DFPC):
>> http://www.zmitac.aei.polsl.pl/Electronics_Firm_Docs/ATMEL/Atmel/acrobat/doc0475.pdf
>>
>> (with circuit schematic)
>>
>> Is this DFPC (using 4000 or 74HC series logic) better that the phase
>> comparators used in e.g. 4046, 74HC7046, 74HC9046?
>>
>> 4046 schematic on page 5:
>> http://www.ti.com/general/docs/lit/getliterature.tsp?literatureNumber=scha002a&fileType=pdf
>>
>>
>> When was the DFPC invented? Is it free to the DFPC for any purpose?
>
>It was invented slightly before dirt--patents long expired.
Yep, That's Ron Treadway's "9-gate-wonder" in our MC4044 part.
<pcdhSpamM...@electrooptical.net> wrote:
>On 01/15/2013 08:14 AM, Glenn wrote:
>> Some time ago I found this on the www:
>>
>> Atmel, Digital Frequency/Phase Comparator (DFPC):
>> http://www.zmitac.aei.polsl.pl/Electronics_Firm_Docs/ATMEL/Atmel/acrobat/doc0475.pdf
>>
>> (with circuit schematic)
>>
>> Is this DFPC (using 4000 or 74HC series logic) better that the phase
>> comparators used in e.g. 4046, 74HC7046, 74HC9046?
>>
>> 4046 schematic on page 5:
>> http://www.ti.com/general/docs/lit/getliterature.tsp?literatureNumber=scha002a&fileType=pdf
>>
>>
>> When was the DFPC invented? Is it free to the DFPC for any purpose?
>
>It was invented slightly before dirt--patents long expired.
>
>The two-output (Motorola) variant avoids the dead zone of the 4046 type
>PFD, at the price of a bit of extra ripple.
>
>Cheers
>
>Phil Hobbs
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
Tim Wescott
Jan 15, 2013, 12:29:49 PM1/15/13
to
On Tue, 15 Jan 2013 12:11:02 -0500, Phil Hobbs wrote:
> On 01/15/2013 08:14 AM, Glenn wrote:
>> Some time ago I found this on the www:
>>
>> Atmel, Digital Frequency/Phase Comparator (DFPC):
>> http://www.zmitac.aei.polsl.pl/Electronics_Firm_Docs/ATMEL/Atmel/
acrobat/doc0475.pdf
>>
>> (with circuit schematic)
>>
>> Is this DFPC (using 4000 or 74HC series logic) better that the phase
>> comparators used in e.g. 4046, 74HC7046, 74HC9046?
>>
>> 4046 schematic on page 5:
>> http://www.ti.com/general/docs/lit/getliterature.tsp?
literatureNumber=scha002a&fileType=pdf
>>
>>
>> When was the DFPC invented? Is it free to the DFPC for any purpose?
>
> It was invented slightly before dirt--patents long expired.
>
> The two-output (Motorola) variant avoids the dead zone of the 4046 type
> PFD, at the price of a bit of extra ripple.
>
> Cheers
>
> Phil Hobbs
I still wish that someone would make a TinyLogic part with just a 4046-
> On 01/15/2013 08:14 AM, Glenn wrote:
>> Some time ago I found this on the www:
>>
>> Atmel, Digital Frequency/Phase Comparator (DFPC):
>> http://www.zmitac.aei.polsl.pl/Electronics_Firm_Docs/ATMEL/Atmel/
acrobat/doc0475.pdf
>>
>> (with circuit schematic)
>>
>> Is this DFPC (using 4000 or 74HC series logic) better that the phase
>> comparators used in e.g. 4046, 74HC7046, 74HC9046?
>>
>> 4046 schematic on page 5:
>> http://www.ti.com/general/docs/lit/getliterature.tsp?
literatureNumber=scha002a&fileType=pdf
>>
>>
>> When was the DFPC invented? Is it free to the DFPC for any purpose?
>
> It was invented slightly before dirt--patents long expired.
>
> The two-output (Motorola) variant avoids the dead zone of the 4046 type
> PFD, at the price of a bit of extra ripple.
>
> Cheers
>
> Phil Hobbs
style phase comparator. While I admit that mostly when I do something
with a 4046 it's to get it out of the circuit and replace it with code in
a processor, I do sometimes design them in. When I do, half the time
that I shove a 4046 _into_ a schematic, it's with the intention of using
the phase comparator 2 and nothing else.
Lessee -- VDD, VSS, in1, in2, out -- yup, that fits...
--
My liberal friends think I'm a conservative kook.
My conservative friends think I'm a liberal kook.
Why am I not happy that they have found common ground?
Tim Wescott, Communications, Control, Circuits & Software
http://www.wescottdesign.com
John Larkin
Jan 15, 2013, 12:38:43 PM1/15/13
to
I sometimes use an xor gate as a phase detector, or a d-flop as a bang-bang PD,
but only for narrowband (VCXO) things where pull-in range isn't a problem.
We put a nice no-deadband PFD into an FPGA now and then.
--
John Larkin Highland Technology Inc
www.highlandtechnology.com jlarkin at highlandtechnology dot com
Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Custom timing and laser controllers
Photonics and fiberoptic TTL data links
VME analog, thermocouple, LVDT, synchro, tachometer
Multichannel arbitrary waveform generators
Jim Thompson
Jan 15, 2013, 1:20:33 PM1/15/13
to
VDD, VSS, IN1, IN2, OUT and a PIN for a resistor to ground to set the
output current (Internal BandGap).
Tim Wescott
Jan 15, 2013, 1:34:28 PM1/15/13
to
be beat (they're interesting critters to write in software -- you have to
make sure you're sampling fast enough, and there are some subtle failure
modes if you're not paying close attention).
> We put a nice no-deadband PFD into an FPGA now and then.
Phil Hobbs
Jan 15, 2013, 2:17:05 PM1/15/13
to
diode-bridge PD. Alternatively you can put a bit of positive feedback
on the (integrating) loop amp, and make it sweep automatically when the
loop unlocks, but PD2 pulls in faster.
You do need to get a 90 degree phase shift from someplace, because PFDs
want to servo at 0 or pi. However, you have to do that anyway if you
want a lock detector, and a Johnson counter is usually easy.
The nice thing about XOR and diode-bridge devices is that missing a
cycle or two doesn't cause you to lose lock the way it does with a PFD.
Gerhard Hoffmann
Jan 15, 2013, 4:06:33 PM1/15/13
to
Am 15.01.2013 18:38, schrieb John Larkin:
...
> 4046's have a nasty deadband.
The 9046 is said to be better, but I have not used it personally.
> I sometimes use an xor gate as a phase detector, or a d-flop as a bang-bang PD,
> but only for narrowband (VCXO) things where pull-in range isn't a problem.
>
> We put a nice no-deadband PFD into an FPGA now and then.
The AD9901 is a nice alternative. It moves the deadband to the
extremes of the phase range, where nobody is molested.
I recently rewrote it in VHDL, but we decided to stay with
a FLL, so it is not needed anymore.
Maybe I'll test it just for fun in a corner of a small Coolrunner..
regards, Gerhard
...
>>> The two-output (Motorola) variant avoids the dead zone of the 4046 type
>>> PFD, at the price of a bit of extra ripple.
>>>
>>> Cheers
>>>
>>> Phil Hobbs
>>
>> I still wish that someone would make a TinyLogic part with just a 4046-
>> style phase comparator. While I admit that mostly when I do something
>> with a 4046 it's to get it out of the circuit and replace it with code in
>> a processor, I do sometimes design them in. When I do, half the time
>> that I shove a 4046 _into_ a schematic, it's with the intention of using
>> the phase comparator 2 and nothing else.
>>
>> Lessee -- VDD, VSS, in1, in2, out -- yup, that fits...
>
I'd like that PFD2, too! In SC-70 !!!
>>> PFD, at the price of a bit of extra ripple.
>>>
>>> Cheers
>>>
>>> Phil Hobbs
>>
>> I still wish that someone would make a TinyLogic part with just a 4046-
>> style phase comparator. While I admit that mostly when I do something
>> with a 4046 it's to get it out of the circuit and replace it with code in
>> a processor, I do sometimes design them in. When I do, half the time
>> that I shove a 4046 _into_ a schematic, it's with the intention of using
>> the phase comparator 2 and nothing else.
>>
>> Lessee -- VDD, VSS, in1, in2, out -- yup, that fits...
>
> 4046's have a nasty deadband.
> I sometimes use an xor gate as a phase detector, or a d-flop as a bang-bang PD,
> but only for narrowband (VCXO) things where pull-in range isn't a problem.
>
> We put a nice no-deadband PFD into an FPGA now and then.
extremes of the phase range, where nobody is molested.
I recently rewrote it in VHDL, but we decided to stay with
a FLL, so it is not needed anymore.
Maybe I'll test it just for fun in a corner of a small Coolrunner..
regards, Gerhard
Jim Thompson
Jan 15, 2013, 4:41:43 PM1/15/13
to
On Tue, 15 Jan 2013 14:17:05 -0500, Phil Hobbs
<pcdhSpamM...@electrooptical.net> wrote:
[snip]
data. They just coast on a missing transition...
http://www.analog-innovations.com/SED/ShiftRegisterPLL.pdf
I've also used this scheme on a satellite receiver.
You can also get fancy...
http://www.analog-innovations.com/SED/SyncRingOsc.pdf
I've done a modification of this scheme to control maximum amount of
phase "jerk" _and_ also lock-in gap.
<pcdhSpamM...@electrooptical.net> wrote:
[snip]
>
>I mostly use PD2 as an acquisition aid for a narrowband loop with a
>diode-bridge PD. Alternatively you can put a bit of positive feedback
>on the (integrating) loop amp, and make it sweep automatically when the
>loop unlocks, but PD2 pulls in faster.
>
>You do need to get a 90 degree phase shift from someplace, because PFDs
>want to servo at 0 or pi. However, you have to do that anyway if you
>want a lock detector, and a Johnson counter is usually easy.
>
>The nice thing about XOR and diode-bridge devices is that missing a
>cycle or two doesn't cause you to lose lock the way it does with a PFD.
>
>Cheers
>
>Phil Hobbs
I'm fond of using a crystal-clocked shift-register for extracting
>I mostly use PD2 as an acquisition aid for a narrowband loop with a
>diode-bridge PD. Alternatively you can put a bit of positive feedback
>on the (integrating) loop amp, and make it sweep automatically when the
>loop unlocks, but PD2 pulls in faster.
>
>You do need to get a 90 degree phase shift from someplace, because PFDs
>want to servo at 0 or pi. However, you have to do that anyway if you
>want a lock detector, and a Johnson counter is usually easy.
>
>The nice thing about XOR and diode-bridge devices is that missing a
>cycle or two doesn't cause you to lose lock the way it does with a PFD.
>
>Cheers
>
>Phil Hobbs
data. They just coast on a missing transition...
http://www.analog-innovations.com/SED/ShiftRegisterPLL.pdf
I've also used this scheme on a satellite receiver.
You can also get fancy...
http://www.analog-innovations.com/SED/SyncRingOsc.pdf
I've done a modification of this scheme to control maximum amount of
phase "jerk" _and_ also lock-in gap.
John Larkin
Jan 15, 2013, 4:44:27 PM1/15/13
to
On Tue, 15 Jan 2013 22:06:33 +0100, Gerhard Hoffmann <dk...@arcor.de>
wrote:
We use the 9901 in one of our ECL delay generators. It's an expensive
power hog, but we get super low jitter.
Rob, my FPGA guy, has a nice PFD design. It uses two external diodes
into a filter/opamp (my idea) so the FPGA outputs swing hard
rail-to-rail, without any tristate charge-pumpy tricks.
--
John Larkin Highland Technology, Inc
jlarkin at highlandtechnology dot com
http://www.highlandtechnology.com
Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Custom laser drivers and controllers
wrote:
power hog, but we get super low jitter.
Rob, my FPGA guy, has a nice PFD design. It uses two external diodes
into a filter/opamp (my idea) so the FPGA outputs swing hard
rail-to-rail, without any tristate charge-pumpy tricks.
--
John Larkin Highland Technology, Inc
jlarkin at highlandtechnology dot com
Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Photonics and fiberoptic TTL data links
VME thermocouple, LVDT, synchro acquisition and simulation
Glenn
Jan 16, 2013, 1:19:26 AM1/16/13
to
On 15/01/13 22.06, Gerhard Hoffmann wrote:
...
> I'd like that PFD2, too! In SC-70 !!!
...
...
> I'd like that PFD2, too! In SC-70 !!!
Is there a very small cheap FPGA where a PFD2 can be implemented?
The smallest I could find at digikey and cheapest ($10 ! ) had 64 pins.
-
What about a universal 16/24/28/32square pin 74HC/74LVC/... FPGA - burn
your own (a)sync counter/PFD2/PLL/NOR/NAND/NOT/LCD-driver/... - and of
course more complicated things?
-
It is even possible to buy single gates today - example:
SN74AUC1G08DBVR - 74AUC1G08 - a dual input AND Gate:
http://www.digikey.com/product-detail/en/SN74AUC1G08DBVR/296-13170-1-ND/484304
Glenn
Gerhard Hoffmann
Jan 16, 2013, 3:33:46 AM1/16/13
to
Am 16.01.2013 07:19, schrieb Glenn:
> On 15/01/13 22.06, Gerhard Hoffmann wrote:
> ...
>> I'd like that PFD2, too! In SC-70 !!!
> ...
>
> Is there a very small cheap FPGA where a PFD2 can be implemented?
>
> The smallest I could find at digikey and cheapest ($10 ! ) had 64 pins.
>
<http://www.digikey.de/product-detail/de/XC2C64A-5VQG44C/122-1420-ND/966601>
> On 15/01/13 22.06, Gerhard Hoffmann wrote:
> ...
>> I'd like that PFD2, too! In SC-70 !!!
> ...
>
> Is there a very small cheap FPGA where a PFD2 can be implemented?
>
> The smallest I could find at digikey and cheapest ($10 ! ) had 64 pins.
>
Probably needs another SC-70 for the 1V8 core voltage.
Gerhard
Allan Herriman
Jan 16, 2013, 5:57:47 AM1/16/13
to
On Tue, 15 Jan 2013 22:06:33 +0100, Gerhard Hoffmann wrote:
> Am 15.01.2013 18:38, schrieb John Larkin:
>> 4046's have a nasty deadband.
>
> The 9046 is said to be better, but I have not used it personally.
The '9046 is definitely better. I have used it in SONET retiming PLLs.
> Am 15.01.2013 18:38, schrieb John Larkin:
>> 4046's have a nasty deadband.
>
> The 9046 is said to be better, but I have not used it personally.
For those not in the know, the logic in the PFD is the same as that in
the '4046, but the output is different. Instead of the hard P pullup and
N pulldown, there is a P pullup current source and an N pulldown current
sink. The currents are matched to perhaps 1% (although this is not
guaranteed in the datasheet).
The '9046 output Z is alway high, unlike that of the '4046 which is
modulated by the phase error.
Regards,
Allan
Tim Wescott
Jan 16, 2013, 1:04:36 PM1/16/13
to
On Wed, 16 Jan 2013 07:19:26 +0100, Glenn wrote:
> On 15/01/13 22.06, Gerhard Hoffmann wrote: ...
>> I'd like that PFD2, too! In SC-70 !!!
> ...
>
> Is there a very small cheap FPGA where a PFD2 can be implemented?
>
> The smallest I could find at digikey and cheapest ($10 ! ) had 64 pins.
>
> -
>
> What about a universal 16/24/28/32square pin 74HC/74LVC/... FPGA - burn
> your own (a)sync counter/PFD2/PLL/NOR/NAND/NOT/LCD-driver/... - and of
> course more complicated things?
>
(snip)
> On 15/01/13 22.06, Gerhard Hoffmann wrote: ...
>> I'd like that PFD2, too! In SC-70 !!!
> ...
>
> Is there a very small cheap FPGA where a PFD2 can be implemented?
>
> The smallest I could find at digikey and cheapest ($10 ! ) had 64 pins.
>
> -
>
> What about a universal 16/24/28/32square pin 74HC/74LVC/... FPGA - burn
> your own (a)sync counter/PFD2/PLL/NOR/NAND/NOT/LCD-driver/... - and of
> course more complicated things?
>
You're thinking of PLDs. You can get really old ones, on the expensive
end of the price curve, from DigiKey for $5-ish. New, 48-pin ones are
more like $2-ish in small quantities.
lang...@fonz.dk
Jan 16, 2013, 5:52:45 PM1/16/13
to
On Jan 16, 7:04 pm, Tim Wescott <t...@seemywebsite.com> wrote:
> On Wed, 16 Jan 2013 07:19:26 +0100, Glenn wrote:
> > On 15/01/13 22.06, Gerhard Hoffmann wrote: ...
> >> I'd like that PFD2, too! In SC-70 !!!
> > ...
>
> > Is there a very small cheap FPGA where a PFD2 can be implemented?
>
> > The smallest I could find at digikey and cheapest ($10 ! ) had 64 pins.
>
> > -
>
> > What about a universal 16/24/28/32square pin 74HC/74LVC/... FPGA - burn
> > your own (a)sync counter/PFD2/PLL/NOR/NAND/NOT/LCD-driver/... - and of
> > course more complicated things?
>
> (snip)
>
> You're thinking of PLDs. You can get really old ones, on the expensive
> end of the price curve, from DigiKey for $5-ish. New, 48-pin ones are
> more like $2-ish in small quantities.
>
a XC9536XL-10VQG44C at digikey is 1.18$ in ones
> On Wed, 16 Jan 2013 07:19:26 +0100, Glenn wrote:
> > On 15/01/13 22.06, Gerhard Hoffmann wrote: ...
> >> I'd like that PFD2, too! In SC-70 !!!
> > ...
>
> > Is there a very small cheap FPGA where a PFD2 can be implemented?
>
> > The smallest I could find at digikey and cheapest ($10 ! ) had 64 pins.
>
> > -
>
> > What about a universal 16/24/28/32square pin 74HC/74LVC/... FPGA - burn
> > your own (a)sync counter/PFD2/PLL/NOR/NAND/NOT/LCD-driver/... - and of
> > course more complicated things?
>
> (snip)
>
> You're thinking of PLDs. You can get really old ones, on the expensive
> end of the price curve, from DigiKey for $5-ish. New, 48-pin ones are
> more like $2-ish in small quantities.
>
-Lasse
lang...@fonz.dk
Jan 16, 2013, 6:04:23 PM1/16/13
to
On Jan 15, 10:44 pm, John Larkin <jlar...@highlandtechnology.com>
wrote:
what would be the advantage of using diodes instead of just a tristate
output
or two ?
-Lasse
wrote:
output
or two ?
-Lasse
John Larkin
Jan 16, 2013, 7:24:27 PM1/16/13
to
On Wed, 16 Jan 2013 15:04:23 -0800 (PST), "lang...@fonz.dk"
<lang...@fonz.dk> wrote:
>On Jan 15, 10:44锟絧m, John Larkin <jlar...@highlandtechnology.com>
of the tristate things. The UP and DOWN outputs each slam
rail-to-rail, fast. We control all the time constants, independent of
the silicon.
More importantly, we can program a bit of overlap on the two outputs
and avoid a deadband like the 4046 type charge pumps have. The 4046
deadband can cause ghastly phase noise and jitter.
<lang...@fonz.dk> wrote:
>On Jan 15, 10:44锟絧m, John Larkin <jlar...@highlandtechnology.com>
>wrote:
>> On Tue, 15 Jan 2013 22:06:33 +0100, Gerhard Hoffmann <dk...@arcor.de>
>> wrote:
>>
>>
>>
>>
>>
>>
>>
>>
>>
>> >Am 15.01.2013 18:38, schrieb John Larkin:
>>
>> >...
>> >>>> The two-output (Motorola) variant avoids the dead zone of the 4046 type
>> >>>> PFD, at the price of a bit of extra ripple.
>>
>> >>>> Cheers
>>
>> >>>> Phil Hobbs
>>
>> >>> I still wish that someone would make a TinyLogic part with just a 4046-
>> >>> style phase comparator. 锟絎hile I admit that mostly when I do something
>> On Tue, 15 Jan 2013 22:06:33 +0100, Gerhard Hoffmann <dk...@arcor.de>
>> wrote:
>>
>>
>>
>>
>>
>>
>>
>>
>>
>> >Am 15.01.2013 18:38, schrieb John Larkin:
>>
>> >...
>> >>>> The two-output (Motorola) variant avoids the dead zone of the 4046 type
>> >>>> PFD, at the price of a bit of extra ripple.
>>
>> >>>> Cheers
>>
>> >>>> Phil Hobbs
>>
>> >>> I still wish that someone would make a TinyLogic part with just a 4046-
>> >>> with a 4046 it's to get it out of the circuit and replace it with code in
>> >>> a processor, I do sometimes design them in. 锟絎hen I do, half the time
>> >>> that I shove a 4046 _into_ a schematic, it's with the intention of using
>> >>> the phase comparator 2 and nothing else.
>>
>> >>> Lessee -- VDD, VSS, in1, in2, out -- yup, that fits...
>>
>> >I'd like that PFD2, too! 锟絀n SC-70 !!!
>> >>> the phase comparator 2 and nothing else.
>>
>> >>> Lessee -- VDD, VSS, in1, in2, out -- yup, that fits...
>>
>>
>> >> 4046's have a nasty deadband.
>>
>> >The 9046 is said to be better, but I have not used it personally.
>>
>> >> I sometimes use an xor gate as a phase detector, or a d-flop as a bang-bang PD,
>> >> but only for narrowband (VCXO) things where pull-in range isn't a problem.
>>
>> >> We put a nice no-deadband PFD into an FPGA now and then.
>>
>> >The AD9901 is a nice alternative. It moves the deadband to the
>> >extremes of the phase range, where nobody is molested.
>>
>> >I recently rewrote it in VHDL, but we decided to stay with
>> >a FLL, so it is not needed anymore.
>> >Maybe I'll test it just for fun in a corner of a small Coolrunner..
>>
>> >regards, Gerhard
>>
>> We use the 9901 in one of our ECL delay generators. It's an expensive
>> power hog, but we get super low jitter.
>>
>> Rob, my FPGA guy, has a nice PFD design. It uses two external diodes
>> into a filter/opamp (my idea) so the FPGA outputs swing hard
>> rail-to-rail, without any tristate charge-pumpy tricks.
>>
>
>what would be the advantage of using diodes instead of just a tristate
>output
>or two ?
>
One is that we don't care about the subtleties (drive strength, speed)
>> >> 4046's have a nasty deadband.
>>
>> >The 9046 is said to be better, but I have not used it personally.
>>
>> >> I sometimes use an xor gate as a phase detector, or a d-flop as a bang-bang PD,
>> >> but only for narrowband (VCXO) things where pull-in range isn't a problem.
>>
>> >> We put a nice no-deadband PFD into an FPGA now and then.
>>
>> >The AD9901 is a nice alternative. It moves the deadband to the
>> >extremes of the phase range, where nobody is molested.
>>
>> >I recently rewrote it in VHDL, but we decided to stay with
>> >a FLL, so it is not needed anymore.
>> >Maybe I'll test it just for fun in a corner of a small Coolrunner..
>>
>> >regards, Gerhard
>>
>> We use the 9901 in one of our ECL delay generators. It's an expensive
>> power hog, but we get super low jitter.
>>
>> Rob, my FPGA guy, has a nice PFD design. It uses two external diodes
>> into a filter/opamp (my idea) so the FPGA outputs swing hard
>> rail-to-rail, without any tristate charge-pumpy tricks.
>>
>
>what would be the advantage of using diodes instead of just a tristate
>output
>or two ?
>
of the tristate things. The UP and DOWN outputs each slam
rail-to-rail, fast. We control all the time constants, independent of
the silicon.
More importantly, we can program a bit of overlap on the two outputs
and avoid a deadband like the 4046 type charge pumps have. The 4046
deadband can cause ghastly phase noise and jitter.
o pere o
Jan 17, 2013, 7:58:52 AM1/17/13
to
in a PLCC package, such as Altera's EPM3064ALC44-10N for 1.78 EUR at
Digikey. I gues this is the smallest beast.
Pere
rickman
Jan 17, 2013, 12:01:33 AM1/17/13
to
Lattice that come in low pin count packages, but not so easy to use,
small pitch BGAs as small as 36 pins, 2.5 mm sq. They are targeted to
the mobile device market so they are pretty cheap, I think they are well
under $5 in quantity. iCE40xxxx, 1.2 volt core
Rick
lang...@fonz.dk
Jan 17, 2013, 4:18:08 PM1/17/13
to
On Jan 17, 1:24 am, John Larkin <jlar...@highlandtechnology.com>
wrote:
> On Wed, 16 Jan 2013 15:04:23 -0800 (PST), "langw...@fonz.dk"
>
>
>
>
>
>
>
>
>
> <langw...@fonz.dk> wrote:
> >On Jan 15, 10:44 pm, John Larkin <jlar...@highlandtechnology.com>
for
data-to-pad and tristate-to-pad is exactly the same, so whether you
drive
the data or the tristate pin the output transistor must be doing the
same
you get the same "slam to the rail"
>
> More importantly, we can program a bit of overlap on the two outputs
> and avoid a deadband like the 4046 type charge pumps have. The 4046
> deadband can cause ghastly phase noise and jitter.
>
you could do the same with two outputs and no diodes
something like this:
assign pc2_p = up ? 1'b1 : 1'bz;
assign pc2_n = down ? 1'b0 : 1'bz;
-Lasse
wrote:
> On Wed, 16 Jan 2013 15:04:23 -0800 (PST), "langw...@fonz.dk"
>
>
>
>
>
>
>
>
>
> <langw...@fonz.dk> wrote:
> >On Jan 15, 10:44 pm, John Larkin <jlar...@highlandtechnology.com>
> >wrote:
> >> On Tue, 15 Jan 2013 22:06:33 +0100, Gerhard Hoffmann <dk...@arcor.de>
> >> wrote:
>
> >> >Am 15.01.2013 18:38, schrieb John Larkin:
>
> >> >...
> >> >>>> The two-output (Motorola) variant avoids the dead zone of the 4046 type
> >> >>>> PFD, at the price of a bit of extra ripple.
>
> >> >>>> Cheers
>
> >> >>>> Phil Hobbs
>
> >> >>> I still wish that someone would make a TinyLogic part with just a 4046-
> >> >>> style phase comparator. While I admit that mostly when I do something
> >> On Tue, 15 Jan 2013 22:06:33 +0100, Gerhard Hoffmann <dk...@arcor.de>
> >> wrote:
>
> >> >Am 15.01.2013 18:38, schrieb John Larkin:
>
> >> >...
> >> >>>> The two-output (Motorola) variant avoids the dead zone of the 4046 type
> >> >>>> PFD, at the price of a bit of extra ripple.
>
> >> >>>> Cheers
>
> >> >>>> Phil Hobbs
>
> >> >>> I still wish that someone would make a TinyLogic part with just a 4046-
> >> >>> with a 4046 it's to get it out of the circuit and replace it with code in
> >> >>> a processor, I do sometimes design them in. When I do, half the time
> >> >>> that I shove a 4046 _into_ a schematic, it's with the intention of using
> >> >>> the phase comparator 2 and nothing else.
>
> >> >>> Lessee -- VDD, VSS, in1, in2, out -- yup, that fits...
>
> >> >I'd like that PFD2, too! In SC-70 !!!
> >> >>> the phase comparator 2 and nothing else.
>
> >> >>> Lessee -- VDD, VSS, in1, in2, out -- yup, that fits...
>
>
> >> >> 4046's have a nasty deadband.
>
> >> >The 9046 is said to be better, but I have not used it personally.
>
> >> >> I sometimes use an xor gate as a phase detector, or a d-flop as a bang-bang PD,
> >> >> but only for narrowband (VCXO) things where pull-in range isn't a problem.
>
> >> >> We put a nice no-deadband PFD into an FPGA now and then.
>
> >> >The AD9901 is a nice alternative. It moves the deadband to the
> >> >extremes of the phase range, where nobody is molested.
>
> >> >I recently rewrote it in VHDL, but we decided to stay with
> >> >a FLL, so it is not needed anymore.
> >> >Maybe I'll test it just for fun in a corner of a small Coolrunner..
>
> >> >regards, Gerhard
>
> >> We use the 9901 in one of our ECL delay generators. It's an expensive
> >> power hog, but we get super low jitter.
>
> >> Rob, my FPGA guy, has a nice PFD design. It uses two external diodes
> >> into a filter/opamp (my idea) so the FPGA outputs swing hard
> >> rail-to-rail, without any tristate charge-pumpy tricks.
>
> >what would be the advantage of using diodes instead of just a tristate
> >output
> >or two ?
>
> One is that we don't care about the subtleties (drive strength, speed)
> of the tristate things. The UP and DOWN outputs each slam
> rail-to-rail, fast. We control all the time constants, independent of
> the silicon.
if you look at the timing spec for a xilinx cmos output the numbers
> >> >> 4046's have a nasty deadband.
>
> >> >The 9046 is said to be better, but I have not used it personally.
>
> >> >> I sometimes use an xor gate as a phase detector, or a d-flop as a bang-bang PD,
> >> >> but only for narrowband (VCXO) things where pull-in range isn't a problem.
>
> >> >> We put a nice no-deadband PFD into an FPGA now and then.
>
> >> >The AD9901 is a nice alternative. It moves the deadband to the
> >> >extremes of the phase range, where nobody is molested.
>
> >> >I recently rewrote it in VHDL, but we decided to stay with
> >> >a FLL, so it is not needed anymore.
> >> >Maybe I'll test it just for fun in a corner of a small Coolrunner..
>
> >> >regards, Gerhard
>
> >> We use the 9901 in one of our ECL delay generators. It's an expensive
> >> power hog, but we get super low jitter.
>
> >> Rob, my FPGA guy, has a nice PFD design. It uses two external diodes
> >> into a filter/opamp (my idea) so the FPGA outputs swing hard
> >> rail-to-rail, without any tristate charge-pumpy tricks.
>
> >what would be the advantage of using diodes instead of just a tristate
> >output
> >or two ?
>
> One is that we don't care about the subtleties (drive strength, speed)
> of the tristate things. The UP and DOWN outputs each slam
> rail-to-rail, fast. We control all the time constants, independent of
> the silicon.
for
data-to-pad and tristate-to-pad is exactly the same, so whether you
drive
the data or the tristate pin the output transistor must be doing the
same
you get the same "slam to the rail"
>
> More importantly, we can program a bit of overlap on the two outputs
> and avoid a deadband like the 4046 type charge pumps have. The 4046
> deadband can cause ghastly phase noise and jitter.
>
something like this:
assign pc2_p = up ? 1'b1 : 1'bz;
assign pc2_n = down ? 1'b0 : 1'bz;
-Lasse
John Larkin
Jan 17, 2013, 4:51:59 PM1/17/13
to
>>
>> More importantly, we can program a bit of overlap on the two outputs
>> and avoid a deadband like the 4046 type charge pumps have. The 4046
>> deadband can cause ghastly phase noise and jitter.
>>
>
>you could do the same with two outputs and no diodes
>
>something like this:
>
>assign pc2_p = up ? 1'b1 : 1'bz;
>assign pc2_n = down ? 1'b0 : 1'bz;
lang...@fonz.dk
Jan 17, 2013, 5:24:42 PM1/17/13
to
On Jan 17, 10:51 pm, John Larkin <jlar...@highlandtechnology.com>
wrote:
> On Thu, 17 Jan 2013 13:18:08 -0800 (PST), "langw...@fonz.dk"
with a single high-low-tristate output that would be impossible
>
>
>
> >> More importantly, we can program a bit of overlap on the two outputs
> >> and avoid a deadband like the 4046 type charge pumps have. The 4046
> >> deadband can cause ghastly phase noise and jitter.
>
> >you could do the same with two outputs and no diodes
>
> >something like this:
>
> >assign pc2_p = up ? 1'b1 : 1'bz;
> >assign pc2_n = down ? 1'b0 : 1'bz;
>
> You'd just connect the outputs?
>
yes, of course if you do up and down at the same time they
will fight each other but so will two push-pull outputs with
diodes unless I missed how you'd connect them
-Lasse
wrote:
> On Thu, 17 Jan 2013 13:18:08 -0800 (PST), "langw...@fonz.dk"
>
>
>
> >> More importantly, we can program a bit of overlap on the two outputs
> >> and avoid a deadband like the 4046 type charge pumps have. The 4046
> >> deadband can cause ghastly phase noise and jitter.
>
> >you could do the same with two outputs and no diodes
>
> >something like this:
>
> >assign pc2_p = up ? 1'b1 : 1'bz;
> >assign pc2_n = down ? 1'b0 : 1'bz;
>
> You'd just connect the outputs?
>
will fight each other but so will two push-pull outputs with
diodes unless I missed how you'd connect them
-Lasse
Jim Thompson
Jan 17, 2013, 5:42:13 PM1/17/13
to
lang...@fonz.dk
Jan 17, 2013, 6:02:30 PM1/17/13
to
On Jan 17, 11:42 pm, Jim Thompson <To-Email-Use-The-Envelope-I...@On-
My-Web-Site.com> wrote:
> On Thu, 17 Jan 2013 14:24:42 -0800 (PST), "langw...@fonz.dk"
I guess xilinx cmos outputs are also current controlled (ish)
at least they are described that way, being programmable with
2,4,6,8,12,16 or 24mA drive and fast or slow slew rate
-Lasse
My-Web-Site.com> wrote:
> On Thu, 17 Jan 2013 14:24:42 -0800 (PST), "langw...@fonz.dk"
at least they are described that way, being programmable with
2,4,6,8,12,16 or 24mA drive and fast or slow slew rate
-Lasse
John Larkin
Jan 17, 2013, 6:28:21 PM1/17/13
to
https://dl.dropbox.com/u/53724080/Circuits/Phase_Detector.jpg
The resistors on the left define the currents into the integrator.
This drives a VCXO. In non-PLL mode, we can turn on U4, turn the
integrator into a linear amp, and make the UP/DOWN signals into a
delta-sigma DAC, to open-loop tune the XO frequency.
lang...@fonz.dk
Jan 17, 2013, 7:07:34 PM1/17/13
to
On Jan 18, 12:28 am, John Larkin <jlar...@highlandtechnology.com>
wrote:
> On Thu, 17 Jan 2013 14:24:42 -0800 (PST), "langw...@fonz.dk"
I think the diodes are redundant if you made the two outputs push/
tristate - pull/tristate
and there would be diode voltage more for the resistors to set the
current
> This drives a VCXO. In non-PLL mode, we can turn on U4, turn the
> integrator into a linear amp, and make the UP/DOWN signals into a
> delta-sigma DAC, to open-loop tune the XO frequency.
is it really needed, wouldn't pwm/delta-sigma into the integrator work
just as good?
if it works for pll-mode it should work for non-pll mode, every thing
is the same it is just what controls the pins that changes
-Lasse
wrote:
> On Thu, 17 Jan 2013 14:24:42 -0800 (PST), "langw...@fonz.dk"
tristate - pull/tristate
and there would be diode voltage more for the resistors to set the
current
> This drives a VCXO. In non-PLL mode, we can turn on U4, turn the
> integrator into a linear amp, and make the UP/DOWN signals into a
> delta-sigma DAC, to open-loop tune the XO frequency.
just as good?
if it works for pll-mode it should work for non-pll mode, every thing
is the same it is just what controls the pins that changes
-Lasse
John Larkin
Jan 17, 2013, 8:44:41 PM1/17/13
to
VCXO frequency. In delta-sigma mode we turn the integrator into a
lowpass filter.
We do the dual-mode thing for instruments that can optionally lock to
an external 10 MHz reference. When they aren't locked to a reference
in PLL mode, we can set the VCXO frequency using a saved cal factor
and the delta-sigma thing.
josephkk
Jan 24, 2013, 12:26:35 AM1/24/13
to
an old 22v10. Just checked, they are still around, cool. It can do
several PFD2s and replace several packages of tiny logic at the same time.
?-)
Phil Hobbs
Jan 25, 2013, 8:13:45 PM1/25/13
to
IC-generated current sources--IME they tend to be many times the shot
noise, whereas a nice CMOS switch to a regulated power supply just looks
like a resistor.
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics
160 North State Road #203
+1 845 480 2058
Jim Thompson
Jan 25, 2013, 8:34:05 PM1/25/13
to
they've measured. My applications are considerably different from
yours... frequency synthesizers where the VCO is tank-type with
high-Q, or grotesques DLL's where I'm synchronizing digital clocks on
multiple chips.
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