ASIC Foundry with JFET Process?

[Jim Thompson]

I've had an inquiry from a potential chip design customer that seeks
to find an ASIC foundry with a process that has a good low-noise JFET.

I'm having trouble verifying X-Fab's XB-06 JFET because the Spice
model provided shows an ugly behavior relative to substrate
potential... i.e. it's not isolated in its own well.

Any lurkers here from other foundries, or anyone knowing of a suitable
process (*), please contact me directly.

Thanks!

(*) +3.3V, -2V supplies operation is desirable.

...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| San Tan Valley, AZ 85142 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I'm looking for work... see my website.

[Phil Hobbs]

On 08/08/2016 03:33 PM, Jim Thompson wrote:
> I've had an inquiry from a potential chip design customer that seeks
> to find an ASIC foundry with a process that has a good low-noise JFET.
>
> I'm having trouble verifying X-Fab's XB-06 JFET because the Spice
> model provided shows an ugly behavior relative to substrate
> potential... i.e. it's not isolated in its own well.
>
> Any lurkers here from other foundries, or anyone knowing of a suitable
> process (*), please contact me directly.
>
> Thanks!
>
> (*) +3.3V, -2V supplies operation is desirable.
>
> ...Jim Thompson
>

Or better, post it to the NG for the benefit of everybody. JT's asking
for a commercial offering, not some hush-hush trade secret.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

[Jim Thompson]

On Mon, 8 Aug 2016 21:21:16 -0400, Phil Hobbs
<pcdhSpamM...@electrooptical.net> wrote:

>On 08/08/2016 03:33 PM, Jim Thompson wrote:
>> I've had an inquiry from a potential chip design customer that seeks
>> to find an ASIC foundry with a process that has a good low-noise JFET.
>>
>> I'm having trouble verifying X-Fab's XB-06 JFET because the Spice
>> model provided shows an ugly behavior relative to substrate
>> potential... i.e. it's not isolated in its own well.
>>
>> Any lurkers here from other foundries, or anyone knowing of a suitable
>> process (*), please contact me directly.
>>
>> Thanks!
>>
>> (*) +3.3V, -2V supplies operation is desirable.
>>
>> ...Jim Thompson
>>
>Or better, post it to the NG for the benefit of everybody. JT's asking
>for a commercial offering, not some hush-hush trade secret.
>
>Cheers
>
>Phil Hobbs

Yep. I'm sure you could make use of that same process ;-)

[Phil Hobbs]

>>Or better, post it to the NG for the benefit of everybody.  JT's asking
>>for a commercial offering, not some hush-hush trade secret.
>

>Yep.  I'm sure you could make use of that same process ;-)

Probably not, since my electronics work is divided between board-level and device-level stuff. I've never done an ASIC, though it would be fun one of these days.

I just think it's a bit unseemly to ask for help without being willing to share.

Cheers

Phil Hobbs

[Jim Thompson]

I didn't mean it that way... sometimes people don't want to post
publicly.

[Robert Baer]

Jim Thompson wrote:
> I've had an inquiry from a potential chip design customer that seeks
> to find an ASIC foundry with a process that has a good low-noise JFET.
>
> I'm having trouble verifying X-Fab's XB-06 JFET because the Spice
> model provided shows an ugly behavior relative to substrate
> potential... i.e. it's not isolated in its own well.
>
> Any lurkers here from other foundries, or anyone knowing of a suitable
> process (*), please contact me directly.
>
> Thanks!
>
> (*) +3.3V, -2V supplies operation is desirable.
>
> ...Jim Thompson

What about DI? Perfect isolation..

[Jim Thompson]

Company name that provides what I asked for?

[bill....@ieee.org]

On Wednesday, August 10, 2016 at 12:06:50 AM UTC+10, Jim Thompson wrote:
> On Tue, 09 Aug 2016 00:37:04 -0800, Robert Baer
> <rober...@localnet.com> wrote:
>
> >Jim Thompson wrote:
> >> I've had an inquiry from a potential chip design customer that seeks
> >> to find an ASIC foundry with a process that has a good low-noise JFET.
> >>
> >> I'm having trouble verifying X-Fab's XB-06 JFET because the Spice
> >> model provided shows an ugly behavior relative to substrate
> >> potential... i.e. it's not isolated in its own well.
> >>
> >> Any lurkers here from other foundries, or anyone knowing of a suitable
> >> process (*), please contact me directly.
> >>
> >> Thanks!
> >>
> >> (*) +3.3V, -2V supplies operation is desirable.

Analog Devices? Their process seems to include quiet FETs - but it does seem to be unusually elaborate.

If memory serves, the fancier processes that produced good FETs included ion-beam implantation, which is pretty exotic.

--
Bill Sloman, Sydney

[Steve Goldstein]

To the best of my knowledge ADI does not offer foundry services. I
suppose anything is possible if the volume is big enough, but it'd
have to be pretty big (many many many millions of dollars, probably)
for that to happen. I can't speak for the other biggies in the analog
space like LTC, TI, Maxim, but I'd be surprised if they offered
foundry access. That's a very different business model and requires a
very different customer support structure.

[Chris Jones]

I have heard of them desiging ASICs for people in return for NRE, which
could achieve a similar outcome under the right circumstances.

[Chris Jones]

Most CMOS is ion implanted IIRC, so not exactly exotic.

[Steve Goldstein]

Yes, in fact my product group at ADI frequently does ASICs. But it
usually takes more than simply NRE, there has to be a pretty big
purchase commitment behind it as well. An ASIC has to compete against
internally-generated products for development resources in a
non-foundry company so has to stand on its own legs as a business
proposition. Opportunity costs in any large non-foundry semiconductor
company set a pretty high bar for ASIC business.

Jim's been around a while and understands this, but people not
directly in the biz often don't. No insults intended.

[bill....@ieee.org]

It was more exotic back in the 1980's when I was working on electron-beam microfabricators - for Cambridge Instrument - and had occasional contact with people in the integrated circuit processing business.

Most modern CMOS processes might use ion-implantation at some stage in the process, but the original RCA and Motorola processes didn't seem to have done so.

--
Bill Sloman, Sydney

[Phil Hobbs]

>Most CMOS is ion implanted IIRC, so not exactly exotic.

They don't do litho with crayons anymore, either. ;)

Cheers

Phil Hobbs

[Jim Thompson]

Yep. The only "big name OEM" that I know of that does foundry work is
ON-Semi, but just their AMIS facility in Pocatello, doesn't have an
appropriate process.

My usual fab source is X-Fab. Their JFET has the back/body at
substrate... making it pretty worthless for low-noise amplifier use
:-(

[Jim Thompson]

That had its advantages ;-)

My Master's project had a JFET. I just drew what I wanted on a
quadrille pad and they (Motorola's layout guys) cut the Rubylith to
match... those were the good-ol-days... no grand
authorization-by-committee required to conduct an experiment... parts
out in three days ;-)

[Phil Hobbs]

On 08/10/2016 10:34 AM, Jim Thompson wrote:
> On Wed, 10 Aug 2016 07:20:45 -0700 (PDT), Phil Hobbs
> <pcdh...@gmail.com> wrote:
>
>>> Most CMOS is ion implanted IIRC, so not exactly exotic.
>>
>> They don't do litho with crayons anymore, either. ;)
>>
>> Cheers
>>
>> Phil Hobbs
>
> That had its advantages ;-)
>
> My Master's project had a JFET. I just drew what I wanted on a
> quadrille pad and they (Motorola's layout guys) cut the Rubylith to
> match... those were the good-ol-days... no grand
> authorization-by-committee required to conduct an experiment... parts
> out in three days ;-)
>
> ...Jim Thompson
>

I used to do a lot of my own processing too, back in my silicon
photonics days, but it was with a Leica e-beam writer with 30 nm minimum
feature size. Fun stuff, except that some of my run sheets had over 600
steps by the time I was done. (That included rework and so on, which I
had to do a fair amount of since I wasn't using what everybody else was,
and had to optimize it on my own.) One learns patience that way, for sure.

[bill....@ieee.org]

On Thursday, August 11, 2016 at 12:56:48 AM UTC+10, Phil Hobbs wrote:
> On 08/10/2016 10:34 AM, Jim Thompson wrote:
> > On Wed, 10 Aug 2016 07:20:45 -0700 (PDT), Phil Hobbs
> > <pcdh...@gmail.com> wrote:
> >
> >>> Most CMOS is ion implanted IIRC, so not exactly exotic.
> >>
> >> They don't do litho with crayons anymore, either. ;)
> >>
> >> Cheers
> >>
> >> Phil Hobbs
> >
> > That had its advantages ;-)
> >
> > My Master's project had a JFET. I just drew what I wanted on a
> > quadrille pad and they (Motorola's layout guys) cut the Rubylith to
> > match... those were the good-ol-days... no grand
> > authorization-by-committee required to conduct an experiment... parts
> > out in three days ;-)
> >
> > ...Jim Thompson
> >
>
> I used to do a lot of my own processing too, back in my silicon
> photonics days, but it was with a Leica e-beam writer with 30 nm minimum
> feature size.

Precisely when? I worked on the Cambridge Instruments EBMF 10.5, which did offer than kind of resolution. That had been incrementally developed over about a decade. Sometime around 1990, Philips gave up on their electron-beam microfabricator - which was a good machine, but needed more supported than they were set up to give - and sold it to Cambridge Instruments-Leica, who were happy to get a machine with fewer obsolete part problems and a non-wire-wrapped back-plane.

<snip>

--
Bill Sloman, Sydney