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How to wind a push-pull transformer?
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Piotr Wyderski
Aug 4, 2018, 3:46:37 AM8/4/18
to
I need to make a transformer for a push-pull converter.
The core is a 25.3/14.8/10 toroid made of N87, f=200kHz
(total, 100kHz per switch), Bmax=100mT, PRIMARY_Irms=10A,
PRIMARY_V_MAX=20V. This gives 2x5 turns and this low
value opens many options.
1. 5 turns, each turn close to one another, then the other 5 turns the
same way. Pros: thin winding, short supply wires.
2. 5 turns across the entire length of the core, then the other 5 turns
in between the first winding's gaps. Should be as thin as the first one,
better coupling. Cons: the center tap endings are far apart.
3. 5 turns of a twisted pair of Litz wires. Cons: much thick,
the center taps are far apart.
4. 5 turns of a twisted bundle of, say, 20 two-color wires,*
then the appropriate unbraiding.
5. It doesn't matter.
The second issue: does any standard current density matter at all
in the case of such short primary wires? Even 1mm^2 (total area
of the Litz wire/twisted bundle) results in negligible RDC and
the I^2R approach seems more scientific than any industrial I/area
rule of thumb. I should focus on minimizing RAC. Correct?
Best regards, Piotr
The core is a 25.3/14.8/10 toroid made of N87, f=200kHz
(total, 100kHz per switch), Bmax=100mT, PRIMARY_Irms=10A,
PRIMARY_V_MAX=20V. This gives 2x5 turns and this low
value opens many options.
1. 5 turns, each turn close to one another, then the other 5 turns the
same way. Pros: thin winding, short supply wires.
2. 5 turns across the entire length of the core, then the other 5 turns
in between the first winding's gaps. Should be as thin as the first one,
better coupling. Cons: the center tap endings are far apart.
3. 5 turns of a twisted pair of Litz wires. Cons: much thick,
the center taps are far apart.
4. 5 turns of a twisted bundle of, say, 20 two-color wires,*
then the appropriate unbraiding.
5. It doesn't matter.
The second issue: does any standard current density matter at all
in the case of such short primary wires? Even 1mm^2 (total area
of the Litz wire/twisted bundle) results in negligible RDC and
the I^2R approach seems more scientific than any industrial I/area
rule of thumb. I should focus on minimizing RAC. Correct?
Best regards, Piotr
bill....@ieee.org
Aug 4, 2018, 9:54:26 AM8/4/18
to
On Saturday, August 4, 2018 at 5:46:37 PM UTC+10, Piotr Wyderski wrote:
> I need to make a transformer for a push-pull converter.
> The core is a 25.3/14.8/10 toroid made of N87, f=200kHz
> (total, 100kHz per switch), Bmax=100mT, PRIMARY_Irms=10A,
> PRIMARY_V_MAX=20V. This gives 2x5 turns and this low
> value opens many options.
>
> 1. 5 turns, each turn close to one another, then the other 5 turns the
> same way. Pros: thin winding, short supply wires.
>
> 2. 5 turns across the entire length of the core, then the other 5 turns
> in between the first winding's gaps. Should be as thin as the first one,
> better coupling. Cons: the center tap endings are far apart.
>
> 3. 5 turns of a twisted pair of Litz wires. Cons: much thick,
> the center taps are far apart.
200kHz is a high enough frequency that skin-effect matters.
> I need to make a transformer for a push-pull converter.
> The core is a 25.3/14.8/10 toroid made of N87, f=200kHz
> (total, 100kHz per switch), Bmax=100mT, PRIMARY_Irms=10A,
> PRIMARY_V_MAX=20V. This gives 2x5 turns and this low
> value opens many options.
>
> 1. 5 turns, each turn close to one another, then the other 5 turns the
> same way. Pros: thin winding, short supply wires.
>
> 2. 5 turns across the entire length of the core, then the other 5 turns
> in between the first winding's gaps. Should be as thin as the first one,
> better coupling. Cons: the center tap endings are far apart.
>
> 3. 5 turns of a twisted pair of Litz wires. Cons: much thick,
> the center taps are far apart.
https://en.wikipedia.org/wiki/Skin_effect
recoomends 38AWG (0.1mm diameter) between 100 and 200kHz
Making the two windings as five turns of twisted pain minimises leakage inductance, but maximinses inter-winding capacitance.
> 4. 5 turns of a twisted bundle of, say, 20 two-color wires,*
> then the appropriate unbraiding.
> 5. It doesn't matter.
> The second issue: does any standard current density matter at all
> in the case of such short primary wires?
> Even 1mm^2 (total area
> of the Litz wire/twisted bundle) results in negligible RDC and
> the I^2R approach seems more scientific than any industrial I/area
> rule of thumb. I should focus on minimizing RAC. Correct?
wire. With Litz wire you've got less copper cross-section in a given window area, but the resistive loss at a given high frequency is less if you fill the winding window with Litz wire.
https://en.wikipedia.org/wiki/Skin_effect
If you aren't dissipating enough heat in the winding to matter, you might start thinking about a more compact (and cheaper) transformer, but you will get heat dissipation in the ferrite as well, and permeability drops quite fast at the Curie temperature (above 210C for N87)
https://en.tdk.eu/download/528882/3226013b0ed82a6a2af3666f537cbf83/pdf-n87.pdf
Transformer design can involves quite a few trade-offs.
--
Bill Sloman, Sydney
bitrex
Aug 4, 2018, 10:38:20 AM8/4/18
to
uses the method of Lagrange multipliers to optimize (minimize) total
copper loss for given transformer requirements
<http://www.endos.com.tr/dosya/Ch14slide.pdf>
Piotr Wyderski
Aug 4, 2018, 11:32:13 AM8/4/18
to
Yes, I know that. The question is not what wire I should use,
because I am able to design it properly, but how to make the
dual primaries correctly using a proper wire.
> Making the two windings as five turns of twisted pain minimises leakage inductance, but maximinses inter-winding capacitance.
I am thinking of using 20+ twisted wires, then unbraiding and
shuffling the endings to make the tap. Leakage inductance is
the source of spikes on the MOSFET drains, but what harm could
the capacitance do (without going to the extremes, i.e. causing
resonance exactly where you don't want it to be)?
> It is going to matter, but you have to know a fair bit about where your problem areas are going to be before you can work out which choice works best for you.
There will be a prototype, of course, but I want to avoid visiting
dead-ends.
> Current density matters if you have enough current in the wire to get it warm.
I'd say if you have enough resistance, that is length.
And enough layers to stop heat spreading.
> The problem is that high frequency current doesn't use the whole area of a solid
> wire.
Yes, proximity + skin effects combined. But this part I can manage.
> Transformer design can involves quite a few trade-offs.
Sure, for example I am not going to use the optimal number of turns,
because it is a multi-output PSU. Bumping the number of secondary turns
requires a similar primary adjustment, and that increases B and R.
But the additional losses are less than making the voltages too big
and then dropping them to the desired level. Since the initial B=90mT,
127mT is still fine. The core is a tad too big, but once again I am
geometry-limitated.
Best regards, Piotr
because I am able to design it properly, but how to make the
dual primaries correctly using a proper wire.
> Making the two windings as five turns of twisted pain minimises leakage inductance, but maximinses inter-winding capacitance.
shuffling the endings to make the tap. Leakage inductance is
the source of spikes on the MOSFET drains, but what harm could
the capacitance do (without going to the extremes, i.e. causing
resonance exactly where you don't want it to be)?
> It is going to matter, but you have to know a fair bit about where your problem areas are going to be before you can work out which choice works best for you.
dead-ends.
> Current density matters if you have enough current in the wire to get it warm.
And enough layers to stop heat spreading.
> The problem is that high frequency current doesn't use the whole area of a solid
> wire.
> Transformer design can involves quite a few trade-offs.
because it is a multi-output PSU. Bumping the number of secondary turns
requires a similar primary adjustment, and that increases B and R.
But the additional losses are less than making the voltages too big
and then dropping them to the desired level. Since the initial B=90mT,
127mT is still fine. The core is a tad too big, but once again I am
geometry-limitated.
Best regards, Piotr
Johann Klammer
Aug 4, 2018, 3:34:17 PM8/4/18
to
maxima file and a .csv based on mostly epcos datasheets. no idea if any of this is correct
-------------------------------xfrmr.mac---------------------------------------
/*
try to guess the power capability of the cores.
using the AP estimate in slup126.pdf
makelist([
(ui[e+1][2]+ui[e][2])/2,
(ui[e+1][1]-ui[e][1])/(ui[e+1][2]-ui[e][2])
],e,2,length(ui)-1,1);
write_data([["Id","Ud'"],%],"dif1.csv",comma);
*/
kill(all);
Po(AP,K,B,f_t):=(AP*100000000)^(3/4)*K*B*f_t;
load("numericalio.lisp");
cores:read_nested_list("cores.csv",comma);
cores:makelist(cores[e],e,2,length(cores),1);
pwr:makelist(Po(cores[e][6]*cores[e][9],0.014,200e-3,100000),e,1,length(cores),1);
/*
the pm is a tad too big (3000W vs 520W)
They(EPCOS) don't include the ring cores
in their simulation tool
want something more detailed..
The plan:
1)guess rtherm from v/surface
2)calc deltaB and currents for equal dissipation Pcore=Pwinding
3)check the temp rise is ok
1)R_th
(EPCOS Ferrites and accessoires)
R_th ~=1/sqrt(V_e)
(a point from their R_th graph)
R_th(300e-9 m^3)=100K/W
100=K/sqrt(300e-9)
K = 0.0547722557505166
therefore:
*/
R_th(V_e) :=0.0548/sqrt(V_e);
delta_T(P_v,R_th) :=P_v*R_th;
/*
transferrable power:
Ptrans=C*delta_B*f*A_e*A_n*J
A_N is copper cross section m^2
A_e is core cross section mm^2
J current density A/m^2
C=1 for push pull
delta_B flux dens variation Vs/m^2
f freq 1/s
Power loss:
P_v=P_vc+P_vj
P_vj=I^2*N*R_cu
P_vc(B,f)=K*f^(1+x)*B^(2+y)
x,y 0..1
delta_B=V*t/(N*A_e)
find the koeff K and exp y for core loss
logexpand:super
B,P
30e-3,7e+3
90e-3,100e+3
dy/dx=
(log(100e+3)-log(7e+3))/(log(90e-3)-log(30e-3));
2.420562799417347
y=k*x+d
y=log(P)
k=dy/dx
x=log(B)
d=?
d = 8.781048544054926
log(P)=2.42*log(B)+8.7810485
P=6509.699302573376*B^(2+0.420562799417347)
y=0.4...
try again for K
K=3.398769238238504E+7
P_B(B):=3.398769238238504E+7*B^(2+0.420562799417347);
now K and x for P(f)
P(f)=K*f^(1+x)
f,Pv
30e3,30e3
300e3,600e3
dy/dx=
(log(600e+3)-log(30e+3))/(log(300e+3)-log(30e+3));
1.301029995663981
d = - 3.103303974733933
P(f):=K*f^(1+0.301029995663981)
K = 0.04490060658064694
P_f(f):=0.04490060658064694*f^(1+0.301029995663981)
now how2 combine?
P_vc(B,f)=K*f^(1+x)*B^(2+y)
K=guessed 11.4
*/
P_vc1(B,f):=11.4*f^(1+0.301029995663981)*B^(2+0.420562799417347);
/*
winding losses:
want those in terms of window area. filling factor 0.4
*/
P_vj(I,l,rho,A_n):=I^2*l*rho/(A_n*0.4);
/*
more accurate l based on inner and outer winding radius
circular bobbins:
fullratsimp(integrate(2*%pi*r,r,r1,r2)/(r2-r1));
l=%pi*r2+%pi*r1;
ring cores:
l1(h,da,di):=2*(h+da-di);
l2(h,da,di):=2*(da/2+di/2+h+di);
l(h,da,di):=(l1(h,da,di)+l2(h,da,di))/2;
vind=dphi/dt
vind=db/dt*a
B=integral(v/a)dt t=0 t=T/2
B=V*(T/2-0)/A
B=V*T/(2*A)
V=Vin/N
*/
delta_B(V,T,N,A_e):=V*T/(2*N*A_e);
B(delta_B):=delta_B/2;
P_vc(f,V,N,A_e,V_e):=P_vc1(B(delta_B(V,1/f,N,A_e)),f)*V_e;
/*
assume p and s winding same voltage + current
if I keep P=u*i const what's the opt u/i, N
with min loss?
P_vc increases times 2^2.5 for half N, double v, half core area
increases times (2^(1.3))/(2^(2.5))=0.43 for twice f
P_vj incr times 4 for twice I, 2 for 2 l, 0.5 for twice A_n
*/
I1:24;
V1:31.4;
N1:4;
RN:800/16;
I2:500e-3;
V2:800;
N2:N1*RN;
pvj_l:makelist(P_vj(I1*N1,cores[e][10],2.3e-8,cores[e][9]*(1-0.417))+P_vj(I2*N2,cores[e][10],2.3e-8,cores[e][9]*(0.417)),e,1,length(cores),1);
pvc_l:makelist(P_vc(100e3,V2,N2,cores[e][6],cores[e][7]),e,1,length(cores),1);
rth_l:makelist(R_th(cores[e][7]),e,1,length(cores),1);
delta_t_l:makelist(delta_T(pvj_l[e]+pvc_l[e],rth_l[e]),e,1,length(cores),1);
/*
I1*N1/A1=I2*N2/A2
A1/A2=(I1*N1)/(I2*N2)
A1/A=0.7172413793103448/1.7172413793103448;
0.417...
(area ratio prim/sec winding based on rms currents
from the simulation I1,I2)
find the minima?
best_N:makelist(
solve(
diff(
P_vj(I*BN,cores[e][10],2.3e-6,cores[e][9])+P_vc(100e3,V,BN,cores[e][6],cores[e][7]),BN
)=0,BN),e,1,length(cores),1);
it's too dumb for that..
have to log and then..
solveradcan:true...
logsolve:true...
??
*/
------------------------------------------cores.csv--------------------------------------------------
Name,al,mu_i,sum_L_over_A,L_e,A_e,V_e,mass,A_n,l_w
"R10",900e-9,1500,3.07e+3,24.07e-3,7.83e-6,188e-9,0.9e-3,28.27e-6,28.325e-3
"R12",1330e-9,2200,2.08e+3,31.17e-3,14.96e-6,466e-9,2.4e-3,49.02e-6,38.25e-3
"R16",1420e-9,2200,1.95e+3,38.52e-3,19.73e-6,760e-9,3.7e-3,72.38e-6,44.65e-3
"R29.5",2880e-9,2200,0.96e+3,73.78e-3,76.98e-6,5680e-9,27e-3,283.5e-6,87.55e-3
"R102",2880e-9,2200,0.96e+3,255.3e-3,267.2e-6,68220e-9,330e-3,3400.49e-6,222.05e-3
"PM62/49",9200e-9,1400,0.191e+3,109e-3,570e-6,62000e-9,280e-3,292.5e-6,198.86e-3
"PM50/39",7400e-9,1340,0.227e+3,84e-3,370e-6,31000e-9,140e-3,196.3e-6,97.232e-3
"ETD29/16/10",2860e-9,2160,0.947e+3,72e-3,76e-6,5470e-9,28e-3,95e-6,53e-3
"ETD39/20/13",2700e-9,1600,0.74e+3,92.2e-3,125e-6,11500e-9,60e-3,178e-6,69e-3
"ETD49/25/16",3800e-9,1630,0.54e+3,114e-3,211e-6,24100e-9,124e-3,269.4e-6,86.7e-3
"ETD59/31/22",5300e-9,1590,0.38e+3,139e-3,368e-6,51200e-9,260e-3,365.6e-6,106.61e-3
"RM14",6000e-9,1670,0.35e+3,70e-3,200e-6,14000e-9,74e-3,140e-6,71.63e-3
"E80/38/20",4590e-9,1710,0.470e+3,184e-3,392e-6,72300e-9,360e-3,1628e-6,157.8e-3
"E71/33/32",10000e-9,1740,0.218e+3,149e-3,683e-6,102000e-9,520e-3,1628e-6,160e-3
"E56/24/19",6900e-9,1730,0.31e+3,107e-3,340e-6,36400e-9,184e-3,281.78e-6,113.8e-3
"E55/28/25",9860e-9,2300,0.239e+3,123e-3,420e-6,52000e-9,260e-3,360e-6,164e-3
"E55/28/21",6300e-9,1760,0.350e+3,124e-3,353e-6,44000e-9,216e-3,375.55e-6,117.0e-3
"E42/21/20",5200e-9,1690,0.41e+3,97e-3,234e-6,22700e-9,116e-3,172e-6,100e-3
"E42/21/15",3950e-9,1710,0.548e+3,97e-3,178e-6,17300e-9,88e-3,177e-6,87e-3
"E36/18/11",3100e-9,1500,0.68e+3,81e-3,120e-6,9670e-9,50e-3,122.55e-6,76.4e-3
Johann Klammer
Aug 4, 2018, 3:50:38 PM8/4/18
to
On 08/04/2018 05:31 PM, Piotr Wyderski wrote:
The layered windings have higher capacitance but lower leak inductance sectioned ones have higher
leak inductance and lower winding capacitance.
There's some formulas in the Transformer and Inductor Design Handbook (google will find a pdf)(but none for toroids)
slup126.pdf is also interesting, but careful it seems to use the cgs System.
for guessing an rtherm, Epcos' PDF_Application.pdf uses 1/sqrt(V_e)
bill....@ieee.org
Aug 4, 2018, 7:45:11 PM8/4/18
to
On Sunday, August 5, 2018 at 1:32:13 AM UTC+10, Piotr Wyderski wrote:
> bill....@ieee.org wrote:
>
> > 200kHz is a high enough frequency that skin-effect matters.
>
> Yes, I know that. The question is not what wire I should use,
> because I am able to design it properly, but how to make the
> dual primaries correctly using a proper wire.
>
> > Making the two windings as five turns of twisted pain minimises leakage inductance, but maximinses inter-winding capacitance.
>
> I am thinking of using 20+ twisted wires, then unbraiding and
> shuffling the endings to make the tap.
Simple twisting doesn't give you Litz wire. You want each wire to cut the same amount of magnetic flux, and single twisting doesn't give you that.
> bill....@ieee.org wrote:
>
> > 200kHz is a high enough frequency that skin-effect matters.
>
> Yes, I know that. The question is not what wire I should use,
> because I am able to design it properly, but how to make the
> dual primaries correctly using a proper wire.
>
> > Making the two windings as five turns of twisted pain minimises leakage inductance, but maximinses inter-winding capacitance.
>
> I am thinking of using 20+ twisted wires, then unbraiding and
> shuffling the endings to make the tap.
> Leakage inductance is
> the source of spikes on the MOSFET drains, but what harm could
> the capacitance do (without going to the extremes, i.e. causing
> resonance exactly where you don't want it to be)?
Baxandall resonant inverters finesse this (which is why Baxandall invented the circuit) but the approach isn't popular if you aren't trying for high turns ratios.
http://sophia-elektronica.com/0344_001_Baxandal.pdf
> > It is going to matter, but you have to know a fair bit about where your problem areas are going to be before you can work out which choice works best for you.
>
> There will be a prototype, of course, but I want to avoid visiting
> dead-ends.
>
> > Current density matters if you have enough current in the wire to get it warm.
>
> I'd say if you have enough resistance, that is length.
> And enough layers to stop heat spreading.
<snipped sensible stuff which we don't need to reiterate>
--
Bill Sloman, Sydney
Tim Williams
Aug 5, 2018, 12:37:57 AM8/5/18
to
Primary impedance is very low, count on heavy interleaving. Consider
transmission line transformer design: not because of the bandwidth, but
because of the method to obtain low impedances.
Ideally, primary Zo is around 2-10 ohms, depending on exactly what you meant
(is V_MAX what the switch sees, or what the CT sees?).
Litz is lower losses but higher inductance. Consider that the whole point
is to allow flux to penetrate the cable. This gives higher impedances,
which may increase losses elsewhere.
Ideally, you'd have flat ribbon shaped Litz, so you get the paralleling and
interleaving basically for free. It's out there, but regular Litz is
already hard to find... :(
Yes, Rac matters, to the extent it may cause the transformer to overheat.
No need to have it stupendously low or anything.
Last time I did something like that, I used 6 strands of #24 in parallel.
Alternating for each side of the primary, P1-P2-... in a flat (multifilar)
winding for the whole primary. Strands are connected to pins alternately,
giving the interleave and CT winding. Leakage so low (between ends of the
primary), I didn't even need snubbing for it -- the transistors are
switching slower. (Slower than I would've liked; they were unfortunately
limited by the inductance of the current sense resistor.)
What's secondary? If same voltage, throw another set in the bundle,
interleaved, and you're good. If high voltage, consider that you need to
keep its impedance high, otherwise it'll be swamped by capacitance.
Tim
--
Seven Transistor Labs, LLC
Electrical Engineering Consultation and Design
Website: https://www.seventransistorlabs.com/
"Piotr Wyderski" <pete...@neverland.mil> wrote in message
news:pk3lkq$3te$1...@node2.news.atman.pl...
transmission line transformer design: not because of the bandwidth, but
because of the method to obtain low impedances.
Ideally, primary Zo is around 2-10 ohms, depending on exactly what you meant
(is V_MAX what the switch sees, or what the CT sees?).
Litz is lower losses but higher inductance. Consider that the whole point
is to allow flux to penetrate the cable. This gives higher impedances,
which may increase losses elsewhere.
Ideally, you'd have flat ribbon shaped Litz, so you get the paralleling and
interleaving basically for free. It's out there, but regular Litz is
already hard to find... :(
Yes, Rac matters, to the extent it may cause the transformer to overheat.
No need to have it stupendously low or anything.
Last time I did something like that, I used 6 strands of #24 in parallel.
Alternating for each side of the primary, P1-P2-... in a flat (multifilar)
winding for the whole primary. Strands are connected to pins alternately,
giving the interleave and CT winding. Leakage so low (between ends of the
primary), I didn't even need snubbing for it -- the transistors are
switching slower. (Slower than I would've liked; they were unfortunately
limited by the inductance of the current sense resistor.)
What's secondary? If same voltage, throw another set in the bundle,
interleaved, and you're good. If high voltage, consider that you need to
keep its impedance high, otherwise it'll be swamped by capacitance.
Tim
--
Seven Transistor Labs, LLC
Electrical Engineering Consultation and Design
Website: https://www.seventransistorlabs.com/
"Piotr Wyderski" <pete...@neverland.mil> wrote in message
news:pk3lkq$3te$1...@node2.news.atman.pl...
Piotr Wyderski
Aug 5, 2018, 2:18:33 AM8/5/18
to
Tim Williams wrote:
> Last time I did something like that, I used 6 strands of #24 in
> parallel. Alternating for each side of the primary, P1-P2-... in a flat
> (multifilar) winding for the whole primary.
I can use 7x0.3mm TRW Litz for that purpose, 3 strands of it would
> Last time I did something like that, I used 6 strands of #24 in
> parallel. Alternating for each side of the primary, P1-P2-... in a flat
> (multifilar) winding for the whole primary.
give me ~1.5mm^2 cross-section per half-primary and a flat winding.
Sounds very reasonable, thanks!
> What's secondary
There's a whole herd of them. 3.3V, 5V, 9V and 18V are the main
outputs, totalling to ~60W. There will also be a lot of 10V isolated
low-current secondaries for high-side MOSFET drivers. I'd like to
check a push-pull first, because it makes the life of the filters
easy and I could steal some AC to directly feed several magamps in the
critical places. A kind of "one ring to rule them all" approach.
A mundane active-clamp forward is waiting as a relief force.
I would like to try the push-pull first also because of its
neuron de-rusting merits. I haven't made a high-power push-pull
for 15 years. Only the SN6501/IR21531 1W-class gizmos.
Best regards, Piotr
Piotr Wyderski
Aug 5, 2018, 3:27:04 AM8/5/18
to
OK, some experimental data.
UCC28084, f_osc=224kHz, V_IN=10V (desired range: ~8..20V),
no feedback to force 50/50 mode, no secondary windings.
R_SENSE=50m, output switches: SQJA62EP-T1_GE3, input cap:
150uF/35V SMD polymer tantalum with 70m of ESR. 3D construction
to minimize the lengths of the wires, ~1cm transformer leads
soldered directly to the cap/drain tabs. BAT83 30mA diodes
between D and S, just in case. No gate resistors. Core
is B64290L0618X087, 25mm OD toroid made of N87.
Trafo #1: 1x7 turns, 20x0.335mm wires twisted together
and then unbraided to make the center-tap primaries.
Spread evenly across the core. Considered the best I can do.
Trafo #2: 2x10 turns of 0.7wire, the first half, the tap
and then the second part, wound tightly. The worst possible
implementation, just for reference.
Results:
Idle current=54mA for Trafo #1, 39mA for T#2. Looks like
the effect of the increased capacitance Bill wrote about.
Gate signals: perfect, sharp, no ringing.
Drain waveforms: strange in both cases. With T#1 and T#2
I have massive ringing, but only on one of the drains.
It's not an output stage issue. If I swap the primary
endings, nothing changes. If I swap the gate signals,
the ringing goes to the other coil. So it originates in
the controller itself.
With T#1 it is always like that:
https://s15.postimg.cc/harvkb1u3/DS1_Z_Quick_Print11.png
With T#2 it started more symmetric:
https://s15.postimg.cc/3tux17el7/DS1_Z_Quick_Print10.png
But by manually squeezing/stretching the primaries I am able
to restore the T#1 situation, i.e. dampen the blue waveform.
I am not able to significantly alter the yellow ringing, though.
50V of ringing in a 10V-powered push-pull looks scary. Moreover,
it continues for the entire off-period.
Best regards, Piotr
UCC28084, f_osc=224kHz, V_IN=10V (desired range: ~8..20V),
no feedback to force 50/50 mode, no secondary windings.
R_SENSE=50m, output switches: SQJA62EP-T1_GE3, input cap:
150uF/35V SMD polymer tantalum with 70m of ESR. 3D construction
to minimize the lengths of the wires, ~1cm transformer leads
soldered directly to the cap/drain tabs. BAT83 30mA diodes
between D and S, just in case. No gate resistors. Core
is B64290L0618X087, 25mm OD toroid made of N87.
Trafo #1: 1x7 turns, 20x0.335mm wires twisted together
and then unbraided to make the center-tap primaries.
Spread evenly across the core. Considered the best I can do.
Trafo #2: 2x10 turns of 0.7wire, the first half, the tap
and then the second part, wound tightly. The worst possible
implementation, just for reference.
Results:
Idle current=54mA for Trafo #1, 39mA for T#2. Looks like
the effect of the increased capacitance Bill wrote about.
Gate signals: perfect, sharp, no ringing.
Drain waveforms: strange in both cases. With T#1 and T#2
I have massive ringing, but only on one of the drains.
It's not an output stage issue. If I swap the primary
endings, nothing changes. If I swap the gate signals,
the ringing goes to the other coil. So it originates in
the controller itself.
With T#1 it is always like that:
https://s15.postimg.cc/harvkb1u3/DS1_Z_Quick_Print11.png
With T#2 it started more symmetric:
https://s15.postimg.cc/3tux17el7/DS1_Z_Quick_Print10.png
But by manually squeezing/stretching the primaries I am able
to restore the T#1 situation, i.e. dampen the blue waveform.
I am not able to significantly alter the yellow ringing, though.
50V of ringing in a 10V-powered push-pull looks scary. Moreover,
it continues for the entire off-period.
Best regards, Piotr
Tim Williams
Aug 5, 2018, 3:42:48 AM8/5/18
to
Duty cycle is too high, limit it to, say, 45% (per output) or thereabouts.
No idea what the BAT83s are for, they're at best resistors when forward
biased if ever. At worst, tiny fuse links when pushed slightly harder. :-)
Shittons of outputs aren't too bad for forward converters, but don't expect
good cross-regulation, unless you can make them all very tightly coupled!
The classic ATX supply solves this by regulating 3.3V separately with a mag
amp (as you're probably well aware :) ).
You may find it's better to use a main supply (e.g., the 18V?) and derive
the others with DC-DCs (possibly with multi-windings or taps, to get certain
"lucky" pairs of voltages, or negative rails if necessary, etc.). Depends
on requirements, including size and cost, regulation, etc.
Tim
--
Seven Transistor Labs, LLC
Electrical Engineering Consultation and Design
Website: https://www.seventransistorlabs.com/
"Piotr Wyderski" <pete...@neverland.mil> wrote in message
news:pk68s5$evs$1...@node2.news.atman.pl...
No idea what the BAT83s are for, they're at best resistors when forward
biased if ever. At worst, tiny fuse links when pushed slightly harder. :-)
Shittons of outputs aren't too bad for forward converters, but don't expect
good cross-regulation, unless you can make them all very tightly coupled!
The classic ATX supply solves this by regulating 3.3V separately with a mag
amp (as you're probably well aware :) ).
You may find it's better to use a main supply (e.g., the 18V?) and derive
the others with DC-DCs (possibly with multi-windings or taps, to get certain
"lucky" pairs of voltages, or negative rails if necessary, etc.). Depends
on requirements, including size and cost, regulation, etc.
Tim
--
Seven Transistor Labs, LLC
Electrical Engineering Consultation and Design
Website: https://www.seventransistorlabs.com/
"Piotr Wyderski" <pete...@neverland.mil> wrote in message
69883925...@nospam.org
Aug 5, 2018, 3:51:02 AM8/5/18
to
Datasheet says threshold <= 2.5V, you will need 4V for it to be full on.
What do the gate signals look like?
Piotr Wyderski
Aug 5, 2018, 4:25:37 AM8/5/18
to
Tim Williams wrote:
> Duty cycle is too high, limit it to, say, 45% (per output) or thereabouts.
Sure, but could you please explain the asymmetry?
> Duty cycle is too high, limit it to, say, 45% (per output) or thereabouts.
> No idea what the BAT83s are for, they're at best resistors when forward
> biased if ever. At worst, tiny fuse links when pushed slightly harder. :-)
with something better later. I'm also going to check Zener clamping
just to see what happens (on a good way to invent a MINIMELF LED?)
> Shittons of outputs aren't too bad for forward converters, but don't
> expect good cross-regulation, unless you can make them all very tightly
> coupled!
is fine) and the 18V rail just needs to be there, as it is intended to
power a 10W D-class audio amplifier with.
> You may find it's better to use a main supply (e.g., the 18V?)
isolation is highly welcome. For that reason another option is to
produce that 18V with something isolated and then go down with
a bunch of SOT-23 synchronous bucks from TI. Will work for sure,
but there would be no fun. ;-)
I'm willing to spend some time on this approach just to learn something.
Best regards, Piotr
Piotr Wyderski
Aug 5, 2018, 4:56:06 AM8/5/18
to
Tim Williams wrote:
> Duty cycle is too high, limit it to, say, 45% (per output) or thereabouts.
Zener snubbing works, with two back-to back connected 18V DO35 diodes
> Duty cycle is too high, limit it to, say, 45% (per output) or thereabouts.
attached to the primary endings the waveforms are like this:
https://s15.postimg.cc/ixq9wyv7f/DS1_Z_Quick_Print12.png
But the diodes get warm and idle current jumps to 104mA.
There is considerable power going into the snubber, not good.
Best regards, Piotr
Piotr Wyderski
Aug 5, 2018, 5:10:58 AM8/5/18
to
Tim Williams wrote:
A third transformer, 2x10 turns on 16mm 3F3. This
is clearly the winner of the ringing contest:
https://s15.postimg.cc/8q7qkg6dn/DS1_Z_Quick_Print13.png
Dr. Zener is able to teach it good manners, but he sweats like hell.
Best regards, Piotr
A third transformer, 2x10 turns on 16mm 3F3. This
is clearly the winner of the ringing contest:
https://s15.postimg.cc/8q7qkg6dn/DS1_Z_Quick_Print13.png
Dr. Zener is able to teach it good manners, but he sweats like hell.
Best regards, Piotr
Tim Williams
Aug 5, 2018, 5:33:37 AM8/5/18
to
"Piotr Wyderski" <pete...@neverland.mil> wrote in message
news:pk6c9t$qvc$1...@node1.news.atman.pl...
> Sure, but could you please explain the asymmetry?
>
Most likely pulse width imbalance, leading to "flux walking" as it's
>
colloquially called, but it's just DC imbalance, not some arcane bit of
magnetic physics.
Reducing duty gives a high impedance period where the transformer can
resolve its flux.
> It was the first low-power Schottky I found in the box. I'll check
> with something better later. I'm also going to check Zener clamping
> just to see what happens (on a good way to invent a MINIMELF LED?)
together the cathodes and use one resistor back to VIN). Downside: wastes
idle current, so efficiency is crap at low output. May or may not be a
concern. There are other similar approaches.
Simply winding the primary well is the best, but that's not always possible
or practical, especially with transistors being as fast as they are these
days.
> Will work for sure,
> but there would be no fun. ;-)
>
> I'm willing to spend some time on this approach just to learn something.
Tim Williams
Aug 5, 2018, 5:34:56 AM8/5/18
to
"Piotr Wyderski" <pete...@neverland.mil> wrote in message
news:pk6e33$snv$1...@node1.news.atman.pl...
would be better, or a clamp snubber, or quasi-resonant snubber if
applicable, etc.
Or you can reduce switching time, effectively burning that power in the
transistors. If you already need to heatsink them, that's not a big deal.
AntonF
Aug 6, 2018, 5:17:51 PM8/6/18
to
May I add one more question on push-pull transformers? How do I choose inductance of primary coil? The datasheets for LT1533 and LT1683 say:
"The inductance of the transformer primary should be such
that LO, when reflected into the primary, dominates the
input current. In other words, we want the magnetizing
current of the transformer small with respect to the
current going through the transformer to LO. In general,
then, the inductance of the primary should be at least five
times that of LO. This ensures that most of the power will
be passed through the transformer to the load. It also
increases the power capability of the converter and
reduces the peak currents that the switch will see."
I don't this recommendation. L0 is inductance of the output filter. First sentence says L0 should dominate (that is: larger L0 compare to Lpri - the better), but the third says Lpri should be "at least 5 • LO/N^2" (that is: large Lpri compare to L0 - the better). What is physical meaning behind that recommendation?
"The inductance of the transformer primary should be such
that LO, when reflected into the primary, dominates the
input current. In other words, we want the magnetizing
current of the transformer small with respect to the
current going through the transformer to LO. In general,
then, the inductance of the primary should be at least five
times that of LO. This ensures that most of the power will
be passed through the transformer to the load. It also
increases the power capability of the converter and
reduces the peak currents that the switch will see."
I don't this recommendation. L0 is inductance of the output filter. First sentence says L0 should dominate (that is: larger L0 compare to Lpri - the better), but the third says Lpri should be "at least 5 • LO/N^2" (that is: large Lpri compare to L0 - the better). What is physical meaning behind that recommendation?
Tim Williams
Aug 6, 2018, 6:51:19 PM8/6/18
to
"AntonF" <fortu...@gmail.com> wrote in message
news:d6fcdc35-8f46-4e7a...@googlegroups.com...
current, therefore LO should be >5 times smaller than Lpri, as it goes on to
say.
Cheers,
news:d6fcdc35-8f46-4e7a...@googlegroups.com...
> I don't this recommendation. L0 is inductance of the output filter. First
> sentence says L0 should dominate (that is: larger L0 compare to Lpri - the
> better)
>
Read it closely: LO _current_ should dominate. Inductance is inverse with
> sentence says L0 should dominate (that is: larger L0 compare to Lpri - the
> better)
>
current, therefore LO should be >5 times smaller than Lpri, as it goes on to
say.
Cheers,
bill....@ieee.org
Aug 6, 2018, 8:12:44 PM8/6/18
to
On Sunday, August 5, 2018 at 5:42:48 PM UTC+10, Tim Williams wrote:
> Duty cycle is too high, limit it to, say, 45% (per output) or thereabouts.
A 50% duty cycle is incompatible with break-before-make switching.
> Duty cycle is too high, limit it to, say, 45% (per output) or thereabouts.
It takes a finite time to switch a MOSFET on or off - you've got to move a finite amount of charge into or out of the gate electrode - so a 50% duty cycle implkes that one is turning off (but not turned fully off) at the same time as the other one is turning on (but not fully turned on).
This tends to produce nasty current spikes in the supply current.
At 100k - a 10usec period - a 45% duty cycle implies two 250nsec gap to cover turn-on and turn-off, which ought to be generous.
With high current gate drivers 25nsec might be enough.
<snip>
--
Bill Sloman, Sydney
69883925...@nospam.org
Aug 7, 2018, 4:25:28 AM8/7/18
to
On a sunny day (Mon, 6 Aug 2018 14:17:44 -0700 (PDT)) it happened AntonF
<fortu...@gmail.com> wrote in
<d6fcdc35-8f46-4e7a...@googlegroups.com>:
>May I add one more question on push-pull transformers? How do I choose inductance
>of primary coil? The datasheets for LT1533 and LT1683 say:
>"The inductance of the transformer primary should be such
>that LO, when reflected into the primary, dominates the
>input current. In other words, we want the magnetizing
>current of the transformer small with respect to the
>current going through the transformer to LO. In general,
>then, the inductance of the primary should be at least five
>times that of LO. This ensures that most of the power will
>be passed through the transformer to the load. It also
>increases the power capability of the converter and
>reduces the peak currents that the switch will see."
>
>I don't this recommendation. L0 is inductance of the output filter. First sentence
>says L0 should dominate (that is: larger L0 compare to Lpri - the better),
>but the third says Lpri should be "at least 5 =E2=80=A2 LO/N^2" (that
you want the UNLOADED inductance of the primary so high that it does not
cause excessive currents in the drivers.
That sets the minimum number of turns.
<fortu...@gmail.com> wrote in
<d6fcdc35-8f46-4e7a...@googlegroups.com>:
>May I add one more question on push-pull transformers? How do I choose inductance
>of primary coil? The datasheets for LT1533 and LT1683 say:
>"The inductance of the transformer primary should be such
>that LO, when reflected into the primary, dominates the
>input current. In other words, we want the magnetizing
>current of the transformer small with respect to the
>current going through the transformer to LO. In general,
>then, the inductance of the primary should be at least five
>times that of LO. This ensures that most of the power will
>be passed through the transformer to the load. It also
>increases the power capability of the converter and
>reduces the peak currents that the switch will see."
>
>I don't this recommendation. L0 is inductance of the output filter. First sentence
>says L0 should dominate (that is: larger L0 compare to Lpri - the better),
>is: large Lpri compare to L0 - the better). What is physical meaning behind
>that recommendation?
Having wound and using several push pull transformers,
>that recommendation?
you want the UNLOADED inductance of the primary so high that it does not
cause excessive currents in the drivers.
That sets the minimum number of turns.
Tim Williams
Aug 7, 2018, 11:55:15 AM8/7/18
to
<bill....@ieee.org> wrote in message
news:10eae4ac-4d9e-46c0...@googlegroups.com...
(including negative) can be okay for half bridge, as long as you're not
driving a low-DCR load (like a transformer without a coupling cap).
The classic solution being the ATX power supply, where a half bridge drives
the transformer primary, returned via 2.2uF film cap to the FWD supply's
middle tap. (The cap could return to any end of the supply, but the middle
tap is convenient to reduce the startup transient. Alternately, a "half
bridge" of caps can be used -- a capacitor divider -- which is the preferred
method for FWB supplies.)
Note that, within a cycle (i.e., ignoring "flux walking" bias over many
cycles), each switching transient involves the inductance between switches.
In the PP case, that's the end-to-end leakage. In the half bridge, it's
stray wiring inductance, from nearest bypass cap, through the two switches.
Zero dead time, or slightly interleaved, switching is possible when that
loop inductance is intentionally controlled, setting dI/dt. This is
preferable for synchronous switching, and for bidirectional converters
(power converters, class D amps) where consistent EMI and higher efficiency
is needed. (Not much higher efficiency, mind -- the high frequency reactive
current drawn by the overlap has to be dealt with appropriately after all.
The main thing to be gained is body diode recovery, which is a monster with
higher voltage MOSFETs.)
Also, a current-sourced inverter MUST operate interleaved. In that case,
"dead time" is dead in the voltage sense, meaning, both devices ON during
the dead time. This isn't used much in power applications, but is relevant
to some configurations ("Royer oscillator") and RF amps (e.g., class E, PP).
news:10eae4ac-4d9e-46c0...@googlegroups.com...
>A 50% duty cycle is incompatible with break-before-make switching.
>It takes a finite time to switch a MOSFET on or off - you've got to move a
>finite amount of charge into or out of the gate electrode - so a 50% duty
>cycle implkes that one is turning off (but not turned fully off) at the
>same time as the other one is turning on (but not fully turned on).
>
Yeah, for PP, you have to deal with the transformer. Small deadtimes
>It takes a finite time to switch a MOSFET on or off - you've got to move a
>finite amount of charge into or out of the gate electrode - so a 50% duty
>cycle implkes that one is turning off (but not turned fully off) at the
>same time as the other one is turning on (but not fully turned on).
>
(including negative) can be okay for half bridge, as long as you're not
driving a low-DCR load (like a transformer without a coupling cap).
The classic solution being the ATX power supply, where a half bridge drives
the transformer primary, returned via 2.2uF film cap to the FWD supply's
middle tap. (The cap could return to any end of the supply, but the middle
tap is convenient to reduce the startup transient. Alternately, a "half
bridge" of caps can be used -- a capacitor divider -- which is the preferred
method for FWB supplies.)
Note that, within a cycle (i.e., ignoring "flux walking" bias over many
cycles), each switching transient involves the inductance between switches.
In the PP case, that's the end-to-end leakage. In the half bridge, it's
stray wiring inductance, from nearest bypass cap, through the two switches.
Zero dead time, or slightly interleaved, switching is possible when that
loop inductance is intentionally controlled, setting dI/dt. This is
preferable for synchronous switching, and for bidirectional converters
(power converters, class D amps) where consistent EMI and higher efficiency
is needed. (Not much higher efficiency, mind -- the high frequency reactive
current drawn by the overlap has to be dealt with appropriately after all.
The main thing to be gained is body diode recovery, which is a monster with
higher voltage MOSFETs.)
Also, a current-sourced inverter MUST operate interleaved. In that case,
"dead time" is dead in the voltage sense, meaning, both devices ON during
the dead time. This isn't used much in power applications, but is relevant
to some configurations ("Royer oscillator") and RF amps (e.g., class E, PP).
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