Phil Hobbs <
ho...@electrooptical.net> wrote:
> On 5/31/2014 9:24 AM, Steve Wilson wrote:
>> Steve Wilson <
no...@nospam.com> wrote:
>>> There is a magical discontinuity at zero. In the forward
>>> direction, the current increases exponentially with voltage
>>> according to the diode equation:
>>>
>>>
http://en.wikipedia.org/wiki/Diode_modelling
>>>
>>> In the reverse direction, the leakage current is virtually
>>> independent of voltage up to the point where the diode breaks down:
>>>
>>>
http://en.wikipedia.org/wiki/Reverse_leakage_current
>>>
>>> These are two different mechanisms.
>>
>> And this explains why you cannot set the bias current to zero in the
>> LMC660/LMC64482 series parts. The diode leakages for the top and
>> bottom diodes add together.
>
> How does that work? One is a positive current, and the other is
> negative.
Exactly. The currents cancel. The degree of matching sets the input bias
current.
>> However, they act as current sources, so they are independent of
>> voltage.
>
> If the diodes are closely matched, the leakage should be close as
> well.
True.
> Second order effects such as bias voltage might very well be enough
> to
> make them match exactly.
True, if they are very close to start with. However, temperature changes
may destroy the cancellation.
>> This means changing VCC and VEE or changing the voltage at the input
>> to the op amp will have no effect on the input bias current.
>
> To leading order.
>
>>
>> The reason this is true is because the actual bias current into the
>> mosfet junction is close to zero, as Paul Grohe stated. So the only
>> currents involved are the leakage currents into the protection
>> diodes.
>>
>> I have answered the questions I asked earlier. The mechanism that
>> creates the input bias current is diode leakage. The currents flow to
>> VCC and gnd.
> Cheers
> Phil Hobbs
I collected a number of Paul Grohe's posts on the LMC660 and related
topics. These confirm your observations and add a bit more light on the
subject. The topics are
1. Removing Input Protection Diodes
2. Diode Leakage Cancellation - Setting Bias Current to Zero
3. Cleaning Plastic Package
4. Layout For Lowest Leakage
5. Latchup
6. Input Protection
7. Testing Op Amps
8. Op Amp as Comparator
===================================================================
1. Removing Input Protection Diodes
Paul Grohe
1/26/03
On Fri, 24 Jan 2003 11:35:06 +0100,
in the newsgroup sci.electronics.design,
al <2...@bill.invalid>
from Technical University Berlin, Germany posted:
> Paul,
>
> how well are the input bias currents in a dual amplifier matched?
Within a few percent - but better than you could do with discrete
devices.
> Can I compensate the temperature dependent bias current with the
> other amplifier?
The "Input Bias Current" is actually the difference in the
leakages of the two ESD protection diodes. The actual MOSFET gate
current is much less.
We actually *tried* to measure the bias current of a device with
the ESD diodes cut out - it was in the "noise" (*if* we did not
accidently "zap" it first - geez they were sensitive!).
A rule of thumb is that the bias current will double every 10�C.
Your best bet is to keep the temperature constant - even if you
have to elevate the ambient temp to keep it constant (like an
XTAL oven).
Cheers,
Paul Grohe
http://tinyurl.com/ktdnm7x
===================================================================
2. Diode Leakage Cancellation - Setting Bias Current to Zero
Paul Grohe
12/31/95
On Sun, 31 Dec 1995 16:14:00 GMT,
in sci.electronics
fra...@euronet.nl (Frank W. van Wensveen)
from Euronet Internet thoughtfully posted:
> I'm looking for someone who can help me with some weird problems I've
> been having with a MOSFET opamp measurement amplifier. I'm trying to
> measure electrostatical charges with a CA3130 opamp. This opamp has
> MOSFETs at the inputs, with internal zener diodes which act as an
> over-voltage protection. (You might want to check the CA3130 data
> sheet for details.)
> The first stage of my amplifier consists of a CA3130 with the
> non-inverting input floating (i.e. not connected to the ground by
> *any* component) and the inverting input connected to the output.
> According to the data sheet, the floating input has an imput impedance
> of about 1.5 Tera-ohm. The opamp is powered by a symetric (sp?) power
> supply at + and - 10 V.
BTW, try Nationals LMC660 (quad) or 662 (dual). Input bias current at
room temperature can be less than 1fA. Call the European number in my
sig for a sample. (yes, I'm biased...pun intended)
> In theory the floating input, screened with a grounded shield to
> prevent it from picking up any charge from the environment, should be
> at ground potential or somewhere near it, and the output of the opamp
> should follow this. (Right?)
> But instead, the output voltage tends towards -Uv if I don't connect
> anything to the non-inverting input pin of the opamp. (Note: the
> non-inverting input pin is *not* connected to anything.) If I connect
> a piece of wire with a length of about 2 inches to the pin and leave
> the other end floating, the output voltage is around zero. If I
> connect a 4 to 6 inch wire to the pin, the output voltage tends
> toward +Uv. Weird but true.
In theory: correct. In practice: Hardly ever.
You are simply seeing the results of the leakages of the input ESD
protection diodes. The ESD diodes are designed so that two diodes
leakage's cancel each other out. The leakage you see is actually the
difference between the two diodes. If your output floats towards V-,
then the diode between the input and V- has slightly higher leakage
than the other one. Temperature changes can also cause this, as well
as contamination or other leakage paths. Make sure the package is
clean, any 'boogers' between the pins can collect dirt and moisture
and cause leakages. This is very noticeable on quads, as they have the
non-inverting pin right next to the power supply leads. Don't use
packages that have been overly handled. Use parts from the shipping
tube and hold them by the ends (not he pins). Don't touch the pins.
Tricks to counter the leakages.
Use an external diode pair (similar to the ESD diodes) and apply a
variable bias on each end to balance out the leakages.
If the leakage is high in one direction, use a single external diode
with variable bias (pot) in the other direction to counteract the
leakages.
If the leakages are very small. Place a single wire "probe" close, but
not in contact with, the input. Apply a bias voltage to the probe to
cancel out the leakages.
In other words, use a controlled leakage to counteract a uncontrolled
leakage.
> I have the following questions:
> 1. What causes the change in output voltage of the opamp if I change
> the length of the wire connected to the floating non-inverting input?
Greater surface area = greater leakages or leakage paths. You could
also be picking up stray RF or ionization. Increasing the surface area
also increases ionization pickup.
> 2. If this is not the best way (quite possible!) to measure
> electrostatical charges, then how can I do it better? Needless to say
> that even an input impedance in the 100 Meg range is much too low to
> measure weak electrostatic charges with any degree of accuracy.
Use a newer generation of op-amp. The RCA is kinda' old. Current
op-amps have input currents of 100fA or less and input R's around 1
Teraohm.
> 3. There is equipment to measure static charge, that is used, among
> other things, for workplace ESD-certification. How do these meters
> work? (Yes, I also asked that question another article.)
Not really sure, I'll keep quiet and let someone else answer that.
> I'd be grateful for any kind of information. If there is anyone who is
> familiar with this kind of measurement technology, please contact me.
> I might be unable to check the newsgroups regularly, as I'm in the
> middle of moving to a new address, so if you post a reply to this,
> please send a copy also to me via Email to
fra...@euronet.nl.
> Thanks! - FvW
My experience has been from trying to measure the input bias currents
of our CMOS op-amps (~1 fA or 1x10-15).
Keithley is a great resource for low level measurements.
Check:
http://www.keithley.com
Contact them and ask for their "Low Level Measurements Techniques"
handbook. It gives some examples of how to measure charge.
Measuring these minute charges and currents *is* Voodoo science. You
have to think in a completely different way than you are used to.
There are a lot of little things to keep track of at these currents.
IT IS NOT EASY AT ALL!
Good Luck,
Paul Grohe
http://tinyurl.com/p25zsjh
===================================================================
3. Cleaning Plastic Package
Paul Grohe
11/5/97
On Tue, 04 Nov 1997 02:06:41 -0500,
in the newsgroup sci.electronics.design,
Phil Maiorana <
pmai...@earthlink.net>
from Biomega Engineering thoughtfully posted:
> You can easily achieve pico amp performance by using an electrometer
grade op-amp
> such as Burr Brown's OPA128: you need a bias current that is at least
an order of
> magnitude less than your minimum measurement current. This is a costly
solution.
> Some of the newer CMOS op-amps (e.g National Semiconductor's LMC
series) have
> electrometer class input bias currents, but I've never tried them in an
electrometer
> circuit (plastic packages are "leaky").
Actually, the plastic packages are VERY good, providing THEY ARE
CLEAN!!! They make very good "electrometer" parts. Try `em!
Plastic parts, fresh out of a factory sealed package, are
un-touched by human hands and are VERY clean.
Any "junk" (oils, dust, flux) between the pins will degrade the
leakage performance.
I have measured the leakages of the various packages, and the
plastic ones are sub-femtoamp. The worst packages are the ceramic
types.
If someone has a "Pizza-fest" at lunch, then handles the parts
without washing their hands, leakages will shoot up tremendously.
Worse, the oil will eventually collect dust and create a leakage
path.
Even the oils on "clean" hands can create leakage paths. If not
immediately, then later.
In short - You should avoid handling the parts, if possible.
Handle them by the ends of the leads, or the ends of the package,
as not to get any "gook" on the package between leads.
A bath in pure alcohol (or similar cleaner), then baked in an
oven at 85'C for an hour will clean the package up. Do not use
the isopropyl alcohol from the dime store!
If you can, avoid soldering the input pins. Solder flux can
create a very nasty leakage path. It does not take much!
We always recommend "up-in-the-air" wiring for any low-leakage
application. Lift the input leg and solder the wires to a
single-pin socket. Insert the lead into the socket instead of
soldering directly.
A little known ditty: For dual parts (LMC662), the lowest leakage
input is the non-inverting input of the second amplifier (pin 5).
It is *away* from the supply pin (pin 4 - `round the corner), and
pin 6 (next door) is usually at the same potential. So, use amp
"B" for your low-leakage circuitry. Shield or guard all power
traces and outputs all the way up to the package.
Also, avoid input voltages 0.5 to 1V from the rails, as the input
currents start to creep-up. Mid-supply is the best range. The
input "leakage" is really the miss-match between the two ESD
protection diodes, as the MOSFET inputs themselves are literally
"nothing".
Our lowest leakage part is still the LMC660/662 in the "N"
plastic DIP package. Out of a handful, you will probably find a
few of them less than 1fA, the rest around 2-3fA, and 5-8fA on a
"bad" day (at +/-7.5V supplies at room temp).
Cheers,
Paul Grohe
http://tinyurl.com/o8rt7c7
===================================================================
4. Layout For Lowest Leakage
Paul Grohe
1/27/99
On Mon, 25 Jan 1999 11:17:18 -0800,
in the newsgroup sci.electronics.design,
Gerry Schneider <
not_...@sympatico.ca>
from Bell Solutions thoughtfully posted:
> Paul Grohe wrote:
>
> > For lowest leakage currents, use the dual version and use the
> > second channel ("right side", pins 5,6,7) for the critical
> > circuit.
> Why's that, Paul? Is this standard for all NatSem parts?
Nope. It is due to the layout of the pins and not the properties
of devices. The singles, duals and quads are identical to each
other. The same is true for the "other guys" parts, too.
Lemme' explain:
Most "low leakage" circuits apply the critical signal path to the
non-inverting input.
Note the layout of the typical dual:
A Out V+
A -In B Out
A +In B -In
V- B +in
On channel "A" - the non-inverting input is located right next to
the negative supply pin. It does not take much "Gook(tm)" between
the adjacent pins to create some healthy leakage paths.
A little household dust, combined with some summertime moisture,
creates a nice leakage path between the pins that can easily
exceed the leakage of the op-amp itself.
However, channel B's non-inverting input (pin 5) is on the other
side of the package - well away from the power pin. You will need
to get a lot more "gook" on, and across, the package to create an
equivalent leakage path.
It is also easier to guard and shield pin 5 than it is to guard
and shield pin 3.
On a quad, all the non-inverting pins are located around power
supply pins, making guarding tough. Even a single has it's
non-inverting input next to V-.
Hope this clears up the misunderstanding. There is no difference
between the parts.
Cheers,
Paul Grohe
http://tinyurl.com/pgu5ecc
===================================================================
5. Latchup
Paul Grohe
5/5/97
On Sun, 04 May 1997 19:57:48 GMT,
in the newsgroup sci.electronics.design,
Pat...@Orrell.prestel.co.uk (Patrick)
from [not set] thoughtfully posted:
> Hi All
>
> Does anyone have any idea if applying signals to an IC is likely to
> cause more or less damage than when the chip has its supply off.
Depends on the available voltage and current available at the
pins. If it is less than a diode drop at less than 1uA, then it
should not be a big problem.
> I suppose it is difficult to generalise as it might be dependant on
> the IC
Yes. And dependant on the circuit.
Officially, we do not recommend or condone it.
You can get into trouble a few ways:
1. The inoperable circuit can load down any other circuits
connected at the same time.
2. The unconnected power supply lines can "float", causing the
unpowered chip to be at unpredictable levels. This can cause
input protection diodes to conduct. Anti-reversal clamping
Shottky diodes should be applied to the supply lines to make sure
they do not float past ground (ie: make sure V+ never goes lower
than ground or V- never goes above ground).
3. Trigger a latchup condition.
Here is a copy of my previous post on a similar subject of
"latchup". It is VERY simplified (it was for a non-electronics
group).
If you break down the IC into what it really is, it is just a
pile of P-N junctions. To isolate a device (transistor, diode,
resistor) from the "substrate", you create another junction,
basically a reversed bias diode, so that there is no conduction
from the circuit elements to the "substrate" (the silicon
"floor"). Think of this as a circuit with a reversed diode
connected from every circuit connection point to V-.
For everything to work right, it is assumed that the substrate is
at the lowest possible voltage potential (usually V-).
If the substrate voltage is brought *above* any other terminal,
these "junctions" (diodes) that were created to isolate now start
conducting, because they are now forward biased.
Some junctions create a parasitic junction similar to an SCR. If
just the right conditions are created, the SCR "gate" triggers
and the junction conducts until power is removed. This is the
classic "latchup" condition, and is very common in input stages,
and output stages.
This usually occurs if any pin has a stiff voltage applied to it
*before* the IC's power supplies are applied.
The most common "SCR Latchup" in an unpowered IC is where the V+
is terminal 1, the other pins are the "gate", and the V- is
terminal 2. Tripping the "gate" causes the conduction across the
chip, shorting V+ to V- until power is removed. Depending on the
system power supply, this "short circuit" current can be a few
mA, or a few amps. That's when things go "BOOM!". Usually the
chip just gets hot and may be *slightly* damaged (usually a shift
in offset voltage or other parameters).
IC designers try to design out possible "latch-up" conditions,
and also try to beef things up to prevent damage from latchups
should they occur. But there is no way to be completely safe.
CMOS and older bipolar parts are most susceptible.
Because of their very low operating currents, it does not take
much to latch up CMOS IC's, so never apply signals to a CMOS part
w/o power.
So, the rule of thumb is not to bring any of the inputs or
outputs above V+, or below V-, and not to apply any large current
sources to any pin before the power supplies are on.
If you must apply a voltage to an unpowered IC, always add a
resistor in series with the inputs to limit the current to a safe
value, say about 10K or so, to prevent triggering "latchup".
Cheers,
Paul Grohe
http://tinyurl.com/lnc3efq
===================================================================
6. Input Protection
Paul Grohe
6/24/97
On Mon, 23 Jun 1997 14:18:48 GMT,
in the newsgroup sci.electronics.design,
dm...@ois.com.au
from iiNet Technologies thoughtfully posted:
> Can some one please explain how in the Absolute Maximum Ratings for
> the LMC662 opamp, the max current at the input pin is rated to +/-
> 5mA. ??
The inputs of CMOS op-amps are protected by a pair of reversed biased
diodes from the input to each rail. They are there to protect the inputs
from ESD transients and other "abuse".
However, these diodes can be "turned on" by applying voltages to the
inputs
above or below the supply voltages ("rails").
The 5mA is the maximum current that could *safely* be "sourced" or "sunk"
from the diodes without causing damage to the diodes or the op-amp.
In reality, the current can exceed several dozen mA or more.
This is why it is recommended to place a current limiting resistor in
series with the input if there is a chance that the input could be
"accidentally" pulled above or below the supply lines (ie: signals coming
from other boards, signals generated by devices running from a higher
supply voltage, or signals from external jacks).
Normally, The feedback resistors provide the necessary current limiting,
but buffers and non-inverting amplifiers may need the limiting resistor
added to their input.
So, If you have a signal applied *directly* to an input of the op-amp,
there should be a 10K-100K resistor in series with the input.
|----------+
| |\ |
+--|-\ |
Rlimit | \----O-------
---/\/\/\-----|+/
10K |/
Compared to the Teraohms of equivalent CMOS input resistance, the 10K is
hardly noticed.
If you have any other questions about our parts, feel free to contact our
support group at
sup...@nsc.com or (39)558-9999.
Cheers,
Paul Grohe
http://tinyurl.com/p4oc7ph
===================================================================
7. Testing Op Amps
Paul Grohe
8/29/00
In the newsgroup sci.electronics.design.
"Aviv Kfir" <
ak...@isdn.net.il> from
Bezeq International Ltd. thoughtfully posted:
>Hi,
>
>does anyone know where can I get the details and meaning
>of each parameter in the data sheet of op-amlifier.
>I have already searched the Analog-devices, National, Maxim and Linear
>but I couldn't find any document that explains these parameters.
>
Shhh.....It's a secret...there are no standards - don't tell anybody...we
just make
`em up!! .:)
Appnote AN-24: A Simplified Test Set for Op Amp Characterisation.
http://www.national.com/an/AN/AN-24.pdf
Note - this is moved to
http://www.ti.com/lit/an/snoa637/snoa637.pdf
This describes the basic "op-amp test loop" for DC tests (PSRR, CMRR,
AVOL, Vos). Not
much has changed in the last 25 years since this document was written -
the basic
tests are the same. Most tests are very simple - and a few are require a
bit of
VooDoo.
BTW: This appnote describes the design of a production "test box" that
was used in
the days prior to automated testing when all production tests were done
by hand. An
operator inserted the device, ran the switch through the ranges and made
sure the
meter readings were within specification and that the oscilloscope traces
were within
the lines marked by grease pencils. Now we do all the same tests in
milliseconds with
modern testers.
There will never be a magic circuit that tests all amplifiers - high
speed devices
have different requirements than micropower devices. One size does not
fit all. Test
circuits must be designed for the particular op-amp family.
Here are some more references:
http://www.national.com/an/AN/AN-A.pdf
http://www.national.com/an/AN/AN-4.pdf
http://www.national.com/an/AN/AN-20.pdf
Also see "Appendix F: How to read a datasheet", written by Bob Pease,
located in the
back of our 1995 Op Amp databook (always overlooked). I can't find that
on line - so
you have to look in the book.
Analog Devices, LTC, and sometimes TI will usually put the test circuits
in the
datasheet. Particularly in their "precision" device datasheets - like the
OP-07/27/37
derivatives and the Instrumentation amps.
Cheers,
Paul Grohe
http://tinyurl.com/k987wrb
===================================================================
8. Op Amp as Comparator
Paul Grohe
11/8/01
On Wed, 07 Nov 2001 09:12:43 -0800,
in the newsgroup sci.electronics.design,
Howard Delman <
del...@blueneptune.com>
from Posted via Supernews,
http://www.supernews.com posted:
> I am considering using an op-amp (TI TLV2783) as a comparator. Simply
> -- there is no negative feedback. There is a bit of positive feedback
> for hysteresis. Over my many years, I've heard different discussions
> about whether or not this was "bad" for the op-amp. Some co-workers
> have suggested that slamming on op-amp's output against the rails was,
> for some ill-defined reasons, not wise. Does anyone here have real
> world experience with this?
I'll warn you: If you intend to design this into a commercial
application - better check with the manufacturer to make sure
that the device:
1. Can handle large *sustained* differential inputs.
2. Nothing "funny" happens when the output is driven hard
against the rail (ie: excessive supply current draw, latching).
3. No recovery time problems. Low power and micropower devices
may have a rough time coming out of hard saturation.
It's possible to use an op-amp, but we do not recommend it. If
you do use an op-amp, better torture your circuit (over expected
operating temperature/voltage range if possible) to make sure it
behaves as you expect.
If your application is power sensitive, comparators (particularly
CMOS ones) will draw much less supply current than comparable
op-amps. Since you don't care about output distortion, there's no
need to burn bias current in the output stage.
Cheers,
Paul Grohe
http://tinyurl.com/l47wtd8
===================================================================