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Jackie

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Mar 1, 2006, 4:07:33 PM3/1/06
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Hi, guys, I am a layman, I want to know the basic process of PCB.
I was told that the process is:
1. draw out the schematic of the circuit in the software: Orcad, PADS
DxDesigner, or something else.
2. generate the netlist of the schematic
3. the software will generate the PCB layout automatically according to
the netlist file
4. the PCB manufacturer will make the PCB according to the layout.

right? Thanks.

Spehro Pefhany

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Mar 1, 2006, 4:34:35 PM3/1/06
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On 1 Mar 2006 13:07:33 -0800, the renowned "Jackie"
<Shuangsh...@gmail.com> wrote:

>Hi, guys, I am a layman, I want to know the basic process of PCB.
>I was told that the process is:
>1. draw out the schematic of the circuit in the software: Orcad, PADS
>DxDesigner, or something else.
>2. generate the netlist of the schematic

So far, so good. You'd run design rule checks before generating the
netlist. You will likely have to create new schematic entities for
parts not in the libraries.

>3. the software will generate the PCB layout automatically according to
>the netlist file

No, there is quite a bit of manual work to get from the netlist to the
final layout. You'd want to set constraints on spacing and trace width
for an autorouter. You may wish to route manually, in which case the
program will typically keep you from creating a layout that does not
match the netlist and some of the constraints. You will have to do
much of the placement of parts manually. You will have to create the
board outline manually. Some of the processes can be iterative (you
may find that the parts won't fit on the outline you hoped to use, or
you may find that routing is impossible with the placement you have,
or you may have to add layers to the board). Footprints can be
associated with each component at the schematic stage or at this
stage. Generally you'll have to create new footprints for parts that
are not in the library.

>4. the PCB manufacturer will make the PCB according to the layout.
>
>right? Thanks.

When you're done the 'layout', you run Design Rule Checks to ensure
that the desired rules are not being violated. Then you generally
generate Gerber and Excellon files, which the PCB manufacturer can use
to generate film and 'drill tapes' (a file of instructions for the
drilling machines). Some PCB makers work with the design files
directly, which eliminates a step, but it's not a very important step,
and would usually be limited to one or two 'softwares'.

Best regards,
Spehro Pefhany
--
"it's the network..." "The Journey is the reward"
sp...@interlog.com Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog Info for designers: http://www.speff.com

Joel Kolstad

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Mar 1, 2006, 4:25:43 PM3/1/06
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"Jackie" <Shuangsh...@gmail.com> wrote in message
news:1141247253.2...@j33g2000cwa.googlegroups.com...

You're a little off on step 3... from a netlist, a PCB layout program will
pull a bunch of footprints from a library that came with the package or that
you've drawn and place them arbitrarily. Typically, then, you position them
the way you want them, and draw (route) the connecting traces between the pins
indicated by the layout program via the netlist. There are PCB tools that
contain both auto-placers and auto-routers, although given how quickly you can
drag the component footprints around yourself, auto-placers aren't used that
much and tend to not be very good. Auto-routers are used commonly, although
setting them up correctly can be somewhat time consuming for complex boards.
For something like a digital board with reasonably slow edge rates, however,
an auto-router can do in 5 minutes what might require many hours of manual
routing. (In many cases a good layout person can do a better job than an
auto-router, but often auto-routers are good enough -- or can be made good
enough with, say, half an hour of tweaking the results manually -- and it's
more important to get a board built quickly than make it look nice, minimize
the number of vias, etc.)

Finally, note that you can skip steps 1 and 2 if you desire -- PCB packages
will let you drop component footprints onto a board and start wiring them up,
so if you have no need for a formal schematic, you can potentially save time
on some designs by not bothering to enter one. Some PCB packages (e.g.,
Pulsonix) seem designed to encourage this approach, whereas some others (e.g.,
PADs) seem designed to discourage it, but they'll all bend to your will given
enough bludgeoning.

Jackie

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Mar 1, 2006, 4:27:29 PM3/1/06
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Thank you very much !
What is "Footprints"?

a7yvm1...@netzero.com

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Mar 1, 2006, 4:35:29 PM3/1/06
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right? Thanks. "

Nope. Between 2 and 3, insert a few steps.
No known software will just take a netlist and give you a layout.

You must have all schematic symbols in a "known good" condition, then
you have to have all PCB footprints in a "known good" condition. The
netlist merely connects the physical parts according to the logical
information in the schematic.

Then you have to design the outline of the PCB, what size and shape it
has, if there are mounting holes, if they are plated or not, if there
are "keep out" areas where you have special conditions apply (like
restricted height, etc..). You also need to keep track of any
electrical parameters like differential pairs, high voltages, min or
max trace lengths, etc...

Then you need to setup the board, number of layers, type of material,
thickness, via technology, etc... You also need to set up the CAD to
respect minimum trace widths, solder mask clearances, etc.

Big CAD packages let you define all these parameters at the schematic
level or the PCB level.

Then you place the parts. Autoplace in CAD software usually refers to
the software's ability to place parts in pre-determined areas as
opposed to a big pile of parts centered at 0,0. Again, you do all the
work.

Even after all this you need to then connect all the netlist in however
many layers of PCB you have deemed necessary for the job. By hand. CAD
software can sometimes try to guess how to terminate a particular bunch
of traces but again, you have to do this and it all depends on the
setup. Most of the time it makes unusable traces.

There are autorouters but you can't just click "go" and have it guess
everything. You still need to set it up, and they are usually
un-intuitive and have a steep, expensive learning curve.

Then ideally, you can have your artwork checked against the PCB
manufacturer's design rules, they usually will check things like drill
sizes and trace widths.

Of course, you didn't say what you want to do. If it's an 8 pin PIC
with a few resistors, you still go through the same steps but it's not
that painful. Some lightweight software like Eagle is actually pretty
easy to learn, I hear.

Big designs= big headaches = big $$$ for the CAD monkeys like me.

DJ Delorie

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Mar 1, 2006, 4:50:38 PM3/1/06
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"Jackie" <Shuangsh...@gmail.com> writes:
> What is "Footprints"?

Footprints are the copper patterns that represent a component's
physical layout on the board - pins, pads, silkscreen, holes, solder
mask, etc.

Spehro Pefhany

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Mar 1, 2006, 5:05:57 PM3/1/06
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On 1 Mar 2006 13:27:29 -0800, the renowned "Jackie"
<Shuangsh...@gmail.com> wrote:

>Thank you very much !
>What is "Footprints"?

A footprint is a layout entity that contains all the elements required
for the layout of a component. It would generally have the silk screen
outline, maybe assembly information, padstacks (which might involve
several layers each), and so on. This entity will be replicated for
every instance of each component that is associated with that
footprint.

For example, you could find one for the 0402 SMT package in the
library which comes with the software. It might be okay for your use,
or you might have to modify it or create your own, but you only have
to do that once for each unique footprint.

John Larkin

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Mar 1, 2006, 5:35:48 PM3/1/06
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On Wed, 1 Mar 2006 13:25:43 -0800, "Joel Kolstad"
<JKolstad7...@yahoo.com> wrote:


>Finally, note that you can skip steps 1 and 2 if you desire -- PCB packages
>will let you drop component footprints onto a board and start wiring them up,
>so if you have no need for a formal schematic, you can potentially save time
>on some designs by not bothering to enter one. Some PCB packages (e.g.,
>Pulsonix) seem designed to encourage this approach, whereas some others (e.g.,
>PADs) seem designed to discourage it, but they'll all bend to your will given
>enough bludgeoning.
>
>

PADS isn't bad. You just enter ECO mode and then do whatever you
like... add parts, add connections, route traces. It keeps an ECO file
of whatever you do. You can use the ECO file to back annotate a
schematic if you ever had one, or just delete it. But in reality we
always start with a schematic to document whatever the thing is.

We rarely autoroute. If you place things carefully and assign pins
intelligently, routing isn't usually hard, and we get much better and
prettier boards by hand routing. PADS typically makes such a mess of
autorouting that it takes more time to clean it up than it's worth,
and if you don't check carefully you can wind up with critical signals
making the grand tour of the board.

People can think strategically, autorouters can't.


John

David L. Jones

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Mar 1, 2006, 8:10:09 PM3/1/06
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My PCB Design tutorial might be of some help:
http://alternatezone.com/electronics/pcbdesign.htm

Dave :)

Joerg

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Mar 1, 2006, 8:11:14 PM3/1/06
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a7yvm1...@netzero.com wrote:

>
> Big CAD packages let you define all these parameters at the schematic
> level or the PCB level.
>

Small ones do, too :-)

>
> Of course, you didn't say what you want to do. If it's an 8 pin PIC
> with a few resistors, you still go through the same steps but it's not
> that painful. Some lightweight software like Eagle is actually pretty
> easy to learn, I hear.
>

Eagle is pretty easy to learn and for a beginner it might be the right
tool. It's integrated, meaning you can go from schematic to layout and
back and forth without a netlist or other hassle. What took me some time
was to learn the library editor to generate parts that aren't found in
the libraries (for some reason hardly any parts that I use are in
there...). The OrCad library editor was easier IMHO.


> Big designs= big headaches = big $$$ for the CAD monkeys like me.
>

I think Eagle can do up to 16 layers or so and boards the size of a
small kitchen table top. If that ain't a big design I don't know what
would be. Much less $$$ than others, which is what convinced me. A huge
downside though, at least for me, is the absence of a hierarchical
design methodology.

Since I don't do layouts I can't say much. Of course I tried it out a
bit. It's quite easy and even the autorouter did a pretty neat job.
However, as was already said, you cannot just hit "route", go have
coffee or tea and expect a flawless and nice layout to result.

Regards, Joerg

http://www.analogconsultants.com

Joerg

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Mar 1, 2006, 8:34:31 PM3/1/06
to
Hello David,

>
> My PCB Design tutorial might be of some help:
> http://alternatezone.com/electronics/pcbdesign.htm
>

Very nice!

I kind of disagree with the notion about star grounds but that's a whole
other topic.

<rant_mode> Now if you could convince some of the universities to
encourage their students to read your paper we might finally get some
competent engineers out of them again. </rant_mode>

Regards, Joerg

http://www.analogconsultants.com

David L. Jones

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Mar 1, 2006, 9:20:25 PM3/1/06
to
Joerg wrote:
> Hello David,
>
> >
> > My PCB Design tutorial might be of some help:
> > http://alternatezone.com/electronics/pcbdesign.htm
> >
>
> Very nice!

Thanks.

> I kind of disagree with the notion about star grounds but that's a whole
> other topic.

I know! :->
Trying to keep it to the lowest common denominator.

> <rant_mode> Now if you could convince some of the universities to
> encourage their students to read your paper we might finally get some
> competent engineers out of them again. </rant_mode>

You'll be pleased to know that several US universities (plus several in
other countries) are now including it as either reference material or
as a basis for their PCB design subjects.

One major european PCB software package has also included it in their
Help system.

Dave :)

DJ Delorie

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Mar 1, 2006, 10:16:34 PM3/1/06
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Joerg <notthis...@removethispacbell.net> writes:
> > Big designs= big headaches = big $$$ for the CAD monkeys like me.
>
> I think Eagle can do up to 16 layers or so and boards the size of a
> small kitchen table top. If that ain't a big design I don't know what
> would be.

gEDA and PCB can be used to make boards up to, um, [does math], oh
boy, 0.3 miles square. I don't think anyone's tried that. I just
tried some big ones, it handles 333 feet square before my working copy[*]
segfaults, probably due to buffer overflow trying to print those
numbers. That's with 0.01 mil resolution. The official version stops
at 30 inches, but that's a leftover from an old design.

As for layers, it's a compile time constant. I've tested it with up
to 50-something layers. The UI gets ugly at that point, but it
functions. Default is 8 layers.

Oh, and gEDA and PCB are free (cost and license). So, other packages
might have more polish and glitter, but there's no reason to use cost
as an excuse to avoid big designs.


http://www.geda.seul.org/
http://pcb.sourceforge.net/

[*] http://www.delorie.com/pcb/

DJ Delorie

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Mar 1, 2006, 10:28:03 PM3/1/06
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DJ Delorie <d...@delorie.com> writes:
> gEDA and PCB can be used to make boards up to, um, [does math], oh
> boy, 0.3 miles square. I don't think anyone's tried that. I just
> tried some big ones, it handles 333 feet square before my working copy[*]
> segfaults, probably due to buffer overflow trying to print those

Got it. 21,474,836 mils == 21,474 inches == 1789 feet per side == 1/3
mile. It crashed when I tried 40,000,000 mils, which exceeds the 2^31
range for signed 0.01 mil units. dsub-9 connectors are *really* small
on the screen.

Paul Burke

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Mar 2, 2006, 3:33:44 AM3/2/06
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Jackie wrote:

> 1. draw out the schematic of the circuit in the software: Orcad, PADS
> DxDesigner, or something else.
> 2. generate the netlist of the schematic
> 3. the software will generate the PCB layout automatically according to
> the netlist file
> 4. the PCB manufacturer will make the PCB according to the layout.

The procedure used to be:

(1) Draw out the schematic on a collection of fag packets, old
envelopes, and scraps of paper, mostly in lunch and tea breaks, or at
home, because all the time at work is spent in "meetings" with
customers, the boss, or discussing football or rock music.
(2) Give the said collection to the drawing office.
(3) A week later, check the print of the beautifully drawn ink-on-paper
schematic. Find that they've drawn big round dots wherever one line
crosses another. Mark the wrong ones in red felt-tip. The same for all
pin numbers, where consistently 0 has been read as 8 and vice-versa.
(4) Meanwhile, the boss has taken another copy, marked it "LATEST
VERSION" in large green letters, and put it in a filing cabinet.
(5) Return the drawing to the drawing office. Mike is off sick, so wait
3 weeks for the corrected drawing to come back.
(6) Repeat 3 to 5 until you can stand it no more, and just remember what
differences there are between the dreawing and the circuit you wnat.
Note that the boss now has 7 different copies of the drawing, all
labelled "LATEST VERSION", and all undated. They are filed in no
particular order.
(7) Get a big sheet of squared draughting film, and 2 big pieces of
acetate sheet. Tape them together.
(8) Get out the required footprints. Find that you are short of a couple
of types. Order them in, and rub down the rest.
(9) A week later, when the footprints arrive, lay them out too.
(10) Use crepe tape to place the tracks, rubbing down pads as vias where
necessary. Find that you haven't left enough room between some
components, and have to rip them up, scrape off the footpints, rub down
new ones in the changed location, and replace the tracks.
(11) Interrupt a colleague and persuade him to stop discussing football,
and help you to check the schematic against the layout. Correct errors.
Forget the bits the draughtsman got wrong in (5), and 'correct' them too.
(12) Send the completed layout to the PCB manufacturer. Because the
photography cost is £200, the boss has demanded that you have 50 off made.
(13) 6 weeks later (guaranteed 15 working days, but who's to say which
days they actually work) the PCBs arrive.
(14) Check with a meter. Dead short between power rails- THAT was what
the draughtsman got wrong, and what you'd forgotten about in (11). Cut
the offending trace with a scalpel, cutting your thumb in the process.
(15) Populate the PCB with components. Power up. Observe volume and
location of smoke.
(16) Find that, while most databooks give the pinout looking from the
top, a few critical components have the pinout looking from underneath.
These of course are the most expensive and on long delivery times.
(17) The prototype now has some components soldered on top and some
others on the bottom. But at least it powers up.
(18) Start functional testing. Find that this particular manufacturer
likes to label his data bus with DB1 as the MOST significant bit. That
means that, after assembling the source code (which only takes 25
minutes for the 2k test program), you have to manually reverse all the
bits before you program the EPROM. Detail the office whizkid to write a
program to do it automatically, and call it a security feature, before
the boss finds out.
(19) Go on a LONG holiday, after which you put in your notice and get
another job.

Paul Burke

Joerg

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Mar 2, 2006, 1:48:09 PM3/2/06
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Hello DJ,

>
> gEDA and PCB can be used to make boards up to, um, [does math], oh
> boy, 0.3 miles square. I don't think anyone's tried that. I just
> tried some big ones, it handles 333 feet square before my working copy[*]
> segfaults, probably due to buffer overflow trying to print those
> numbers. That's with 0.01 mil resolution. The official version stops
> at 30 inches, but that's a leftover from an old design.
>
> As for layers, it's a compile time constant. I've tested it with up
> to 50-something layers. The UI gets ugly at that point, but it
> functions. Default is 8 layers.
>

Pretty impressive. However, in my experience a board of that caliber
leads to some problems. Solderability, warping, alignment, just to name
a few.


> Oh, and gEDA and PCB are free (cost and license). So, other packages
> might have more polish and glitter, but there's no reason to use cost
> as an excuse to avoid big designs.
>
> http://www.geda.seul.org/
> http://pcb.sourceforge.net/
>

The shareware concept is great. But timely support is also a big issue
in the CAD world. Eagle isn't really a huge cost issue either. For the
full version each part is under $500 and there are only three:
Schematic, layout and auto-router (which many folks like me don't need).

What I really like about it is the fully integrated environment. For a
beginner like the OP I believe that would be a key requirement.

Regards, Joerg

http://www.analogconsultants.com

Joerg

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Mar 2, 2006, 1:52:12 PM3/2/06
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Hello David,


>><rant_mode> Now if you could convince some of the universities to
>>encourage their students to read your paper we might finally get some
>>competent engineers out of them again. </rant_mode>
>
> You'll be pleased to know that several US universities (plus several in
> other countries) are now including it as either reference material or
> as a basis for their PCB design subjects.
>

Great. Now they just have to require the students to do something
practical with it. I have encountered numerous cases where freshly
minted engineers could not even solder (!) <gasp>. To me that's like a
tile setter who can't mix mortar.


> One major european PCB software package has also included it in their
> Help system.
>

If it's not Cadsoft Eagle it might be worth a mention on their support
forums.

Regards, Joerg

http://www.analogconsultants.com

DJ Delorie

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Mar 2, 2006, 2:12:23 PM3/2/06
to

Joerg <notthis...@removethispacbell.net> writes:
> Pretty impressive. However, in my experience a board of that caliber
> leads to some problems. Solderability, warping, alignment, just to
> name a few.

On our list, the concerns were shipping and finding a big enough card
cage ;-)

> > Oh, and gEDA and PCB are free (cost and license). So, other packages
> > might have more polish and glitter, but there's no reason to use cost
> > as an excuse to avoid big designs.
> > http://www.geda.seul.org/
> > http://pcb.sourceforge.net/
>
> The shareware concept is great.

gEDA and PCB aren't shareware. Unlike shareware (which, I think,
is/was a trademarked term for a very specific distribution plan), gEDA
and PCB are non-prorietary, and don't require payment.

> But timely support is also a big issue in the CAD world.

Hmm... our average turnaround on critical bugs is minutes. But yeah,
we don't have a large team of developers with lots of time to work on
bug fixing. PCB has, er, two people working on it regularly in their
spare time. I suspect anyone who was willing to pay for a fix
wouldn't have trouble convincing us, though.

> Eagle isn't really a huge cost issue either. For the full version
> each part is under $500 and there are only three: Schematic, layout
> and auto-router (which many folks like me don't need).
>
> What I really like about it is the fully integrated environment. For
> a beginner like the OP I believe that would be a key requirement.

I wasn't trying to compare pcb and eagle; each has their strong
points. Just pointing out that in the "big projects cost money"
argument, there's a zero cost software option available that supports
arbitrarily big projects.

JeffM

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Mar 2, 2006, 2:17:41 PM3/2/06
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>Eagle can do up to 16 layers or so
> Joerg
>
NOTE: That's COPPER layers--there's still lots left for silk,
soldermask, keepout, etc.
http://www.google.com/search?q=cadsoft+16-signal-layers+255-drawing-layers
.
.

>and boards the size of a small kitchen table top
>
What's the name of that place where you come from? Brobdingnag?
Wherever is is, they must have HUGE kitchen tables there.
http://www.google.com/search?q=cadsoft+64-x-64

JeffM

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Mar 2, 2006, 2:24:05 PM3/2/06
to
> The procedure used to be:
>(1) Draw out the schematic on a collection of fag packets,
>old envelopes, and scraps of paper, mostly in lunch and tea breaks,
>or at home, because all the time at work is spent in "meetings"
>with customers, the boss, or discussing football or rock music.
>.

>.
>(19) Go on a LONG holiday, after which you put in your notice
>and get another job.
> Paul Burke

Ah. A variation on a theme that complements Ken Smith's gem:
http://groups.google.com/group/sci.electronics.design/browse_frm/thread/85d427921d4ae936/4f65710c80ef5961?q=the-main-stepps-involved-in-circuit-board-design

and the addendum by George Gonzalez:
http://groups.google.com/group/sci.electronics.design/browse_frm/thread/c50de971e779f7e8/c32c0c19ccd2080e?q=you-could-add-a-few-more

Joerg

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Mar 2, 2006, 2:30:55 PM3/2/06
to
Hello Jeff,


>>and boards the size of a small kitchen table top
>
> What's the name of that place where you come from? Brobdingnag?
> Wherever is is, they must have HUGE kitchen tables there.
> http://www.google.com/search?q=cadsoft+64-x-64
>

Like in Gulliver's land where I come from the kitchen was "the" place to
congregate in the house. So 64" by 64" was considered smallish :-)

Actually, when I look at the open counter in our kitchen today I find
that it is more than 10 feet long. This is at the same time the center
of the house. When visitors come over they tend to all stand around that
counter, beer in hand, talking and watching what's cooking. So maybe
times haven't changed all that much.

Regards, Joerg

http://www.analogconsultants.com

David L. Jones

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Mar 2, 2006, 7:02:25 PM3/2/06
to
Joerg wrote:
> Hello David,
>
> >><rant_mode> Now if you could convince some of the universities to
> >>encourage their students to read your paper we might finally get some
> >>competent engineers out of them again. </rant_mode>
> >
> > You'll be pleased to know that several US universities (plus several in
> > other countries) are now including it as either reference material or
> > as a basis for their PCB design subjects.
> >
>
> Great. Now they just have to require the students to do something
> practical with it. I have encountered numerous cases where freshly
> minted engineers could not even solder (!) <gasp>. To me that's like a
> tile setter who can't mix mortar.

Yep, all too common unfortunately, same here in Australia.
I've met grads and even so called experienced grads who can't use a
meter or scope, or don't know what the beta of a transistor is.
It's amazing how a few very simple technical questions in an interview
will easily weed out the no-hopers from the ones with a clue.

Dave :)

Joerg

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Mar 2, 2006, 7:22:32 PM3/2/06
to
Hello David,

>
> Yep, all too common unfortunately, same here in Australia.
> I've met grads and even so called experienced grads who can't use a
> meter or scope, or don't know what the beta of a transistor is.
> It's amazing how a few very simple technical questions in an interview
> will easily weed out the no-hopers from the ones with a clue.
>

When hiring analog engineers I only needed to ask one question. Gave
them a single-BJT RF amp schematic and asked what they would do to
stretch the high frequency gain a little. If they couldn't answer that
this was pretty much the end of the interview.

Regards, Joerg

http://www.analogconsultants.com

Joel Kolstad

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Mar 2, 2006, 7:35:25 PM3/2/06
to
"Joerg" <notthis...@removethispacbell.net> wrote in message
news:c%LNf.17486$rL5....@newssvr27.news.prodigy.net...

> When hiring analog engineers I only needed to ask one question. Gave them a
> single-BJT RF amp schematic and asked what they would do to stretch the high
> frequency gain a little.

Were you looking for suggestions of passives to add/change or was "I'd buy a
better transistor" considered a sufficient answer? :-)


RST Engineering (jw)

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Mar 2, 2006, 7:40:38 PM3/2/06
to
WEll, man, don't keep us in suspenders. Pass the schematic on and let us
take a crack at it. Other than rebiasing it for max GBW or tossing in a
peaking coil of some sort, I'd be hard pressed to stretch something that is
unstretchable. Doesn't the device itself set the limits on high frequency
gain? Unless you've purposely done some sort of feedback to limit the high
end.

Jim

Joerg

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Mar 2, 2006, 7:56:50 PM3/2/06
to
Hello Joel,


>>When hiring analog engineers I only needed to ask one question. Gave them a
>>single-BJT RF amp schematic and asked what they would do to stretch the high
>>frequency gain a little.
>
> Were you looking for suggestions of passives to add/change or was "I'd buy a
> better transistor" considered a sufficient answer? :-)
>
>

It was more along the line "... for an additional 2 cents" :-)

Regards, Joerg

http://www.analogconsultants.com

Joerg

unread,
Mar 2, 2006, 8:07:26 PM3/2/06
to
Hello Jim,


> WEll, man, don't keep us in suspenders. Pass the schematic on and let us
> take a crack at it. Other than rebiasing it for max GBW or tossing in a
> peaking coil of some sort, I'd be hard pressed to stretch something that is
> unstretchable. Doesn't the device itself set the limits on high frequency
> gain? Unless you've purposely done some sort of feedback to limit the high
> end.
>

It was pretty simple. Hotshot RF transistor, biased at 8mA or so,
collector resistor, emitter resistor (that's where they'd have to put a
series RC across). IOW the stuff in the "Basics" section of AoE. Believe
it or not, most wouldn't know. And I am pretty sure they didn't know
what AoE is either.

The candidate that passed I asked what he'd do if he had to drive
something capacitive really hard and fast. Then he began to sketch how
he'd done that to drive inkjet cartridge piezos. Well, I hired him and
he still works there :-)

Regards, Joerg

http://www.analogconsultants.com

John Larkin

unread,
Mar 2, 2006, 8:17:24 PM3/2/06
to

Good interview question:

What's the last thing you worked on? Sketch some schematics.

If they mutter something about it being proprietary, subtract 5 points
and try another approach.

John


Joerg

unread,
Mar 2, 2006, 8:31:57 PM3/2/06
to
Hello John,

>
> Good interview question:
>
> What's the last thing you worked on? Sketch some schematics.
>
> If they mutter something about it being proprietary, subtract 5 points
> and try another approach.
>

Oh, I told them right up front not to devulge anything about previous
jobs. This stuff had been published. But it wouldn't have mattered
whether he was the originator or not. What matters to me is whether they
are able to find out. If someone would have said "Page xyz in AoE" that
answer would have been good enough.

Regards, Joerg

http://www.analogconsultants.com

DJ Delorie

unread,
Mar 2, 2006, 9:02:28 PM3/2/06
to

Joerg <notthis...@removethispacbell.net> writes:
> When hiring analog engineers I only needed to ask one question. Gave
> them a single-BJT RF amp schematic and asked what they would do to
> stretch the high frequency gain a little. If they couldn't answer that
> this was pretty much the end of the interview.

I did a software interview like that once. "Here's a computer. Write
me a tic tac toe program using XYZ. You have 30 minutes. Begin". 30
minutes later, I knew how well he knew that software.

Homer J Simpson

unread,
Mar 2, 2006, 9:20:18 PM3/2/06
to

"DJ Delorie" <d...@delorie.com> wrote in message
news:xnfym0i...@delorie.com...

> I did a software interview like that once. "Here's a computer. Write
> me a tic tac toe program using XYZ. You have 30 minutes. Begin". 30
> minutes later, I knew how well he knew that software.

That's like asking a carpenter to hammer in a nail.


DJ Delorie

unread,
Mar 2, 2006, 9:30:37 PM3/2/06
to

"Homer J Simpson" <nob...@nowhere.com> writes:
> > I did a software interview like that once. "Here's a computer. Write
> > me a tic tac toe program using XYZ. You have 30 minutes. Begin". 30
> > minutes later, I knew how well he knew that software.
>
> That's like asking a carpenter to hammer in a nail.

Depends what XYZ is. More like asking a carpenter to *design* a
house, or plan how to build it (like a GC). In my case, XYZ was GUI
toolkit, and it took most of the 30 minutes just to plan the whole
thing. Watching how he approached the problem told me a lot.

Joerg

unread,
Mar 2, 2006, 10:04:52 PM3/2/06
to
Hello Homer,

>
>>I did a software interview like that once. "Here's a computer. Write
>>me a tic tac toe program using XYZ. You have 30 minutes. Begin". 30
>>minutes later, I knew how well he knew that software.
>
> That's like asking a carpenter to hammer in a nail.
>

Which doesn't mean everybody can do it. When I repaired part of a stair
case that had fallen apart I quickly realized why it had: Six out of six
nails had missed the beams underneath. They were just kind of dangling
there.

Regards, Joerg

http://www.analogconsultants.com

Homer J Simpson

unread,
Mar 3, 2006, 12:31:17 AM3/3/06
to

"Joerg" <notthis...@removethispacbell.net> wrote in message
news:onONf.18392$2O6....@newssvr12.news.prodigy.com...

Perhaps his test was "saw a bit of wood"!

Rich The Newsgroup Wacko

unread,
Mar 3, 2006, 11:47:06 AM3/3/06
to

I can't understand it! I've cut this damn board THREE TIMES and it's
_still_ too short!
--
Cheers!
Rich

Joel Kolstad

unread,
Mar 3, 2006, 11:54:14 AM3/3/06
to
"Joerg" <notthis...@removethispacbell.net> wrote in message
news:onONf.18392$2O6....@newssvr12.news.prodigy.com...
> Which doesn't mean everybody can do it. When I repaired part of a stair case
> that had fallen apart I quickly realized why it had: Six out of six nails
> had missed the beams underneath. They were just kind of dangling there.

I figure the first time you hit your heard on an exposed roofing nail in your
attic, while you're sitting there contemplating what a lovely mess of red your
hair's going to be (since scalps like to bleed so profusely) and when you had
your last tentanus shot -- that's a good time to take a good long look at the
roof, and see how often the roofers missed the framing... and mentally review
the likelihood of hurricanes or tornados where you live.

:-)


RST Engineering (jw)

unread,
Mar 3, 2006, 12:13:13 PM3/3/06
to
And if (s)he was REALLY on the ball, they'd take lead length of the
capacitor into account as an inductor and give you a series resonant short
circuit at the frequency of interest across the emitter resistor.

Jim

Joerg

unread,
Mar 3, 2006, 3:18:31 PM3/3/06
to
Hello Jim,


> And if (s)he was REALLY on the ball, they'd take lead length of the
> capacitor into account as an inductor and give you a series resonant short
> circuit at the frequency of interest across the emitter resistor.
>

I wish. What I found a lot instead was that there were a great many
"engineers" who didn't even understand the basics of a single transistor
amplifier. I mean, they didn't seem to grasp how that thing would work
in the first place.

Regards, Joerg

http://www.analogconsultants.com

John Larkin

unread,
Mar 3, 2006, 3:40:19 PM3/3/06
to

Try this interview question:

+10v
|
|
|
c
+5v----------------b npn transistor
e
|
|
|
1k
|
|
|
|
gnd

What is the base voltage? (seriously!)

What is the emitter voltage?

What are the base, collector, and emitter currents?

Any other comments?

This one usually befuddles resume-heavy types. Maybe 10% of applicants
for ee or tech positions understand this circuit!

(Extra credit if he mentions oscillation)

I get great comments, like "the base voltage is 5, so the transistor
must be saturated, so the emitter voltage is 10" and "the base voltage
is 0.6"

If they can't handle that, try this

+10
|
|
|
3k
|
|
+------- ???
|
|
1k
|
|
|
gnd


or

+10
|
|
|
1k
|
|
+------- ???
|
|
1 uF
|
|
|
gnd


John

Rich Grise, but drunk

unread,
Mar 3, 2006, 3:58:03 PM3/3/06
to

Or, you've got a dark closet underneath a staricase, and you crawl in on
your knees to explore it, and discover the carpet strip the hard way. =:-O

Cheers!
Rich

--
-----BEGIN GEEK CODE BLOCK-----
Version: 3.1
GAT(E P) dpu s: a++ C++@ P+ L++>+ !E W+ N++ o? K? w-- !O !M !V PS+++
PE Y+ PGP- t 5+++)-; X- R- tv+ b+ DI++++>+ D-? G e+$ h+ r-- z+
------END GEEK CODE BLOCK------

Joerg

unread,
Mar 3, 2006, 5:42:34 PM3/3/06
to
Hello John,

>
> Try this interview question:
>
>
>
> +10v
> |
> |
> |
> c
> +5v----------------b npn transistor
> e
> |
> |
> |
> 1k
> |
> |
> |
> |
> gnd
>
>
>
> What is the base voltage? (seriously!)
>

Like, how many popes named Pius were there before Pope Pius the 12th?

>
> This one usually befuddles resume-heavy types. ...


These usually didn't even make it into my office. Credentials are very
low on my radar scope when hiring. With very few execptions I found that
excellent credentials are in no way an indication of true performance.
Much less so than callusses.

>
> (Extra credit if he mentions oscillation)
>

Considering what comes out of academia these days that would almost
warrant a Nobel prize nomination.

Regards, Joerg

http://www.analogconsultants.com

RST Engineering (jw)

unread,
Mar 3, 2006, 6:56:17 PM3/3/06
to
>
>
>
> +10v
> |
> |
> |
> c
> +5v----------------b npn transistor
> e
> |
> |
> |
> 1k
> |
> |
> |
> |
> gnd
>
>
>
> What is the base voltage? (seriously!)

Duh.

>
> What is the emitter voltage?

Silicon, germanium, or gallium arsenide transistor?

>
> What are the base, collector, and emitter currents?

Collector and emitter are equal and trivial to a first order (Ve/1k). Base
is indeterminate until you give me beta.


>
> Any other comments?

It ain't gonna oscillate as shown, even with the +5 at nearly zero impedance
IF the +10 is zero impedance and that dotted line from +10 to collector
doen't have little curlies on it.

>


>
> +10
> |
> |
> |
> 3k
> |
> |
> +-2½ volts measured with an infinite impedance meter. Lower as the
> meter z drops.


> |
> |
> 1k
> |
> |
> |
> gnd
>
>
> or
>
> +10
> |
> |
> |
> 1k
> |
> |

> +--I can't believe anybody above freshman ee would miss this one.
> |
> |
> 1 uF
> |
> |
> |
> gnd
>
>
> John
>


RST Engineering (jw)

unread,
Mar 3, 2006, 6:58:04 PM3/3/06
to
>
>
>
> +10v
> |
> |
> |
> c
> +5v----------------b npn transistor
> e
> |
> |
> |
> 1k
> |
> |
> |
> |
> gnd
>
>
>
> What is the base voltage? (seriously!)

Duh.

>
> What is the emitter voltage?

Silicon, germanium, or gallium arsenide transistor?

>


> What are the base, collector, and emitter currents?

Collector and emitter are equal and trivial to a first order (Ve/1k). Base


is indeterminate until you give me beta.


>
> Any other comments?

It ain't gonna oscillate as shown, even with the +5 at nearly zero impedance
IF the +10 is zero impedance and that dotted line from +10 to collector
doen't have little curlies on it.

>


>
> +10
> |
> |
> |
> 3k
> |
> |
> +-2½ volts measured with an infinite impedance meter. Lower as the
> meter z drops.
> |
> |

> 1k
> |
> |
> |
> gnd
>
>
> or
>
> +10
> |
> |
> |
> 1k
> |
> |

John Larkin

unread,
Mar 3, 2006, 7:44:29 PM3/3/06
to
On Fri, 3 Mar 2006 15:56:17 -0800, "RST Engineering \(jw\)"
<j...@rstengineering.com> wrote:


>It ain't gonna oscillate as shown, even with the +5 at nearly zero impedance
>IF the +10 is zero impedance and that dotted line from +10 to collector
>doen't have little curlies on it.

Try it with a 2N2219 and get back to me.

John


John Larkin

unread,
Mar 3, 2006, 10:30:17 PM3/3/06
to
On Fri, 03 Mar 2006 20:58:03 GMT, "Rich Grise, but drunk"
<yahr...@example.net> wrote:

>On Fri, 03 Mar 2006 08:54:14 -0800, Joel Kolstad wrote:
>
>> "Joerg" <notthis...@removethispacbell.net> wrote in message
>> news:onONf.18392$2O6....@newssvr12.news.prodigy.com...
>>> Which doesn't mean everybody can do it. When I repaired part of a stair case
>>> that had fallen apart I quickly realized why it had: Six out of six nails
>>> had missed the beams underneath. They were just kind of dangling there.
>>
>> I figure the first time you hit your heard on an exposed roofing nail in your
>> attic, while you're sitting there contemplating what a lovely mess of red your
>> hair's going to be (since scalps like to bleed so profusely) and when you had
>> your last tentanus shot -- that's a good time to take a good long look at the
>> roof, and see how often the roofers missed the framing... and mentally review
>> the likelihood of hurricanes or tornados where you live.
>>
>> :-)
>
>Or, you've got a dark closet underneath a staricase, and you crawl in on
>your knees to explore it, and discover the carpet strip the hard way. =:-O
>
>Cheers!
>Rich

Sorta like stepping on an upside-down DIP16 barefoot.

John

Spehro Pefhany

unread,
Mar 3, 2006, 10:56:30 PM3/3/06
to

Socks don't make much difference.


Best regards,
Spehro Pefhany
--
"it's the network..." "The Journey is the reward"
sp...@interlog.com Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog Info for designers: http://www.speff.com

Michael A. Terrell

unread,
Mar 4, 2006, 3:23:24 AM3/4/06
to


40 pins seem to be more common under my bench. That's why I won't go
out to the shop barefoot. They are hard enough to pry out of my shoes,
and with circulation problems, it wout take months to heal.


--
Service to my country? Been there, Done that, and I've got my DD214 to
prove it.
Member of DAV #85.

Michael A. Terrell
Central Florida

RST Engineering (jw)

unread,
Mar 4, 2006, 4:54:57 PM3/4/06
to
Don't have some in the stockroom or in the engineering junkbox stock.
What's special about the 2219 and will anything else exhibit this behavior?

Jim


"John Larkin" <jjla...@highNOTlandTHIStechnologyPART.com> wrote in message
news:bloh02p3l4l79kei6...@4ax.com...

John Larkin

unread,
Mar 4, 2006, 5:53:03 PM3/4/06
to
On Sat, 4 Mar 2006 13:54:57 -0800, "RST Engineering \(jw\)"
<j...@rstengineering.com> wrote:

>Don't have some in the stockroom or in the engineering junkbox stock.
>What's special about the 2219 and will anything else exhibit this behavior?
>
>Jim
>
>

I'm guessing lots of transistors will oscillate as emitter followers.
The first time I saw this, I was doing a powerup-reset circuit for a
TTL system. +5 went to an R-C, then an emitter follower, then a TTL
gate. It wouldn't go high at the gate input, and we eventually figured
out that the transistor, a 2N2219, was oscillating violently at about
100 MHz.

The 2219 is a fast TO-5, and the relatively long wire bonds probably
figure in.

Really fast transistors, like an NE68039 or whatever, usually
oscillate as emitter followers or differential pairs. Adding a bit of
series resistance at the base, 33 ohms maybe, generally fixes it.
Collector resistance can stop it too, but usually a lot more ohms.

Power mosfets tend to do this too, and the fix is a bit of gate
resistance. An opamp driving a power mosfet with an ungrounded source
will often oscillate too... the opamp output doesn't look resistive
enough.

I recently did a current source with a small PNP transistor, BCX71 as
I recall, inside the loop of an opamp. Yup, it oscillated. Rather than
kluging a resistor into a very dense circuit, I substituted one of
those "digital transistors", the ones with integral base resistors.


John


Spehro Pefhany

unread,
Mar 4, 2006, 6:09:06 PM3/4/06
to
On Sat, 04 Mar 2006 14:53:03 -0800, the renowned John Larkin
<jjla...@highNOTlandTHIStechnologyPART.com> wrote:

>
>I recently did a current source with a small PNP transistor, BCX71 as
>I recall, inside the loop of an opamp. Yup, it oscillated. Rather than
>kluging a resistor into a very dense circuit, I substituted one of
>those "digital transistors", the ones with integral base resistors.
>John

You used a digital transistor in an analog circuit? I'm appalled or
aghast, whichever is worse. ;-)

RST Engineering (jw)

unread,
Mar 4, 2006, 6:12:23 PM3/4/06
to
Y'know, the reason I've probably never seen it is that my first solid state
grad school class was taught by an old warhorse by the name of Bill Brown at
San DIego State. He told us that the transistor case parasitics would cause
an emitter follower to oscillate because of the inductance inherent in the
large transistor cases at the time. He cautioned us always to use a hundred
ohms or so in series with the base lead and we'd never have to worry about
it. I just took his advice, used the series resistor, and never had the
thing sing on me.

Just for giggles, I think I'll gin one up and use purposely long (1" or so)
leads on an RF device I've come to love (2N5770) and fire up the spectrum
analyzer to see if and where it goes bananas.

My original comment stands, though. Unless that +10 supply with the dotted
lines going to the collector has some curlies on the lines (inductors) that
sucker will NOT oscillate.

John Larkin

unread,
Mar 4, 2006, 8:03:40 PM3/4/06
to
On Sat, 04 Mar 2006 18:09:06 -0500, Spehro Pefhany
<spef...@interlogDOTyou.knowwhat> wrote:

>On Sat, 04 Mar 2006 14:53:03 -0800, the renowned John Larkin
><jjla...@highNOTlandTHIStechnologyPART.com> wrote:
>
>>
>>I recently did a current source with a small PNP transistor, BCX71 as
>>I recall, inside the loop of an opamp. Yup, it oscillated. Rather than
>>kluging a resistor into a very dense circuit, I substituted one of
>>those "digital transistors", the ones with integral base resistors.
>>John
>
>You used a digital transistor in an analog circuit? I'm appalled or
>aghast, whichever is worse. ;-)
>

Aghast hurts a lot more.

John


John Larkin

unread,
Mar 4, 2006, 8:09:44 PM3/4/06
to
On Sat, 4 Mar 2006 15:12:23 -0800, "RST Engineering \(jw\)"
<j...@rstengineering.com> wrote:

>Y'know, the reason I've probably never seen it is that my first solid state
>grad school class was taught by an old warhorse by the name of Bill Brown at
>San DIego State. He told us that the transistor case parasitics would cause
>an emitter follower to oscillate because of the inductance inherent in the
>large transistor cases at the time. He cautioned us always to use a hundred
>ohms or so in series with the base lead and we'd never have to worry about
>it. I just took his advice, used the series resistor, and never had the
>thing sing on me.

>My original comment stands, though. Unless that +10 supply with the dotted
>lines going to the collector has some curlies on the lines (inductors) that
>sucker will NOT oscillate.
>

So you are saying that I'm either lying or stupid. So why do you
continue to use base resistors?

John


RST Engineering (jw)

unread,
Mar 5, 2006, 2:44:45 PM3/5/06
to
I'm saying neither. I continue to use base resistors so I don't have to
worry about whether or not the collector is AC grounded to the center of the
earth. I also use them for the same reason I throw a pinch of salt over my
shoulder every morning -- it keeps the giraffes away.

You don't need to get testy with me.

Jim

John Larkin

unread,
Mar 5, 2006, 3:23:30 PM3/5/06
to
On Sun, 5 Mar 2006 11:44:45 -0800, "RST Engineering \(jw\)"
<j...@rstengineering.com> wrote:

>I'm saying neither. I continue to use base resistors so I don't have to
>worry about whether or not the collector is AC grounded to the center of the
>earth. I also use them for the same reason I throw a pinch of salt over my
>shoulder every morning -- it keeps the giraffes away.
>
>You don't need to get testy with me.
>
>Jim
>


I'm not the slightest testy, I'm just trying to understand the logic
of your position. As I see it,


Your EE prof told you that emitter followers tend to oscillate.

I told you that emitter followers tend to oscillate.

You use base resistors to keep your emitter followers from
oscillating.

You deny that emitter followers tend to oscillate.

Just trying to understand.

John


RST Engineering (jw)

unread,
Mar 5, 2006, 3:31:53 PM3/5/06
to

"John Larkin" <jjla...@highNOTlandTHIStechnologyPART.com> wrote in message
news:6shm02905363dub2q...@4ax.com...

> I'm not the slightest testy, I'm just trying to understand the logic
> of your position. As I see it,
>
>
> Your EE prof told you that emitter followers tend to oscillate.

... unless you take pains to see that the collector is truly grounded for
AC.


>
> I told you that emitter followers tend to oscillate.

>
> You use base resistors to keep your emitter followers from
> oscillating.

... unless you take pains to see that the collector is truly grounded for
AC.


>
> You deny that emitter followers tend to oscillate.

... unless you take pains to see that the collector is truly grounded for
AC.


>
>
>
> Just trying to understand.

Just trying to say that ... unless you take pains to see that the collector
is truly grounded for AC ... the sucker WILL oscillate.

Jim


John Larkin

unread,
Mar 5, 2006, 3:43:59 PM3/5/06
to

Except that the better you bypass the collector, the harder it
oscillates.

The reason most people don't see this is probably because it's unusual
to drive an emitter follower from a very stiff signal source; just a
little loss in the base will usually kill the squirrels.

Slow SOT-23s will often be stable, presumably because they have short
wirebonds. But you can buy 5+ GHz npn's cheap nowadays, which more
than makes up the difference.


John


Joerg

unread,
Mar 5, 2006, 8:46:46 PM3/5/06
to
Hello John,


> ... But you can buy 5+ GHz npn's cheap nowadays, which more


> than makes up the difference.
>

Any favorites in that category? Under 5c? Always on the lookout for a
bargain :-)

Regards, Joerg

http://www.analogconsultants.com

John Larkin

unread,
Mar 5, 2006, 9:18:01 PM3/5/06
to
On Mon, 06 Mar 2006 01:46:46 GMT, Joerg
<notthis...@removethispacbell.net> wrote:

>Hello John,
>
>
>> ... But you can buy 5+ GHz npn's cheap nowadays, which more
>> than makes up the difference.
>>
>
>Any favorites in that category? Under 5c? Always on the lookout for a
>bargain :-)
>

My products are expensive, and I don't buy in huge volume, so I don't
usually sweat a few cents. I like the NEC parts, because they're good
and available. The NE680xx (10 GHz) parts cost roughly 50 cents at
100. I like the BFS17, because it's fast but no so fast that it's hard
to tame; it's about 20 cents in 100s.

There must be dirt-cheap RF transistors around. Actually, I do fast
time-domain stuff, not actual RF (sinewaves are boring) so I haven't
explored this terrain much.

John


Joerg

unread,
Mar 6, 2006, 4:40:56 PM3/6/06
to
Hello John,


> My products are expensive, and I don't buy in huge volume, so I don't
> usually sweat a few cents. I like the NEC parts, because they're good
> and available. The NE680xx (10 GHz) parts cost roughly 50 cents at
> 100. I like the BFS17, because it's fast but no so fast that it's hard
> to tame; it's about 20 cents in 100s.
>

50c is way above the pain threshold for most of my stuff. The BFS17 can
be had for under 8c. I always keep lots these on hand but it's tough to
net under 1nsec with them.


> There must be dirt-cheap RF transistors around. Actually, I do fast
> time-domain stuff, not actual RF (sinewaves are boring) so I haven't
> explored this terrain much.
>

Infineon has a lot but their distribution system, well, let's just say I
am not enthused about that.

Another thing I am looking for is a cheap enhancement n-channel, like
the 2N7002 but 1/5th or less of its silicon area so it has less
capacitance. Cheap meaning under 5c or at least under 10c. Many of the
RF FETs of the olden days are becoming hard to find because RF goes BJT
these days.

Regards, Joerg

http://www.analogconsultants.com

Ken Smith

unread,
Mar 6, 2006, 8:47:51 PM3/6/06
to
In article <21752$440b4ab3$42512d35$29...@DIALUPUSA.NET>,

RST Engineering \(jw\) <j...@rstengineering.com> wrote:
>
>"John Larkin" <jjla...@highNOTlandTHIStechnologyPART.com> wrote in message
>news:6shm02905363dub2q...@4ax.com...
>
>> I'm not the slightest testy, I'm just trying to understand the logic
>> of your position. As I see it,
>>
>>
>> Your EE prof told you that emitter followers tend to oscillate.
>
>... unless you take pains to see that the collector is truly grounded for

Take a look at a (Colpitts or is it Clapp) common collector oscillator.

It is very easy to make one of these when you don't want to. All it takes
is a longish base lead to make the inductance and some stry capacitance.

--
--
kens...@rahul.net forging knowledge

Jim Thompson

unread,
Mar 6, 2006, 8:51:57 PM3/6/06