How to invert output of NE555?
Slater
the output to be inverted, that is, normally high, but stays low for a
second when a low pulse is sent to the trigger input, then goes high
again. The obvious thing is to use a 74LS04, which I have, but is
there any way to achieve this without an additional IC or transistors?
Jon Danniken
How about a long duty cycle? This can be accomplished with a little signal
diode stuffed in the timing circuitry.
Here is one page describing this:
http://www.williamson-labs.com/555-circuits.htm
Jon
Jamie
What you're looking for is a delayed trigger ? If you're not using
edge triggering, then supply the trigger with a R and shunt a cap to
create a time delay on the trigger. The input of this circuit should be
pulled up via an R from the Vcc to ensure proper charging of this cap
for the next time cycle to be accurate or close to it..
If you are not using edge triggering, then you could use a 556 timer
(dual). The first stage to be used as a time delay for the second stage
on the trigger..
Jamie
Jamie
No matter what all the youngish try to do, they just can't kill
the use of a 555/C555 timer :)
Btw, that's a nice page.
Jamie
Bitrex
Hey Slater,
Here's a circuit I came up with that hopefully will do what you ask:
http://i227.photobucket.com/albums/dd240/bitrex2007/555pulser.jpg
At idle, the output pin is HIGH and the timing capacitor is charged up.
The negative-going pulse applied to the RESET input brings the output
low, and the capacitor discharges through the resistor until the voltage
on the capacitor reaches 1/3rd Vcc; the output is low for this time.
Then the TRIGGER input sets the output high again, and the capacitor is
quickly charged up again through the diode to prepare for the next pulse.
In the picture the purple pulse is the negative going pulse on the reset
input, and the green is the output.
Bitrex
The "low time" is approximately RC*log[Vcc/(3*(Vcc-0.6)].
Slater
I'll try Bitrex's solution, it's just what I need.
Jim Thompson
>Thank you all!
>I'll try Bitrex's solution, it's just what I need.
What was his suggestion? The post didn't show up here for some reason
:-(
...Jim Thompson
--
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| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
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| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
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Remember: Once you go over the hill, you pick up speed
Bitrex
> On Sat, 26 Mar 2011 16:53:58 GMT, non...@dico.no (Slater) wrote:
>
>> Thank you all!
>> I'll try Bitrex's solution, it's just what I need.
>
> What was his suggestion? The post didn't show up here for some reason
> :-(
>
> ...Jim Thompson
Here ya go:
http://i227.photobucket.com/albums/dd240/bitrex2007/555pulser.jpg
Negative going pulse at RESET gives a negative going one-shot at the
output, the "low time" is approximately RC*log[Vcc/(3*(Vcc-0.6))].
John Fields
<To-Email-Use-Th...@On-My-Web-Site.com> wrote:
>On Sat, 26 Mar 2011 16:53:58 GMT, non...@dico.no (Slater) wrote:
>
>>Thank you all!
>>I'll try Bitrex's solution, it's just what I need.
>
>What was his suggestion? The post didn't show up here for some reason
>:-(
---
Version 4
SHEET 1 880 704
WIRE 32 176 16 176
WIRE 272 176 256 176
WIRE 32 240 0 240
WIRE 320 240 256 240
WIRE 320 288 320 240
WIRE 32 304 -112 304
WIRE 32 368 -208 368
WIRE -336 432 -336 384
WIRE -208 432 -208 368
WIRE -112 432 -112 304
WIRE -80 432 -112 432
WIRE 0 432 0 240
WIRE 0 432 -16 432
WIRE 320 432 320 368
WIRE 320 432 0 432
WIRE -112 464 -112 432
WIRE 320 464 320 432
WIRE -336 560 -336 512
WIRE -304 560 -336 560
WIRE -336 592 -336 560
WIRE -208 592 -208 512
WIRE -208 592 -336 592
WIRE -112 592 -112 544
WIRE -112 592 -208 592
WIRE 320 592 320 528
WIRE 320 592 -112 592
WIRE -336 640 -336 592
FLAG -336 640 0
FLAG -336 384 +5
FLAG 272 176 +5
FLAG -304 560 0V
FLAG 16 176 0V
SYMBOL Misc\\NE555 144 272 R0
SYMATTR InstName U1
SYMBOL voltage -208 416 R0
WINDOW 3 24 104 Invisible 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value PULSE(12 0 0 1e-7 1e-7 1e-6 0 1)
SYMATTR InstName V1
SYMBOL res 304 272 R0
SYMATTR InstName R1
SYMATTR Value 47k
SYMBOL cap 304 464 R0
SYMATTR InstName C1
SYMATTR Value 4.7e-7
SYMBOL voltage -336 416 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 23 10 Left 0
WINDOW 3 24 104 Invisible 0
SYMATTR InstName V2
SYMATTR Value 5
SYMBOL res -128 448 R0
WINDOW 0 -40 54 Left 0
WINDOW 3 -44 83 Left 0
SYMATTR InstName R2
SYMATTR Value 10k
SYMBOL diode -80 448 R270
WINDOW 0 32 32 VTop 0
WINDOW 3 0 32 VBottom 0
SYMATTR InstName D1
SYMATTR Value 1N4148
TEXT -128 632 Left 0 !.tran 1
--
JF
John Fields
---
Oops...
V1 should idle at 5V, not 12V.
--
JF
Fred Bloggs
> On Sat, 26 Mar 2011 10:10:03 -0700, Jim Thompson
>
What is that in ASCII?
Jamie
The op wanted a Monostable not a Time delay on.. Also, that circuit
won't function if you don't hold the RESET low long enough..
Maybe I am over looking something but It sure does not look like what
was requested. A monostable turns off when the Threshold is reached. A
time delayed one-shot/monostable.
Jamie
Bitrex
Sorry, should be -RC*log[Vcc/(3*(Vcc-0.6))].
Fred Bloggs
<jamie_ka1lpa_not_valid_after_ka1l...@charter.net> wrote:
> Bitrex wrote:
> > On 3/26/2011 1:10 PM, Jim Thompson wrote:
>
>
> >>> Thank you all!
> >>> I'll try Bitrex's solution, it's just what I need.
>
> >> What was his suggestion? The post didn't show up here for some reason
> >> :-(
>
> >> ...Jim Thompson
>
> > Here ya go:
>
> >http://i227.photobucket.com/albums/dd240/bitrex2007/555pulser.jpg
>
> > Negative going pulse at RESET gives a negative going one-shot at the
> > output, the "low time" is approximately RC*log[Vcc/(3*(Vcc-0.6))].
>
> The op wanted a Monostable not a Time delay on.. Also, that circuit
> won't function if you don't hold the RESET low long enough..
>
> Maybe I am over looking something but It sure does not look like what
> was requested. A monostable turns off when the Threshold is reached. A
> time delayed one-shot/monostable.
>
>
> - Show quoted text -
That is a monostable - the only potential problem I see is there
should be a 10K, or so, to GND from the THRESH input, otherwise it
will work great.
Bitrex
The reset goes low, and then the output goes low for a time determined
by an RC network. So it's the opposite of the standard 555 monostable,
where the trigger input is pulsed low and the output goes high for a
time determined by an RC network. Sure, it won't work if the reset
isn't held low long enough, but I don't see why the reset input would
need the pulse to stay low any longer than the trigger would with the
ordinary monostable in the standard configuration.
The OP says it satisfies his requirements, so I'm not sure what the
problem is.
Bitrex
Good catch - that will keep the threshold from accidentally floating up
to a high level and messing things up. Hopefully the OP sees your
correction.
Jamie
Sure, when the Threshold is being used. What I see there, it's not
even connected.. So, it's not monostable at all.. Just a time on
delay.. On top of that, the Reset pulse must be shorter than the
mono cycle and the off duration long enough to fully discharge that cap!
problems, problems...
Jamie
Jon Kirwan
<bloggs.fred...@gmail.com> wrote:
>What is that in ASCII?
This:
>: ,-----------,
>: 0V-- |--+5
>: | |
>: | |
>: | |
>: ,--|TRIG DIS|----,
>: | | | |
>: | | | |
>: | | | |
>: ,---------|OUT THRS| \
>: | | | | / R1
>: | | | | \ 47k
>: | | | | /
>: +5 ,---------------|RST CV| |
>: | | | | | | |
>: | | | | '-----------' |
>: | | | D1 | |
>: | | +--|>|-+-------------------+
>: --- --- | 1N4148 |
>: - V2 - V1 | |
>: --- 5 --- \ --- C1
>: - - / R2 --- 4.7e-7
>: | | \ 10k |
>: | | / |
>: | | | |
>: +--0V | | |
>: | | | |
>: +-------+-----+--------------------------'
>: |
>: | V1=PULSE(12 0 0 1e-7 1e-7 1e-6 0 1)
>: | .tran 1
>: gnd
Jamie
Ok, so it's a inverted Monostable how ever, with what the OP stated
using the trigger input, one would assume that the cycle needed
completing even if the source that triggered the event goes off before
the sequence is complete.. sort of a pulse stretcher. Seeing that the
trigger input was being used, a low logic signal is obvious here and
the trigger input will maintain the cycle once operating.
The op stated 1 sec inverted pulse. That kind of tells me something.
Maybe edge triggering on the THRESHOLD of a common monostable with
the TRIGGER wired to the DISCHARGE and RC network would be better. But
then again, the op never really indicated the logic state that should
start the cycle. Using the TRIGGER input only assumes a logic 0, if the
op is aware of its internal operations (PNP). THRESHOLD being a (NPN).
The problem I have is, the timer can do so many things and if the
requested information supplied is brief, it leads to a lot of different
variations of what can happen and what will happen.. In other words,
more detailed information needs to be supplied in the questionnaire to
convey to the community clearly, so that a proper circuit can be
designed . I find that many overlook side effects if they don't get the
target design clear to start with.
Jamie
Fred Bloggs
The OP said "...but stays low for a second... ", so it /should be/
unlikely that the trigger is still applied during the timeout. It is
monostable in the strictest sense, assuming the RST trigger is lifted,
because the TRIG is tied to the timing capacitor heading towards 0V
and thus a threshold crossing of the TRIG input causing the output to
flip back H where it will remain indefinitely - the mono-stable state,
until retriggered via RST.
Fred Bloggs
> On Sat, 26 Mar 2011 17:05:34 -0700 (PDT), Fred Bloggs
>
>
> - Show quoted text -
OIC- thanks, the same thing-.
John Fields
---
Jon Kirwan posted the ASCIImatic, but in reality it's an LTspice
netlist.
If you don't have LTspice you can get it for free at:
http://www.linear.com/designtools/software/#LTspice
Copy the netlist, rename it *.asc, then save it to some convenient
location and open it with LTspice.
You'll see the schematic and you'll be able to run a simulation.
--
JF
John Fields
---
The OP stated precisely what he wanted:
Then bitrex came up with a clever implementation and a circuit
description and I posted an LTspice netlist, since he didn't, so
anyone could simulate the circuit.
Everyone but you seems to understand how it works, so instead of
whining about how everyone's at fault but you, why don't you just
study the circuit until you figure it out?
--
JF
Jon Kirwan
<jfi...@austininstruments.com> wrote:
><snip>
>Jon Kirwan posted the ASCIImatic, but in reality it's an LTspice
>netlist.
><snip>
Yes, and I just ran your .ASC file through a program I wrote
to create the ASCII, automatically pasting it to the
clipboard.
Jon
Jamie
here is the problem. Many are over looking side effects and problems
with that circuit.
No duration was not indicated here and yes, I did miss the part about
the low pulse being used on the trigger. Sorry I over looked that how
ever, it does not excuse the fact that this circuit has issues when the
input pulse duration is not indicated. If you look hard enough I think
you'll see the problem.
Think Edge triggering.. !
Jamie
Jamie
I started to write a ASC converter program for Ltspice and lost
interest. Doing this in delphi is a simple matter how ever, my approach
was to monitor the folder the project was being updated/saved in using
the windows Folder Change API calls. The clipboard feature would be nice
how ever, I have other things operating on the desktop while I am logged
in that uses that feature automatically and I think it would interfere
with it. I suppose I could finish it, it would make it simpler for me to
throw things on the group here instead of trying to explain myself. Must
be the reason why GUIs were invented ;)
Jamie
John Fields
---
Excellent!
--
JF
John Fields
---
Such as?
---
> No duration was not indicated here and yes, I did miss the part about
>the low pulse being used on the trigger. Sorry I over looked that how
>ever, it does not excuse the fact that this circuit has issues when the
>input pulse duration is not indicated. If you look hard enough I think
>you'll see the problem.
---
The only issue I see is the same one which the TRIGGER\ input has to
deal with, that being that the input pulse must not last as long as
the output pulse and, for RESET\ triggering, the input level must fall
to within 0.4V of ground, worst case.
---
> Think Edge triggering.. !
---
Edge triggering has nothing to do with it since the TRIGGER\ and
RESET\ inputs are both level sensitive.
--
JF
Jamie
If you say so, I guess I see things you don't.
Jamie
John Fields
<jamie_ka1lpa_not_v...@charter.net> wrote:
---
Delusions, I'd warrant, since you don't seem to want to discuss the
issues.
--
JF
Jamie
Correct, I don't harp on what you can't see. It's inadequate for
anything I would use. Did you ever stop and think what would happen if
the input pulse duty cycle exceeded the 1 sec output required? Did you
ever ask yourself that maybe the op wants it to pulse 1 sec regardless
if the input pulse was short or maybe held on for some longer period?
Using Edge triggering would solve all those problems but you don't
seem to understand that.. Or maybe you just assume a sloppy variable
length pulse on the output is just fine.. Hell, if that is the case, why
bother with a dame timer? Just stick a RC circuit in there.
Now that sounds about as ridiculous as you not seeing what I am trying
to point out.
Have a good day.
Jamie
John - KD5YI
Yes, you do. Like right now.
It's inadequate for
> anything I would use. Did you ever stop and think what would happen if
> the input pulse duty cycle exceeded the 1 sec output required? Did you
> ever ask yourself that maybe the op wants it to pulse 1 sec regardless
> if the input pulse was short or maybe held on for some longer period?
He already covered that, but you didn't notice or recognize the
significance of his response due to your lack of technical knowledge.
> Using Edge triggering would solve all those problems but you don't seem
> to understand that.. Or maybe you just assume a sloppy variable
> length pulse on the output is just fine.. Hell, if that is the case, why
> bother with a dame timer? Just stick a RC circuit in there.
So, you don't simulate circuits? If you did, you would see what it's all
about.
> Now that sounds about as ridiculous as you not seeing what I am trying
> to point out.
>
Ridiculous is what you are for attempting to argue with someone far
superior to you. Only a dummy does that.
> Have a good day.
I feel certain he will, and so will we all. Can't say the same for you.
>
> Jamie
Oh, yeah. Jamie. The embarrassment of the ham community. What a shame
you are.
Phil Hobbs
BTW at least in my newsreader (SeaMonkey), you can add .asc files as
attachments to the post, and have it appear as a clickable attachment
even on text NGs--on Windows, LTSpice comes right up. (Apologies to any
residual tin and pine folks, who probably see big steaming piles of HTML
when this happens.)
Cheers
Phil Hobbs
--
Dr Philip C D Hobbs
Principal
ElectroOptical Innovations
55 Orchard Rd
Briarcliff Manor NY 10510
845-480-2058
email: hobbs (atsign) electrooptical (period) net
http://electrooptical.net
Slater
>> the only potential problem I see is there
>> should be a 10K, or so, to GND from the THRESH input, otherwise it
>> will work great.
>
>Good catch - that will keep the threshold from accidentally floating up
>to a high level and messing things up. Hopefully the OP sees your
>correction.
Correction seen. Thank you all for your help!
Jamie
Ha Ha Ha,.
You should stay out of what you don't understand.
I would never use that flawed circuit, if I wanted a consistent
pulse response on the output. You see, you are like a lot of the
sheep around here that follow who you assume to be always correct. That
is only because you know no better.
I've used 555's/6 for so many different things over the years in
industrial functions where semi accurate response and reliable behavior
is required and I can tell you, that circuit would not be seen in
anything I would use other than maybe a toy for a kid.
The fact do you don't see this flaw, should tell you to stay out it,
it only makes to deteriorate your image even more. Lets not even talk
about Ham radio here, you are only talking about yourself when you
say "Embarrassment", that you are.
I don't care what you do here, you can follow these miss guided sheep
here all you want how ever, I take it very seriously when you think you
can judge me when you can barely crawl..
Maybe you should pay a visit to our site one day and we could show you
how to break down a 2Mev Irradiation Xlinking process machine. Yes, lets
break down the dyno, scan amplifiers, 350kWatt oscillator along with
its inner components, many of which have lots of my handy work in it and
yes, many 555's used through out in configurations you never thought
could happen.
Let me ask you this, do you really think they would allow me to do
this level of work on multi million dollar machines generating dangerous
emissions with in, if I didn't know what I was doing?
Sorry that you have to be a sap, I guess every organization must have
them.
Jamie
John - KD5YI
You must be a clone of Dimbulb.
Michael A. Terrell
They share a single brain cell.
--
You can't fix stupid. You can't even put a Band-Aid™ on it, because it's
Teflon coated.
John - KD5YI
Thanks, Michael. That makes sense.