CA3140 model. Again!

[Lostgallifreyan]

In what context did this model ever work in LTspice used as supplied? I can't
find one. I have no trouble with any other amp model I need to use, but in
all the realworld CA3140 situations I have emulated in LTspice, THIS model
fails, with an interesting variety of errors.

Now I am NOT interested in what spurious ways I might be gettign it WRONG,
I'll work that out in my own time withotu bothering anyone at all. Right now
I want to know if it EVER worled RIGHT. In complete context please. If I can
see proof that it works, I'll start to figure out why I can never use it.

(It's interesting to me that on the web at larghe, though this model has been
accepted gratefully many times, no-one has ever actually said whether they
managed to USE it or not.)




*$ model description: "awbca3140"
*a Device model created by analog_uprev for ca3140 on Thu Mar 1
18:48:14 IST 2001


..subckt awbca3140 1 36 15 20 12
*START OF DECK
* +IN -IN OUT +VSS -VSS
*NODE: 1 36 15 20 12
*------INPUT STAGE-------
VOSBAL 7 29 3.00000000E-03
EU1 8 1 20 12 0.0001
EU2 8 7 5 12 -1
RB1 12 10 1 TC= 1.991040E-03 (-1.244400E-04)
IB4 10 12 1.000000E-06
RB3 12 5 8743.17 TC= 1.60000000E-03 (0.00000000E+00)
IB3 12 5 5.718750E-07
G1 12 1 10 12 1.025000E-05
G2 12 36 10 12 9.750000E-06
RDM 36 29 1.500000E+12
RCM 31 13 1.500000E+12
CDM 36 29 4.000000E-12
G5 31 13 36 31 6.66667E-13
G6 31 13 1 31 6.66667E-13
*------INTERMEDIATE STAGE-------
GDM 31 16 29 36 1
GCM 31 16 13 31 -1.58113883E-05
R1 31 16 3.16358380E+02
C1 31 16 6.45457E-11
VCP 23 31 100
VCM 24 31 -100
DD1 16 23 MD2
..MODEL MD2 D XTI=1.000000P
* SPECTRE: + IMAX=1000
DD2 24 16 MD2
G3 31 6 16 31 -1.07249255E-06
R2 31 6 100000
C2 11 6 1.2E-11
RP1 31 20 3750
RP2 31 12 3750
*------OUTPUT STAGE-------
G4 31 11 6 31 -5.10867719E+01
ROUT 31 11 60
DD3 11 9 MD3
..MODEL MD3 D IS=10.0F XTI=1.0P N= 3.612647E-01
* SPECTRE: + IMAX=1000
DD4 9 11 MD4
..MODEL MD4 D IS=10.0F XTI=1.0P N= 8.028126E-01
* SPECTRE: + IMAX=1000
EU6 9 31 2 31 1
RO1 11 26 20
FF1 31 28 VFF1 1
VFF1 26 2 0.0
FF2 31 20 VFF2 -1
VFF2 33 31 0.0
FF3 12 31 VFF3 -1
VFF3 31 27 0.0
DD8 27 28 MID
DD7 28 33 MID
..MODEL MID D XTI=1.000000F N=1 IS=10.000000F
* SPECTRE: + IMAX=1000
VP 20 22 -29.2613
VM 21 12 -29.3113
DD5 25 22 MID
DD6 21 17 MID
VP1 20 30 2.7501
VM1 32 12 .859456
DD9 2 30 MD9
DD10 32 15 MD9
..MODEL MD9 D XTI=1.000000F N=1 IS=10.000000F
* SPECTRE: + IMAX=1000
HH1 25 2 POLY(2) VIC2 VIC1 0 1960 0 1540 0 0 0 0 0 0
HH2 2 17 POLY(2) VIC3 VIC1 0 -1960 0 -1540 0 0 0 0 0 0
VIC1 37 3 0.0
VIC2 2 14 0.0
VIC3 14 15 0.0
VPP 37 0 1
RPP 3 0 100.0K
RO3 15 20 200.0MEG
RO2 15 12 200.0MEG
..ends
*$ end model description: "awbca3140"
*
*
*$ model description: "awbca3140a"
*a Device model created by analog_uprev for ca3140a on Thu Mar 1
18:48:14 IST 2001


..subckt awbca3140a 1 36 15 20 12
*START OF DECK
* +IN -IN OUT +VSS -VSS
*NODE: 1 36 15 20 12
*------INPUT STAGE-------
VOSBAL 7 29 3.00000000E-03
EU1 8 1 20 12 0.0001
EU2 8 7 5 12 -1
RB1 12 10 1 TC= 1.991040E-03 (-1.244400E-04)
IB4 10 12 1.000000E-06
RB3 12 5 8743.17 TC= 3.00000000E-03 (0.00000000E+00)
IB3 12 5 2.287500E-07
G1 12 1 10 12 1.025000E-05
G2 12 36 10 12 9.750000E-06
RDM 36 29 1.500000E+12
RCM 31 13 1.500000E+12
CDM 36 29 4.000000E-12
G5 31 13 36 31 6.66667E-13
G6 31 13 1 31 6.66667E-13
*------INTERMEDIATE STAGE-------
GDM 31 16 29 36 1
GCM 31 16 13 31 -1.58113883E-05
R1 31 16 3.16358380E+02
C1 31 16 6.45457E-11
VCP 23 31 100
VCM 24 31 -100
DD1 16 23 MD2
..MODEL MD2 D XTI=1.000000P
* SPECTRE: + IMAX=1000
DD2 24 16 MD2
G3 31 6 16 31 -1.07249255E-06
R2 31 6 100000
C2 11 6 1.2E-11
RP1 31 20 3750
RP2 31 12 3750
*------OUTPUT STAGE-------
G4 31 11 6 31 -5.10867719E+01
ROUT 31 11 60
DD3 11 9 MD3
..MODEL MD3 D IS=10.0F XTI=1.0P N= 3.612647E-01
* SPECTRE: + IMAX=1000
DD4 9 11 MD4
..MODEL MD4 D IS=10.0F XTI=1.0P N= 8.028126E-01
* SPECTRE: + IMAX=1000
EU6 9 31 2 31 1
RO1 11 26 20
FF1 31 28 VFF1 1
VFF1 26 2 0.0
FF2 31 20 VFF2 -1
VFF2 33 31 0.0
FF3 12 31 VFF3 -1
VFF3 31 27 0.0
DD8 27 28 MID
DD7 28 33 MID
..MODEL MID D XTI=1.000000F N=1 IS=10.000000F
* SPECTRE: + IMAX=1000
VP 20 22 -29.2613
VM 21 12 -29.3113
DD5 25 22 MID
DD6 21 17 MID
VP1 20 30 2.7501
VM1 32 12 .859456
DD9 2 30 MD9
DD10 32 15 MD9
..MODEL MD9 D XTI=1.000000F N=1 IS=10.000000F
* SPECTRE: + IMAX=1000
HH1 25 2 POLY(2) VIC2 VIC1 0 1960 0 1540 0 0 0 0 0 0
HH2 2 17 POLY(2) VIC3 VIC1 0 -1960 0 -1540 0 0 0 0 0 0
VIC1 37 3 0.0
VIC2 2 14 0.0
VIC3 14 15 0.0
VPP 37 0 1
RPP 3 0 100.0K
RO3 15 20 200.0MEG
RO2 15 12 200.0MEG
..ends
*$ end model description: "awbca3140a"

[Lostgallifreyan]

Lostgallifreyan <no-...@nowhere.net> wrote in
news:Xns9FE1BE34E7B...@216.196.109.145:

> In what context did this model ever work in LTspice used as supplied? I
> can't find one. I have no trouble with any other amp model I need to
> use, but in all the realworld CA3140 situations I have emulated in
> LTspice, THIS model fails, with an interesting variety of errors.
>

> Now I am NOT interested in what spurious ways I might be getting it
> WRONG, I'll work that out in my own time without bothering anyone at
> all. Right now I want to know if it EVER worked RIGHT. In complete

> context please. If I can see proof that it works, I'll start to figure

> out why I could never use it.
>
> (It's interesting to me that on the web at large, though this model has
> been given and accepted gratefully many times, no-one has ever actually

> said whether they managed to USE it or not.)
>

First post had broken formatting of the model (web page copy), here's the
copy I originally found and used. (Also, crossposted to s.e.d this time, and
corrected some typos above..) Maybe this model is still borked in copying, or
maybe it has fundamental flaws. Please help me find out...

*$ model description: "awbca3140"
*a Device model created by analog_uprev for ca3140 on Thu Mar 1 18:48:14 IST
2001

* CONNECTIONS: NON-INVERTING INPUT
* | INVERTING INPUT
* | | POSITIVE POWER SUPPLY
* | | | NEGATIVE POWER SUPPLY
* | | | | OUTPUT
* | | | | |

.subckt CA3140 1 36 15 20 12

*START OF DECK
* +IN -IN OUT +VSS -VSS
*NODE: 1 36 15 20 12
*------INPUT STAGE-------
VOSBAL 7 29 3.00000000E-03
EU1 8 1 20 12 0.0001
EU2 8 7 5 12 -1
RB1 12 10 1 TC= 1.991040E-03 (-1.244400E-04)
IB4 10 12 1.000000E-06
RB3 12 5 8743.17 TC= 1.60000000E-03 (0.00000000E+00)

*IB3 for CA3140, and CA3140A
IB3 12 5 5.718750E-07
*IB3 12 5 2.287500E-07

G1 12 1 10 12 1.025000E-05
G2 12 36 10 12 9.750000E-06
RDM 36 29 1.500000E+12
RCM 31 13 1.500000E+12
CDM 36 29 4.000000E-12
G5 31 13 36 31 6.66667E-13
G6 31 13 1 31 6.66667E-13
*------INTERMEDIATE STAGE-------
GDM 31 16 29 36 1
GCM 31 16 13 31 -1.58113883E-05
R1 31 16 3.16358380E+02
C1 31 16 6.45457E-11
VCP 23 31 100
VCM 24 31 -100
DD1 16 23 MD2

[Lostgallifreyan]

Lostgallifreyan <no-...@nowhere.net> wrote in
news:Xns9FE1C0DDF59...@216.196.109.145:

> *a Device model created by analog_uprev for ca3140 on Thu Mar 1 18:48:14
> IST 2001
>

Note that line wrapped; all others are intact in that post.

[Lostgallifreyan]

Lostgallifreyan <no-...@nowhere.net> wrote in
news:Xns9FE1C0DDF59...@216.196.109.145:

Please help. I'm sure plenty of people here know Spice, and use the CA3240,
and would have no trouble trying this subcircuit (below) as a quick
substitution just to see if it works.

[Jim Thompson]

On Sat, 21 Jan 2012 12:57:39 -0600, Lostgallifreyan
<no-...@nowhere.net> wrote:

[snip]

The description pin order does not match with the

+IN -IN OUT +VSS -VSS order

* CONNECTIONS: NON-INVERTING INPUT
* | INVERTING INPUT
* | | POSITIVE POWER SUPPLY
* | | | NEGATIVE POWER SUPPLY
* | | | | OUTPUT
* | | | | |
.subckt CA3140 1 36 15 20 12
*START OF DECK
* +IN -IN OUT +VSS -VSS
*NODE: 1 36 15 20 12

[snip]

...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

[Lostgallifreyan]

Jim Thompson <To-Email-Use-Th...@On-My-Web-Site.com> wrote in news:abtqh7pt15qalknp9...@4ax.com:

> The description pin order does not match with the
>
> +IN -IN OUT +VSS -VSS order
>
> * CONNECTIONS: NON-INVERTING INPUT
> * | INVERTING INPUT
> * | | POSITIVE POWER SUPPLY
> * | | | NEGATIVE POWER SUPPLY
> * | | | | OUTPUT
> * | | | | |
> .subckt CA3140 1 36 15 20 12
> *START OF DECK
> * +IN -IN OUT +VSS -VSS
> *NODE: 1 36 15 20 12
>

Amazing. Thanks. :) I never noticed that because I assumed the post I found it in
was right because all the other amp models use the first order stated in comments,
not the second (so I didn't notice the conflict at all..)

I corrected that and saw traces graphed, at last... I still get some errors though,
for example: (in LTspice)
Analysis: Time step too small: time = 0.00138, timestep = 1.25001e-018: trouble with node "n010"

Things like this are why I didn't notice the obvious error, I was confronted with
many more subtle ones like this one which persist, there really does seem to be a
flaw in the model even after the pin correction.

Node n010 in my circuit is the noninverting pin on a differential amp, with 3K3 in,
and 680R to ground, nothing unusual there, and exactly what LT1215 wants for good
fast and accurate performance. No other amp model I tried has trouble with it, just
this one...

I tried changing the resistors to ten times the low values LT1215 likes, to something
more usual for CA3240, and removing the compensation caps that LT1215 needs and the
CA3240 doesn't, and I get a different error:
Analysis: Time step too small: time = 0.001368, timestep = 1.25001e-018: trouble with U2:mid-instance d:u2:d6

Sorry if this is not helpful info, I'm doing the best I can short of posting a huge
post with the entire context, and even from this is should show that there is
something wrong with model internally, beyond the original pin order error, and
where one major flaw exists, there may well be others too. Please can you tell me
if this model is in any way redeemable. The CA3240 is a fine and venerable old IC
and I'd really like to see a good working model for it.

[Lostgallifreyan]

Looking at the Harris and Intersil datasheets for CA3140 I see an identical
schematic. I don't know much about Spice notations in subcircuits, but when I
did this in the past for some other amp (possibly LF412 or more likely LM317)
I saw a close match with transistor and resistor numbers that helped me to
understand that I was at least looking at a real model of a real device. :)

In this case, things are not so clear! To start with, both input pins should
connect only to an FET gate and a diode, yet the model appears to show at
least 4 internal connections to the inverting input pin. Is it a fine model
of exacting conditions beyond anythign the datasheet sdescribes, or is it
just a broken mess? I really have no way to know without help, because no
matter what I do I never see it working so I can't learn from breaking it.

[Jim Thompson]

On Mon, 23 Jan 2012 09:52:36 -0600, Lostgallifreyan
<no-...@nowhere.net> wrote:

>Jim Thompson <To-Email-Use-Th...@On-My-Web-Site.com> wrote in news:abtqh7pt15qalknp9...@4ax.com:
>
>> The description pin order does not match with the
>>
>> +IN -IN OUT +VSS -VSS order
>>
>> * CONNECTIONS: NON-INVERTING INPUT
>> * | INVERTING INPUT
>> * | | POSITIVE POWER SUPPLY
>> * | | | NEGATIVE POWER SUPPLY
>> * | | | | OUTPUT
>> * | | | | |
>> .subckt CA3140 1 36 15 20 12
>> *START OF DECK
>> * +IN -IN OUT +VSS -VSS
>> *NODE: 1 36 15 20 12
>>
>
>Amazing. Thanks. :) I never noticed that because I assumed the post I found it in
>was right because all the other amp models use the first order stated in comments,
>not the second (so I didn't notice the conflict at all..)

I caught it because I often change subcircuit node order to match my
home-made symbols.

>
>I corrected that and saw traces graphed, at last... I still get some errors though,
>for example: (in LTspice)
>Analysis: Time step too small: time = 0.00138, timestep = 1.25001e-018: trouble with node "n010"
>
>Things like this are why I didn't notice the obvious error, I was confronted with
>many more subtle ones like this one which persist, there really does seem to be a
>flaw in the model even after the pin correction.
>
>Node n010 in my circuit is the noninverting pin on a differential amp, with 3K3 in,
>and 680R to ground, nothing unusual there, and exactly what LT1215 wants for good
>fast and accurate performance. No other amp model I tried has trouble with it, just
>this one...
>
>I tried changing the resistors to ten times the low values LT1215 likes, to something
>more usual for CA3240, and removing the compensation caps that LT1215 needs and the
>CA3240 doesn't, and I get a different error:
>Analysis: Time step too small: time = 0.001368, timestep = 1.25001e-018: trouble with U2:mid-instance d:u2:d6
>
>Sorry if this is not helpful info, I'm doing the best I can short of posting a huge
>post with the entire context, and even from this is should show that there is
>something wrong with model internally, beyond the original pin order error, and
>where one major flaw exists, there may well be others too. Please can you tell me
>if this model is in any way redeemable. The CA3240 is a fine and venerable old IC
>and I'd really like to see a good working model for it.

Back up to some simple circuit configuration and make sure that it
behaves as an OpAmp... verifying there isn't some other node out of
proper order.

I'm not familiar with that CA3140 model, but it seems to have a lot of
behavioral components, so add some capacitance to slow your external
nodes, then see if it converges.

[Jim Thompson]

On Mon, 23 Jan 2012 06:22:25 -0600, Lostgallifreyan
<no-...@nowhere.net> wrote:

>Lostgallifreyan <no-...@nowhere.net> wrote in
>news:Xns9FE1C0DDF59...@216.196.109.145:
>

>Please help. I'm sure plenty of people here know Spice, and use the CA3140,

>and would have no trouble trying this subcircuit (below) as a quick
>substitution just to see if it works.
>

[snip]

Further perusing that subcircuit, it seems I was the original poster
of that netlist, having found it in some Analog Workbench materials.

But I've never used it myself.

Looking it over... it's crap of the finest level :-)

Behavioral modeling to an extreme.

(Though that "Dynamic Current Sink" looks like a disaster waiting to
happen.)

Amusingly the schematic bears a strong resemblance to my Master's
Thesis of 1968, except I used JFET's, the only kind I could make back
then :-)

I'll see if I can't write a better subcircuit.

[Lostgallifreyan]

Jim Thompson <To-Email-Use-Th...@On-My-Web-Site.com> wrote in

news:a55rh7tmrjnmlfoam...@4ax.com:

> Back up to some simple circuit configuration and make sure that it
> behaves as an OpAmp... verifying there isn't some other node out of
> proper order.
>
> I'm not familiar with that CA3140 model, but it seems to have a lot of
> behavioral components, so add some capacitance to slow your external
> nodes, then see if it converges.
>

I don't think it does. :) Try this, a simple voltage follower, the kind often
used to generate a split rail from a single supply. I used 10K resistors to
halve a 15V single-rail supply, and to add some capacitance to slow the
transition on the +input I added a 10湩 cap across the ground-side resistor.

If I use an LF412 model I get the exact result expected, as with LT1215.
If I omit the 'startup' part of a .tran directive I see the 300 ms or so of
cap charging curve omitted from the graph, as expected. In either case with
either model, the output is a clean 7.5V.

If I do this with the CA3140 model, it works if the startup bit is added, but
if not, it oscillates at around 7.5V. The datasheet suggests a 3K9 resistor
for feedback instead of the direct link used for voltage followers, but if I
add that the output, while not oscillating, is only 2V! I know that a REAL
CA3140 doesn't behave this way as a voltage follower because I've done it.

it gets weirder... Keeping the single 15VDC supply, add a new 5V supply to
feed the 10K+10K divider. Output should be 2.5V, with or without the cap
charge curve depending on use (or not) of 'startup' in the .tran directive.
It isn't. With 'startup' the output is a millivolt below 15V (that amp cannot
swing that far!), and there is no sign of the cap charge curve at the start.
Without 'startup, it oscillates at about 125 KHz between 45.5 kilovolts and
46.1 kilovolts!!!!!!! The only word that I can use to describe this without
waxing explosively lyrical, is 'rediculous'.

[Lostgallifreyan]

Jim Thompson <To-Email-Use-Th...@On-My-Web-Site.com> wrote in

news:689rh79n8b4qn03kb...@4ax.com:

> Further perusing that subcircuit, it seems I was the original poster
> of that netlist, having found it in some Analog Workbench materials.
>
> But I've never used it myself.
>
> Looking it over... it's crap of the finest level :-)
>
> Behavioral modeling to an extreme.
>
> (Though that "Dynamic Current Sink" looks like a disaster waiting to
> happen.)
>

Well, thanks for looking at it seriously now. Better late than never. I knew
it couldn't just be me it did strange things to. What amazes me that in TEN
YEARS no-one else seems to have noticed and posted about it anywhere. It's
all over the net now, I'd have thought someone might have mentioned it, but
no...

> Amusingly the schematic bears a strong resemblance to my Master's
> Thesis of 1968, except I used JFET's, the only kind I could make back
> then :-)
>
> I'll see if I can't write a better subcircuit.
>

That will be awesome. I think all who love the CA3140 will welcome it. :) See
my other post, it shows some very strange stuff...

[Lostgallifreyan]

Jim Thompson <To-Email-Use-Th...@On-My-Web-Site.com> wrote in
news:689rh79n8b4qn03kb...@4ax.com:

> I'll see if I can't write a better subcircuit.
>

Here's something I can do that may help... It's as exact a rendering of the
CA3140 schematic as I can make from the Intersil datasheet. Resistors have
correct values, and numbering of all parts is exact (though the MOSFETS get
an M where bipolars get a Q). I have repeatedly double-checked the wiring so
the nodes should be right (though arbitrarily numbered in the netlist). I
made (far simpler) working subcircuits for SPST and SPDT switches yesterday
(things strangely lacking from LTspice as supplied!) based on netlists, and
applied my methods to this one, below, so it should be intact. I don't know
nearly enough to get the modelling right for the CA3140 diodes, bipolar and
FET transistors, and what appear to be Schottky diodes, let alone add
anything else vital like temperature related behaviour, but this starting
framework might save you some work if you're willing to add the vital
details. It likely also needs a reduction to 5 pins from 8 to fit a standard
op-amp model.

*Intersil CA3140, basic model drafted from datasheet.
* 8, Strb -------------------------|
* 7, V+ -----------------------| |
* 6, Out --------------------| | |
* 5, null -----------------| | | |
* 4, Gnd --------------| | | | |
* 3, +In -----------| | | | | |
* 2, -In --------| | | | | | |
* 1, null -----| | | | | | | |
* | | | | | | | |
.SUBCKT CA3140 31 21 23 15 30 16 1 12
D1 N001 N002 Diode
Q1 N005 N002 N001 0 PNP
Q2 N007 N002 N001 0 PNP
Q3 N006 N002 N001 0 PNP
Q4 N012 N005 N006 0 PNP
Q5 N024 N005 N007 0 PNP
Q6 N011 N005 N002 0 PNP
Q7 N005 N011 N017 0 NPN
R1 N017 N015 8K
M8 N020 N015 N011 N011 PMOS
D2 N020 N015 Diode
D3 N022 N021 Schottky
D4 N022 N023 Schottky
D5 N022 N024 Schottky
M9 N025 N021 N024 N024 PMOS
M10 N026 N023 N024 N024 PMOS
R2 N025 N029 500R
R3 N026 N027 500R
Q11 N029 N025 N030 0 NPN
Q12 N027 N025 N031 0 NPN
R4 N030 N015 500R
R5 N031 N015 500R
Q13 N012 N027 N015 0 NPN
C1 N027 N012 12pF
Q14 N018 N020 N032 0 NPN
Q15 N016 N020 N015 0 NPN
Q16 N016 N028 N015 0 NPN
D6 N028 N033 Diode
R6 N032 N015 50R
R7 N033 N015 30R
Q17 N001 N012 N018 0 NPN
R8 N018 N019 1K
Q18 N013 N019 N016 0 NPN
Q19 N006 N009 N013 0 NPN
Q20 N001 N003 N008 0 NPN
R9 N004 N010 50R
R10 N009 N010 1K
R11 N010 N013 20R
R12 N008 N014 12K
R13 N001 N003 5K
R14 P001 N015 20K
M21 N028 N016 N014 N014 PMOS
D7 N001 N004 Diode
D8 P001 N003 Schottky
*
*MODELS NEEDED FOR CA3140 INNARDS
.model Diode D
.model Schottky D
.lib E:\EDITORS\LTSPICE\lib\cmp\standard.dio
.model NPN NPN
.model PNP PNP
.lib E:\EDITORS\LTSPICE\lib\cmp\standard.bjt
.model NMOS NMOS
.model PMOS PMOS
.lib E:\EDITORS\LTSPICE\lib\cmp\standard.mos
.ends

[Jim Thompson]

Wow! That's extraordinarily helpful. Now all I have to do is search
my libraries for appropriate models. (I believe the diodes you call
Schottky are actually zeners... see D8 for instance... it's reverse
biased at all times.)

[Lostgallifreyan]

Jim Thompson <To-Email-Use-Th...@On-My-Web-Site.com> wrote in

news:jeprh7l78plbm57td...@4ax.com:

> Wow! That's extraordinarily helpful. Now all I have to do is search
> my libraries for appropriate models. (I believe the diodes you call
> Schottky are actually zeners... see D8 for instance... it's reverse
> biased at all times.)
>

Now I feel better. :) I understand a need to do what I can for myself. I just
wish I'd known that makign a SUBCKT from a netlist was this easy, just takes
time and care. But the real core detail is beyond me, this is where I really
do need help.

I'll see if I can figure out the reduction needed for the 5-pin amp model but
there seems to be a conflict of interest because some might like that offset
network modelled in full. Working out what to include was easy, workign out
what can safely be omitted might be more than I should try to do. This model
needs to help all those who encountered that other one. :)

[Lostgallifreyan]

Jim Thompson <To-Email-Use-Th...@On-My-Web-Site.com> wrote in

news:jeprh7l78plbm57td...@4ax.com:

> I believe the diodes you call
> Schottky are actually zeners... see D8 for instance... it's reverse
> biased at all times.)
>

Ooops. :) So true, I don't know why I did that, my last circuit had enough
zeners. I think I saw the Schottky symbol in a moment of uncertainty. Also,
no zener voltages are specified, so that's another detail I don't know enough
to solve here.

[Lostgallifreyan]

Jim Thompson <To-Email-Use-Th...@On-My-Web-Site.com> wrote in

news:jeprh7l78plbm57td...@4ax.com:

> Now all I have to do is search
> my libraries for appropriate models.

I tried something of my own, so far with no luck...
Googling for 'PMOS Bipolar process', and 'BiMOS Operational Amplifier',
hoping to find some IC that also had a good working Spice subckt that I could
raid models from. I learned that a CA3260 exists, but could not find a model
for it. NTE7144 may be another source of appropriate models IF there's a
subckt for it, but again, I can't find one. I'm fairly sure I don't know
enough to decide if it's usable even if I do.

Incidentally, that old CA3140 model appears to have no transistor models, and
a very wrong diode model count. I'm no judge of these things, but when I look
at it I can imagine how Mulder or Scully feel when confronted with a human
form that has no clearly discernable anatomy.

[Lostgallifreyan]

I found this:
http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=16322

...but I have no way to get a look at it.

[Jim Thompson]

I do all my searches -IEEE :-)

They're invariably worthless anyway.

[Lostgallifreyan]

Jim Thompson <To-Email-Use-Th...@On-My-Web-Site.com> wrote in news:smhth75nfahtlc3hf...@4ax.com:

>>I found this:
>>http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=16322
>>
>>...but I have no way to get a look at it.
>
> I do all my searches -IEEE :-)
>
> They're invariably worthless anyway.
>

Ok :) I figure that if they need to hide them that much,
maybe they are like the Emperor's New Clothes, and they
don't want too many people to notice.

How about these?
http://www.intusoft.com/nlpdf/nl30.pdf
(More than halfway through file, model of a Phillips BiCMOS bjt).
http://espice.ugr.es/espice/src/modelos_subckt/spice_complete/ABTMBN.LIB
Related to the ABT BiCMOS mentioned above, whole sets of models. :) Any good?
(That LIB file also appears to directly reference the above file...)

[Jim Thompson]

I found some high-voltage MOS models dating back to the dark ages, and
am now trying to remember how they work ;-) (They're subcircuits that
include the parasitics found in BiCMOS.)

[Lostgallifreyan]

Jim Thompson <To-Email-Use-Th...@On-My-Web-Site.com> wrote in

news:2eoth7ph79r380a7p...@4ax.com:

> I found some high-voltage MOS models dating back to the dark ages, and
> am now trying to remember how they work ;-) (They're subcircuits that
> include the parasitics found in BiCMOS.)
>

Sounds good. Sort of what I was looking for, but I was never there, and
might not know if if I saw it. I guess like good records of anything, it
helps to have saved stuff from the time and place of occurence. If Google is
anything to go by, BiMOS wasn't used all that much. Weird, given how good it
can be.

[Jim Thompson]

Google doesn't know $#^*

BiCMOS is wonderful for high-end analog/mixed-signal systems. I've
designed numerous chips on XFAB and Polarfab BiCMOS processes. BiCMOS
is quite a bit more expensive, but well worth it given the performance
gains.

[Lostgallifreyan]

Jim Thompson <To-Email-Use-Th...@On-My-Web-Site.com> wrote in

news:ospth79223jbsmjv1...@4ax.com:

> Google doesn't know $#^*
>

Well, that's kind of my point. >:) I'm citing their best output to encourage
you to come up with the good stuff. :)

I think analog accuracy has been underrated over many years. Never mind that
it doesn't get to the last bit-worth of accuracy, the SPEED of calculating
complex forms is second till none, at least until someone does it with
quantum computing. So much time might have been saved by analog cumputers,
leaving digital ones to refine the output.

[Jim Thompson]

>quantum computing. So much time might have been saved by analog computers,

>leaving digital ones to refine the output.

I disagree (slightly)... It's hard to beat a uP for decision making
and using its outputs to control analog functions.

It's a rare chip I've designed in recent years that doesn't either
have an embedded uP in it (designed by or purchased IP embedded by a
subcontractor buddy of mine), or is controlled by an external uP. We
are, after all, living in a system on a chip (SOC) world.

[Jim Thompson]

On Mon, 23 Jan 2012 06:22:25 -0600, Lostgallifreyan
<no-...@nowhere.net> wrote:

>Lostgallifreyan <no-...@nowhere.net> wrote in
>news:Xns9FE1C0DDF59...@216.196.109.145:
>

[snip]

Ran your schematic... behavior is extraordinarily weird, output hangs
about 0.7V below ground when powered from +/-12V

Please recheck your netlist. Thanks!

[Lostgallifreyan]

Jim Thompson <To-Email-Use-Th...@On-My-Web-Site.com> wrote in

news:2bvth7l6oknup47dn...@4ax.com:

> Ran your schematic... behavior is extraordinarily weird, output hangs
> about 0.7V below ground when powered from +/-12V
>
> Please recheck your netlist. Thanks!
>

I checked it, it's definitely wired ok, transistors are of correct type
and orientation, and the pins are correctly numbered according to node. I
can't model its parts so didn't check by running it.

I can think of a few things that might matter. I didn't assign a ground, so
there was no node 0, it was node 15, and maybe there has to be a node 0 in
all subcircuits. Also, I used European resistor value methods like 500R,
which LTspice can be told not to accept. Also, as LTspice uses M for MOSFET
and Q for bipolar, and I kept the numbering from the datasheet, the first M
value is 8, not 1, and there is no Q8. Maybe spice programs don't like
discontinuities like that.

Apart from that last point, which I left as I did it, so the numbers match
up, I changed the other details I mentioned for more likely compatibility,
and also reordered parts by stage as they appear in the datasheet schematic,
which should help with verifying their nodes are right.

*Intersil CA3140, basic model drafted from datasheet.
* 8, Strb -------------------------|
* 7, V+ -----------------------| |
* 6, Out --------------------| | |
* 5, null -----------------| | | |
* 4, Gnd --------------| | | | |
* 3, +In -----------| | | | | |
* 2, -In --------| | | | | | |
* 1, null -----| | | | | | | |
* | | | | | | | |

.SUBCKT CA3140 30 20 22 0 29 15 1 12
* BIAS CIRCUIT

D1 N001 N002 Diode
Q1 N005 N002 N001 0 PNP

Q6 N011 N005 N002 0 PNP

Q7 N005 N011 N016 0 NPN
R1 N016 0 8000
M8 N019 0 N011 N011 PMOS
D2 N019 0 Diode
* INPUT STAGE

Q2 N007 N002 N001 0 PNP

Q5 N023 N005 N007 0 PNP
D3 N021 N020 Zener
D4 N021 N022 Zener
D5 N021 N023 Zener
M9 N024 N020 N023 N023 PMOS
M10 N025 N022 N023 N023 PMOS
R2 N024 N028 500
R3 N025 N026 500
Q11 N028 N024 N029 0 NPN
Q12 N026 N024 N030 0 NPN
R4 N029 0 500
R5 N030 0 500
* SECOND STAGE

Q3 N006 N002 N001 0 PNP
Q4 N012 N005 N006 0 PNP

Q13 N012 N026 0 0 NPN
C1 N026 N012 12E-12
* OUTPUT STAGE
Q17 N001 N012 N017 0 NPN
R8 N017 N018 1000
Q18 N013 N018 N015 0 NPN
D7 N001 N004 Diode
R9 N004 N010 50

Q19 N006 N009 N013 0 NPN

R10 N009 N010 1000
R11 N010 N013 20
Q14 N017 N019 N031 0 NPN
R6 N031 0 50
Q15 N015 N019 0 0 NPN
* DYNAMIC CURRENT SINK
Q16 N015 N027 0 0 NPN
D6 N027 N032 Diode
R7 N032 0 30

Q20 N001 N003 N008 0 NPN

R12 N008 N014 12000
R13 N001 N003 5000
D8 P001 N003 Zener
R14 P001 0 20000
M21 N027 N015 N014 N014 PMOS

*
*MODELS NEEDED FOR CA3140 INNARDS
.model Diode D

.model Zener D

.lib E:\EDITORS\LTSPICE\lib\cmp\standard.dio
.model NPN NPN
.model PNP PNP
.lib E:\EDITORS\LTSPICE\lib\cmp\standard.bjt
.model NMOS NMOS
.model PMOS PMOS
.lib E:\EDITORS\LTSPICE\lib\cmp\standard.mos

.ENDS

[Lostgallifreyan]

Jim Thompson <To-Email-Use-Th...@On-My-Web-Site.com> wrote in

news:rnrth7hkj2icujq1b...@4ax.com:

>>I think analog accuracy has been underrated over many years. Never mind
>>that it doesn't get to the last bit-worth of accuracy, the SPEED of
>>calculating complex forms is second till none, at least until someone
>>does it with quantum computing. So much time might have been saved by
>>analog computers, leaving digital ones to refine the output.
>
> I disagree (slightly)... It's hard to beat a uP for decision making
> and using its outputs to control analog functions.
>

That's true. I guess it's the other perspective in a duality, the one I
didn't take. A good hybrid is likely the best of all possibles, so a really
effective computer might combine all methods in full intercommunication
between methods.

So the program can decide what to try, try analog where fast and appropriate,
then return to digital for accurate computations entirely ignoring methods
that analog methods quickly showed to be unacceptable. I'd like to see what
happens when quantum methods are added to a system like that. :) Might be a
whole new kind of brain.

[Lostgallifreyan]

> Jim Thompson <To-Email-Use-Th...@On-My-Web-Site.com> wrote in
> news:2bvth7l6oknup47dn...@4ax.com:
>
>> Ran your schematic... behavior is extraordinarily weird, output hangs
>> about 0.7V below ground when powered from +/-12V
>>
>> Please recheck your netlist. Thanks!
>>
>

I guess you did reorder the pin count and quantity. :) (And possibly reversed
+in and -In in doing so by accident?) I used all 8, but I imagine my new
SUBCKT can be made standard for 5 pins +In -In V+ V- Out by doing this:
.SUBCKT CA3140 22 20 1 0 15
(Leaving the other 3 as no external connection).

[Jim Thompson]

On Tue, 24 Jan 2012 15:01:39 -0600, Lostgallifreyan
<no-...@nowhere.net> wrote:

>Jim Thompson <To-Email-Use-Th...@On-My-Web-Site.com> wrote in
>news:2bvth7l6oknup47dn...@4ax.com:
>
>> Ran your schematic... behavior is extraordinarily weird, output hangs
>> about 0.7V below ground when powered from +/-12V
>>
>> Please recheck your netlist. Thanks!
>>
>
>I checked it, it's definitely wired ok, transistors are of correct type
>and orientation, and the pins are correctly numbered according to node. I
>can't model its parts so didn't check by running it.
>
>I can think of a few things that might matter. I didn't assign a ground, so
>there was no node 0, it was node 15, and maybe there has to be a node 0 in
>all subcircuits.

No. You don't need a Node Zero inside a subcircuit.

>Also, I used European resistor value methods like 500R,

Fixed right away.

>which LTspice can be told not to accept. Also, as LTspice uses M for MOSFET
>and Q for bipolar, and I kept the numbering from the datasheet, the first M
>value is 8, not 1, and there is no Q8. Maybe spice programs don't like
>discontinuities like that.

Not a problem in PSpice. I did have to fix your headers, "15" =>
"N015", etc, otherwise everything "floats" :-)

[snip]

It could be simply an issue with guessing the MOSFET parameters, for
example M(Q)8... probably a long channel device to act like a variable
resistor... how long, who knows? Plus that output current "sink"
structure is plain-ass somebody's wet dream ;-)

But the data sheet offers some clues, the strobe current is 220uA, so
that's the current in Q3/Q4.

Given the weirdness of that output stage I'm becoming inclined to
model it as a mix of behavioral blocks plus NPN's to match the data
sheet.

The data sheet indicates to me that it's not the world's gift to OpAmp
performance standards... why do you want to use it?

I invented that Q11, Q12, Q13 "turnaround"... see Tom Frederiksen's
book, "Intuitive IC Op Amps", page 14. The schematic in the data
sheet is NOT balanced... I suspect a typo... maybe there are more.

[Jim Thompson]

PSpice _is_ a mixed-signal simulator. I can throw in digital
primitives right along with analog stuff. I often simply use 74HC
behaviorals to speed up my design cycle, then convert to device-level.

[Jim Thompson]

Nope, no reorder... I symbolized it as an 8-pin block, pin order per
the data sheet... as you did.

[Lostgallifreyan]

Jim Thompson <To-Email-Use-Th...@On-My-Web-Site.com> wrote in

news:ba9uh7pk732mi0etc...@4ax.com:

> Nope, no reorder... I symbolized it as an 8-pin block, pin order per
> the data sheet... as you did.
>

Ok

[Lostgallifreyan]

Jim Thompson <To-Email-Use-Th...@On-My-Web-Site.com> wrote in

news:u97uh7peo4he06h6g...@4ax.com:

> On Tue, 24 Jan 2012 15:01:39 -0600, Lostgallifreyan
> <no-...@nowhere.net> wrote:
>
>>Jim Thompson <To-Email-Use-Th...@On-My-Web-Site.com> wrote
>>in news:2bvth7l6oknup47dn...@4ax.com:
>>
>>> Ran your schematic... behavior is extraordinarily weird, output hangs
>>> about 0.7V below ground when powered from +/-12V
>>>
>>> Please recheck your netlist. Thanks!
>>>
>>
>>I checked it, it's definitely wired ok, transistors are of correct type
>>and orientation, and the pins are correctly numbered according to node.
>>I can't model its parts so didn't check by running it.
>>
>>I can think of a few things that might matter. I didn't assign a ground,
>>so there was no node 0, it was node 15, and maybe there has to be a node
>>0 in all subcircuits.
>
> No. You don't need a Node Zero inside a subcircuit.
>

Ok. I thought not too, but reordered anyway, because I noticed that pin
orders must be contigous starting from 1 in a symbol, and I decided to
avoid similar trouble.

>>Also, I used European resistor value methods like 500R,
>
> Fixed right away.
>

Ok. In mine I just used literal values of ohms, and 12E-12 for that cap.

>>which LTspice can be told not to accept. Also, as LTspice uses M for
>>MOSFET and Q for bipolar, and I kept the numbering from the datasheet,
>>the first M value is 8, not 1, and there is no Q8. Maybe spice programs
>>don't like discontinuities like that.
>
> Not a problem in PSpice. I did have to fix your headers, "15" =>
> "N015", etc, otherwise everything "floats" :-)
>

Yeah, I just noticed that! I chucked any model that looked like it would
fit from the standard libraries just to see if I can run this. it took a
while, chewing, but it DID run, and my output from that equal-divider
test shows correct 2.5V from 5V input.

With 'startup' in .tran it does funny things extremely fast at low
amplitude, but that might just be because I threw models recklessly
inside it. It still settled down eventually to a correct DC output.

For the record, this is what I threw inside:

*MODELS NEEDED FOR CA3140 INNARDS

.model Diode D(Is=2.52n Rs=.568 N=1.752 Cjo=4p M=.4 tt=20n Iave=200m Vpk=75 mfg=OnSemi type=silicon)
.model Zener D(Is=1.13E-14 N=1.103 Vpk=15 bv=15 Ibv=0.005 Rs=0.4798 Cjo=4.023E-11 Vj=0.6144 M=0.3297 FC=0.5 mfg=Philips type=Zener)
.model NPN NPN(Is=7.049f Xti=3 Eg=1.11 Vaf=23.89 Bf=493.2 Ise=99.2f Ne=1.829 Ikf=.1542 Nk=.6339 Xtb=1.5 Br=2.886 Isc=7.371p Nc=1.508 Ikr=5.426 Rc=1.175 Cjc=5.5p Mjc=.3132 Vjc=.4924 Fc=.5 Cje=11.5p Mje=.6558 Vje=.5 Tr=10n Tf=420.3p Itf=1.374 Xtf=39.42 Vtf=10 mfg=PHILIPS)
.model PNP PNP(Is=1.02f Xti=3 Eg=1.11 Vaf=34.62 Bf=401.6 Ise=38.26p Ne=5.635 Ikf=74.73m Nk=.512 Xtb=1.5 Br=9.011 Isc=1.517f Nc=1.831 Ikr=.1469 Rc=1.151 Cjc=9.81p Mjc=.332 Vjc=.4865 Fc=.5 Cje=30p Mje=.3333 Vje=.5 Tr=10n Tf=524p Itf=.9847 Xtf=17.71 Vtf=10 mfg=PHILIPS)
.model NMOS VDMOS(Rg=3 Vto=2.2 Rd=22m Rs=5.5m Rb=28m Kp=10 lambda=.01 Cgdmax=.4n Cgdmin=.1n Cgs=.64n Cjo=.2n Is=25p mfg=Fairchild Vds=60 Ron=55m Qg=12.5n)
.model PMOS VDMOS(pchan Rg=3 Vto=-2.5 Rd=42m Rs=10.5m Rb=53m Kp=9 lambda=.01 Cgdmax=.5n Cgdmin=.12n Cgs=.8n Cjo=.24n Is=30p mfg=Fairchild Vds=-60 Ron=105m Qg=15n)

>
> It could be simply an issue with guessing the MOSFET parameters, for
> example M(Q)8... probably a long channel device to act like a variable
> resistor... how long, who knows? Plus that output current "sink"
> structure is plain-ass somebody's wet dream ;-)
>

It's a mystery to me entirely. :) All I could make of it was a weird
feedback potential but there is meant to be feedback anyway. For now
I'll have to accept my ignorance on this one. Likewise most of what follows...

> But the data sheet offers some clues, the strobe current is 220uA, so
> that's the current in Q3/Q4.
>
> Given the weirdness of that output stage I'm becoming inclined to
> model it as a mix of behavioral blocks plus NPN's to match the data
> sheet.
>
> The data sheet indicates to me that it's not the world's gift to OpAmp
> performance standards... why do you want to use it?
>

I found it performs very well in a laser diode analpog modulator I designed.
Better than other hobbyists are sellign boards to punters are acheiving. I
had to use LT1215 to sigificantly beat it. (And if you can recommend other
amps likely to share the essential qualities of those two (single rail,
fast slew rate), please do).

Also, it's been in general use for so long, and is always fairly easy to find.
Sometimes it might be better than using something newer (those hobbyists were
using new video amps and getting less performance, though my circuit might
suceed where theirs fail by using the amp(s) at unity gain or less and doing
the gain with a voltage regulator (of all things, but it DOES work...).

In short, I learned to like it a lot. I found it worked so often in various
things that I'd like to model it as first base in many new ideas.

> I invented that Q11, Q12, Q13 "turnaround"... see Tom Frederiksen's
> book, "Intuitive IC Op Amps", page 14. The schematic in the data
> sheet is NOT balanced... I suspect a typo... maybe there are more.
>

Nasty possibility... If so, it persisted from the Harris original.

> ...Jim Thompson

[Lostgallifreyan]

Jim Thompson <To-Email-Use-Th...@On-My-Web-Site.com> wrote in

news:d69uh7hsm9gpkg0tu...@4ax.com:

> PSpice _is_ a mixed-signal simulator. I can throw in digital
> primitives right along with analog stuff. I often simply use 74HC
> behaviorals to speed up my design cycle, then convert to device-level.
>

Hmm, logically I ought to apply that idea to my switches. :) If I needed
enough of them I might, for speed. As it is I used the voltage source and the
voltage controlled switch, and used my own arrangement of arguments to input
to the voltage used as a pulse, then subcircuited all, with appropriate
symbols. It works but leaves me thinking there ought to be a better way.

[Jim Thompson]

On Mon, 23 Jan 2012 06:22:25 -0600, Lostgallifreyan
<no-...@nowhere.net> wrote:

>Lostgallifreyan <no-...@nowhere.net> wrote in
>news:Xns9FE1C0DDF59...@216.196.109.145:
>

>Please help. I'm sure plenty of people here know Spice, and use the CA3240,
>and would have no trouble trying this subcircuit (below) as a quick
>substitution just to see if it works.
>
[snip]

The data sheet is amongst the worst I've ever seen.

Can you collect the following data:

(1) Unloaded supply current versus total supply voltage

(2) Maximum SINK current capability versus total supply voltage

[Lostgallifreyan]

Jim Thompson <To-Email-Use-Th...@On-My-Web-Site.com> wrote in

news:1ia1i7t48tsitavju...@4ax.com:

> The data sheet is amongst the worst I've ever seen.
>
> Can you collect the following data:
>
> (1) Unloaded supply current versus total supply voltage
>
> (2) Maximum SINK current capability versus total supply voltage
>

I got three samples of Intersil CA3140, of various ages, likely from
different sources, each set up as a voltage follower: wire links from Out
back to -In, +in to V- rail. The output was unloaded. 33 readings for each
IC. This data set may well be overkill, but I want quality so I have to give
it. :) It takes some endurance and patience with my setup to get stable
readings this accurate, so I'll sleep before I try for the sink currents.

Is there any change I must make to that voltage follower circuit I described
just now, for the sink current tests? Also, I assumed I'd have to limit the
current in whatever was on the output to prevent damage to the output, so I
don't understand what is needed to set up that test. (Might if I was less
tired, but please save me from a silly mistake tomorrow, as I have callers
to measure up fencing and cracked glass, plenty of distractions....)




TABLES OF 3 CA1410 IC'S, IDLE CURRENT DRAW AT BETWEEN 4VDC AND 26VDC.
(Current measured on 40 mA range of Fluke 79, series II).
(Voltage measured simultaneously on Fluke 77, series II).

V mA
Sample 1:
4.02 1.216
5.01 1.302
6.00 1.383
7.00 1.466
8.01 1.550
9.01 1.632
10.01 1.711
11.01 1.789
12.01 1.866
13.01 1.944
14.00 2.020
15.00 2.095
16.01 2.172
17.01 2.249
18.01 2.324
19.01 2.398
20.00 2.471
21.01 2.546
22.01 2.620
23.00 2.692
24.00 2.765
25.01 2.837
26.01 2.908
27.01 2.979
28.00 3.048
29.00 3.118
30.01 3.190
31.00 3.258
32.01 3.328
33.00 3.401
34.00 3.469
35.00 3.538
36.00 3.601

Sample 2:
4.00 1.331
5.00 1.446
6.01 1.535
7.01 1.621
8.00 1.706
9.01 1.789
10.00 1.868
11.01 1.946
12.00 2.022
13.01 2.100
14.00 2.174
15.01 2.249
16.01 2.268
17.01 2.294
18.00 2.370
19.01 2.446
20.01 2.521
21.00 2.595
22.01 2.670
23.01 2.744
24.00 2.817
25.00 2.889
26.01 2.962
27.00 3.031
28.00 3.104
29.01 3.174
30.00 3.242
31.01 3.314
32.01 3.384
33.00 3.456
34.00 3.522
35.00 3.588
36.00 3.655

Sample 3:
4.00 1.250
5.01 1.333
6.00 1.391
7.01 1.075
8.01 1.559
9.01 1.644
10.00 1.722
11.01 1.802
12.00 1.879
13.00 1.958
14.01 2.036
15.00 2.113
16.01 2.191
17.01 2.268
18.00 2.341
19.01 2.418
20.01 2.493
21.00 2.567
22.00 2.642
23.00 2.716
24.01 2.790
25.01 2.863
26.01 2.936
27.00 3.007
28.01 3.079
29.01 3.148
30.00 3.218
31.01 3.287
32.01 3.357
33.00 3.431
34.00 3.495
35.00 3.562
36.00 3.632

[Lostgallifreyan]

Lostgallifreyan <no-...@nowhere.net> wrote in
news:Xns9FE63BF8B1B...@216.196.109.145:

> 26VDC

It will be obvious, but that should be 36VDC. :)

[Lostgallifreyan]

Lostgallifreyan <no-...@nowhere.net> wrote in
news:Xns9FE63BF8B1B...@216.196.109.145:

Maybe worth mentioning the ambient temperature: 21°C. Same for all three idle
current tests.

[Lostgallifreyan]

I looked at the Intersil datasheet and saw a graph for idle current vs
voltage that suggested my readings were half what they should be! As the
milliamp range on a meter is the most easily damaged, I did a simple test to
see what if any scale change should be made to my readings to get accuracy
from them.

3.802V across Li-ion cell loaded by 996 ohms.
Calculated current: 3.776mA.
Actual current: 3.817mA.

Not as close as they should be, but much closer than the difference between
datasheet graphs and measured values.

[Jim Thompson]

On Wed, 25 Jan 2012 23:53:45 -0600, Lostgallifreyan
<no-...@nowhere.net> wrote:

>Jim Thompson <To-Email-Use-Th...@On-My-Web-Site.com> wrote in
>news:1ia1i7t48tsitavju...@4ax.com:
>
>> The data sheet is amongst the worst I've ever seen.
>>
>> Can you collect the following data:
>>
>> (1) Unloaded supply current versus total supply voltage
>>
>> (2) Maximum SINK current capability versus total supply voltage
>>
>
>I got three samples of Intersil CA3140, of various ages, likely from
>different sources, each set up as a voltage follower: wire links from Out
>back to -In, +in to V- rail. The output was unloaded. 33 readings for each
>IC. This data set may well be overkill, but I want quality so I have to give
>it. :) It takes some endurance and patience with my setup to get stable
>readings this accurate, so I'll sleep before I try for the sink currents.
>
>Is there any change I must make to that voltage follower circuit I described
>just now, for the sink current tests? Also, I assumed I'd have to limit the
>current in whatever was on the output to prevent damage to the output, so I
>don't understand what is needed to set up that test. (Might if I was less
>tired, but please save me from a silly mistake tomorrow, as I have callers
>to measure up fencing and cracked glass, plenty of distractions....)
>
>

[snip]

The implication from the data sheet is that it's limited to some small
amount... the data sheet says, at 5V, Isinkmax=1mA :-(

Maybe, as a follower, input biased at midpoint, pull up output with a
voltage source (gently :-) and observe current?

[Lostgallifreyan]

Jim Thompson <To-Email-Use-Th...@On-My-Web-Site.com> wrote in

news:lar2i7tpd1ladt5dl...@4ax.com:

> Maybe, as a follower, input biased at midpoint, pull up output with a
> voltage source (gently :-) and observe current?
>

Midpoint between negative and positive supply, or between negative and the
same fixed voltage that pulls up the output? (I'll use 5V through a resistor
value of your choosing for the output pullup, so we have known conditions).

[Jim Thompson]

On Thu, 26 Jan 2012 09:51:10 -0600, Lostgallifreyan
<no-...@nowhere.net> wrote:

>Jim Thompson <To-Email-Use-Th...@On-My-Web-Site.com> wrote in
>news:lar2i7tpd1ladt5dl...@4ax.com:
>
>> Maybe, as a follower, input biased at midpoint, pull up output with a
>> voltage source (gently :-) and observe current?
>>
>
>Midpoint between negative and positive supply,

My original thought.

>or between negative and the
>same fixed voltage that pulls up the output? (I'll use 5V through a resistor
>value of your choosing for the output pullup, so we have known conditions).

Maybe easier: Use split supplies, ground input, then use variable
resistor to +. When output lifts from zero, that's the maximum sink
current.

[Lostgallifreyan]

Jim Thompson <To-Email-Use-Th...@On-My-Web-Site.com> wrote in

news:88u2i7l7ud01f95vc...@4ax.com:

> Maybe easier: Use split supplies, ground input, then use variable
> resistor to +. When output lifts from zero, that's the maximum sink
> current.
>

Nice, that fits with a vague idea I had earlier too. I'll set that up later
and get you some results. With two tweaks per sampling it will take longer
but I like the method.

[Lostgallifreyan]

Jim Thompson <To-Email-Use-Th...@On-My-Web-Site.com> wrote in

news:88u2i7l7ud01f95vc...@4ax.com:

> When output lifts from zero, that's the maximum sink
> current.
>

I think that test might be impossible. I used a single rail as before (my
supply arrangements won't allow a split AND variable supply to test with.)

I grounded the voltage follower input to negative as for the first test. A DC
offset appears on the output, about 3.2mV at 4V supply, rising in nonlinear
slope to about 6.1 mV at 36V supply. Even if this didn't make things
intractably tedious, I found that a Li-ion cell in series with as much as 47K
between output and negative ground causes a few mV added to the offset on
the output, and 83µA to flow through the output pin, a value that is very
constant from 4V to 36V supply. It suggests that the method fails with no
definable point at which output voltage rises due to loss of current sinking.
Even with the offset there to confuse things, it should have been possible to
see a discontinuous change in the output voltage with respect to current
change around 1 mA if the datasheet is to be beleived. There isn't one, or if
there is, its signal is swamped by noise from offset and whatever else is
going on. I saw the same result with two IC's and didn't try the third.

[Lostgallifreyan]

I know that Google isn't all that at times, but beat this for a new low:
No results found for "measuring sink current"

What to do, what to do....?
Surely there IS a way? If not, how and why does anyone specify this for an
op-amp? After today's debacle it will be some time before my head clears
enough to solve this.

[Jim Thompson]

OK. Single supply. Ground Input. Load Output with resistor to V+.
Lower resistor value until Output is at +1V. Record value of resistor
and of V+. Do that for V+ = 5V, 10V, and 15V. That should be enough
data.

(I have the basic core running to specification. All I need is to add
the sink current.)

[Lostgallifreyan]

Jim Thompson <To-Email-Use-Th...@On-My-Web-Site.com> wrote in

news:0hl3i7d947gvldlhm...@4ax.com:

> OK. Single supply. Ground Input. Load Output with resistor to V+.
> Lower resistor value until Output is at +1V. Record value of resistor
> and of V+. Do that for V+ = 5V, 10V, and 15V. That should be enough
> data.
>

That won't work either. I set up for 5V supply, found resistors such that a
1K pot (all I have available) in series will find the 1V pullup on output.
What happens is that at just over 200mV it latches up to 2.3V or so! There's
a lot of hysteresis there, I can reduce that to about 1.5V at which point it
suddenly collapses to 147mV.

I remember the datasheet saying that the voltage follower needs at least 3K9
as current limit, so I tried a 4K7 to see if this fixed the problem, but it
doesn't. The ONLY clearly consistent feature of both attempts as this test is
to reveal some hint of nonlinearity. I doubt anything I have will nail it.

I did try a second IC with near-identical results, then set to 10V supply,
and found that the total resistance needed to do it was about 2K less. The
start point of the jump was a similar voltage, and the end point over 8V.

> (I have the basic core running to specification. All I need is to add
> the sink current.)
>

I think we're going to have to permanently do without it, or go with the
datasheet nominal declaration. If what you need is a linear(ish) quality,
this amp doesn't seem to have it.

[Jim Thompson]

That dynamic current sink is a crock... as I already opined. If the
schematic is anything resembling that shown in the data sheet, it's
definitely a latch (positive feedback).

Where in the data sheet is the 3K9 requirement?

[Lostgallifreyan]

Jim Thompson <To-Email-Use-Th...@On-My-Web-Site.com> wrote in

news:p7t3i7dcm8as1b1tt...@4ax.com:

> That dynamic current sink is a crock... as I already opined. If the
> schematic is anything resembling that shown in the data sheet, it's
> definitely a latch (positive feedback).
>

Certainly looked like one. If it's of any use, I could maybe do the test
using 100 mV instead of 1V. It may even let me do 200 mV if it latches at
above that on all supply voltages. (Doubtful).

> Where in the data sheet is the 3K9 requirement?
>

Intersil datasheet CA3140, CA3140A, September 1998, File Number 957.4
(Excerpt starts near end of page 7. Whether this is much different from yours
I don't know).

"As mentioned previously, the amplifier inputs can be driven
below the Terminal 4 potential, but a series current limiting
resistor is recommended to limit the maximum input terminal
current to less than 1mA to prevent damage to the input
protection circuitry.
Moreover, some current limiting resistance should be
provided between the inverting input and the output when
the CA3140 is used as a unity gain voltage follower. This
resistance prevents the possibility of extremely large input
signal transients from forcing a signal through the input
protection network and directly driving the internal constant
current source which could result in positive feedback via the
output terminal. A 3.9k resistor is sufficient."

[Jim Thompson]

That's NOT output current limiting.... read carefully.

[Lostgallifreyan]

Jim Thompson <To-Email-Use-Th...@On-My-Web-Site.com> wrote in

news:vh24i79bak8er70ns...@4ax.com:

>>"As mentioned previously, the amplifier inputs can be driven
>>below the Terminal 4 potential, but a series current limiting
>>resistor is recommended to limit the maximum input terminal
>>current to less than 1mA to prevent damage to the input
>>protection circuitry.
>>Moreover, some current limiting resistance should be
>>provided between the inverting input and the output when
>>the CA3140 is used as a unity gain voltage follower. This
>>resistance prevents the possibility of extremely large input
>>signal transients from forcing a signal through the input
>>protection network and directly driving the internal constant
>>current source which could result in positive feedback via the
>>output terminal. A 3.9k resistor is sufficient."
>
> That's NOT output current limiting.... read carefully.
>

I realise that, though I don't fully understand it either. I thought what it
was meant to avoid was the result of a fast swing of the output feeding a
transient back to the inverting input, in response to one arriving on the
non-inverting input. Whatever it is exactly, I didn't think the resistor
would fix the latchup problem in that test because that is a result, not a
cause, in this case directly from the pullup. I just tried that resistor
because it was suggested, so NOT trying it seemed like a bad idea. In
practise, I've often used a CA3140 as a voltage follower with a direct link
feedback, no resistor, and never run into trouble. I didn't know about that
3.9K recommendation until a couple of days ago.

[Lostgallifreyan]

Jim Thompson <To-Email-Use-Th...@On-My-Web-Site.com> wrote in

news:vh24i79bak8er70ns...@4ax.com:

>> If it's of any use, I could maybe do the test
>> using 100 mV instead of 1V.

Go, or no go?

[Jim Thompson]

Put 10K in the feedback just to make sure it isn't latching up via the
input ESD structure.

Use a resistive divider at the input to establish a midpoint input.

Before any loading, verify that output is also midpoint.

Can you get your hands on a decade resistor box?

Start with it set at least 20K

Connect it between output and V+ (thru you ammeter)

Gradually reduce resistance value avoiding massive steps by backing up
to a high setting before down-ranging.

Record current at which output node lifts.

This CA3140 may well be a POS, but your query has stirred my mind to
improve my generalized OpAmp to include:

(1) Output dead-band
(2) Output current limiting, V+ and V- values independently set
(3) Supply currents
(4) Swing limits (including load effects)

All with just 2 simple TANH functions... convergence guaranteed... all
derivatives exist :-)

[Jim Thompson]

On Fri, 27 Jan 2012 08:45:34 -0700, Jim Thompson
<To-Email-Use-Th...@On-My-Web-Site.com> wrote:

[snip]

>
>This CA3140 may well be a POS, but your query has stirred my mind to
>improve my generalized OpAmp to include:
>
>(1) Output dead-band
>(2) Output current limiting, V+ and V- values independently set
>(3) Supply currents
>(4) Swing limits (including load effects)
>
>All with just 2 simple TANH functions... convergence guaranteed... all
>derivatives exist :-)
>
> ...Jim Thompson

I missed mentioning (5) ROUT... independent values for sourcing and
sinking :-)

[Lostgallifreyan]

Jim Thompson <To-Email-Use-Th...@On-My-Web-Site.com> wrote in

news:lsg5i71e178pmkp99...@4ax.com:

I can't go further on this. I just spent three hours with resistors,
tweezers, a magnifier, I can barely see to type now. No resistor box, just a
pin deck and various resistors, and op-amps that may or may not be broken now
for all I know.

What results I did get were weird. First, I got VERY few results, running ten
miles is less stressful. :) Trust me, I know.

Sample 1:
V mA Ltch mA Lift
5.12 0.760
10.01 1.074
15.01 1.206
20.02 1.588
25.02 1.560
30.02 1.842
35.00 2.048 1.310

That's it, and it's enough for me to conclude that going further will not
yield a pattern to grasp at all.

First, that latchup still occurs, even with 10K for feedback resistor.
Second, when the lift starts to occur, it is sharp, at a lower current but
still a latchup, just a smaller one. There is nothing neat, linear or
predictable about any of this. With supply voltages above 20V, the current
FELL from a slightly higher peak before latchup occured, as resistance from
out to V+ was gently lowered.

If this hasn't tried your patience as much as mine, please can you take a
brief look here:
http://repairfaq.cis.upenn.edu/Misc/laserdps.htm#dpsldd317
It's my laser driver, using a CA3140 if that's all avaliable, good for over
200 KHz easily, with fairly good wave shapes. LT1215 was needed to get it
good to 1 MHz and beyond. (Sam Goldwasser has seen it and confirms that it
works). My question is, as CA3140 seems to justify the POS tag :) .... can
you suggest amps that are more widely available than the LT1215 that might do
as well, or better? Bear in mind that unity gain or less for these amps (the
LM317 is doing the grunt work) seems to imply that fast slew rate is vital,
but high GBP is less so. (Other people using video amps are getting less fast
and shapely waveforms at 100 KHz in their drivers, than mine gets at 200 KHz
or more, even with the CA3140. Not bragging, this is purely to set context.
It's an unusual situation). I want to make this easy for people to build.
GEtting LT1215's isn't so easy, or as cheap, as CA3140, and the margin of
difference is enough that I hope to find other contenders better placed than
either to do this well. Whatever I try must run on a single rail supply as
well as having fast slew rate. Apparently not an easy pairing of requirements
to meet....

[Lostgallifreyan]

Jim Thompson <To-Email-Use-Th...@On-My-Web-Site.com> wrote in

news:0hl3i7d947gvldlhm...@4ax.com:

> (I have the basic core running to specification. All I need is to add
> the sink current.)
>

Despite my new wariness about this amp, and the intractability of getting any
clear picture of current sink limitations, I'm still pleased about that, and
keen to try the model. :) It's worth having purely because that IC is so
widely used, and many people might still reach for one whenever they want a
very high resistance input and a single rail supply, especially as they
probably have one somewhere.

[Jim Thompson]

On Fri, 27 Jan 2012 16:51:39 -0600, Lostgallifreyan

I'll post my subcircuit as it stands right now and you can see if it
remotely matches your measured performance.... unwrap the usual
suspects...

******************************************************************
****** PINS: 1 2 3 4 5 6 7 8 ******
.SUBCKT CA3140 NULL1 INN INP VN NULL5 OUT VP STROBE
Q_Q11 N_1 N_1 NULL5 CA3046_ORG
Q_Q12 N_2 N_1 NULL1 CA3046_ORG
C_CIN INP INN 4pF
GDC_I2 VP STROBE VALUE
{(1+TANH(2.2976*(2*V(VP,STROBE)/1V-1)))*200uA/2}
Q_Q17 VP STROBE N_3 CA3046_ORG
R_R11 N_4 N_5 20
R_R9 N_6 N_4 50
R_R10 N_7 N_4 1K
Q_Q19 N_8 N_7 N_5 CA3046_ORG
Q_QD7 VP VP N_6 CA3046_ORG
R_R8 N_3 N_9 1K
GDC_I3 N_3 VN VALUE {(1+TANH(2.2976*(2*V(N_3,VN)/1V-1)))*2uA/2}
Q_Q13 STROBE N_2 VN CA3046_ORG
R_R5 NULL1 VN 500
R_R4 NULL5 VN 500
F_F1 STROBE VN VF_F1 1
VF_F1 VP N_8 0V
Q_Q18 N_5 N_9 OUT CA3046_ORG
G_G2 OUT VN VALUE { (TANH(3.66*V(OUT, N_9)-1.83)+19/17)*8.5mA
}
C_C1 STROBE N_2 12pF
G_G1 N_2 N_1 VALUE { (TANH(2.2/188mV*V(INP, INN))+1)*25uA }
GDC_I1 VP N_2 VALUE
{(1+TANH(2.2976*(2*V(VP,N_2)/1V-1)))*50uA/2}
******************************************************************
.MODEL CA3046_ORG NPN IS=3.860200F BF=120 NF=1.04845 VAF=61.1026 IKF=
+ 50.000000M ISE=3.100000P NE=2.16533 BR=100.101000M NR=1.04845 ISC=0
+ NC=1 RB=214.644 RBM=214.644 RE=721.362980M RC=9.2065 CJE=1.249000P
+ VJE=899.999940M MJE=499.999970M TF=210.000000P XTF=1.85 VTF=1.585
+ ITF=50.000000M PTF=0 CJC=1.000000P VJC=749.999940M MJC=333.000000M
+ XCJC=499.999970M TR=10.000000N CJS=6.300000P VJS=749.999940M MJS=
+ 499.999970M XTB=1.5 EG=1.11 XTI=3 KF=0 AF=1 FC=499.999970M
******************************************************************
.ENDS CA3140
******************************************************************

[Lostgallifreyan]

Jim Thompson <To-Email-Use-Th...@On-My-Web-Site.com> wrote in

news:mbd6i7t4ea1jr2tr3...@4ax.com:

> I'll post my subcircuit as it stands right now and you can see if it
> remotely matches your measured performance.... unwrap the usual
> suspects...
>

It has about -0.6V of output spiking not seen in real ones when a 5V
200 KHz square wave goes negative on the inverting input of a differential
amplifier, and a small kink in the slope when the input signal rises. This
kink occurs slightly earlier on the slope if the load is reduced from 1K to
10K. It's definitely slightly odd. Generally the frequency response seems
about right, judging by effects on square waves at 1 MHz, but they're spikier
than the real ones would be.

(All this bearing in mind that LT1215 was showing very close agreement
between model and built circuit in virtually identical context (only the
compensation caps were absent in the CA3240 version as it doesn't need
them, and this is true for the current model too, where they make no
difference to the wave other than a very slight recuction in that spiking).

Please let me know if you have suggestions for that laser driver's op-amps.
http://repairfaq.cis.upenn.edu/Misc/laserdps.htm#dpsldd317
I think you're right that the CA3140 (CA3240 in this case) is not to be
relied on, and I hope that the LT1215 is not the only game in town! It's
great but I imagine there may be a standard that is cheaper and easier to get
while being as good, and that maybe better ones exist too. I need a dual amp,
for single rail, with fast slew, ideally unconditionally stable at unity
gain. Something that makes a 1 MHz square have a bit more snap to its rise
and fall times. There may be amps that work well in this context that might
not be expected to, knowing that CA3140 even works at all well, and that
LT1215 works very well, might help prompt ideas from you because you know
amps a lot better than me. I Googled for months, and followed LT's and NS's
IC suggestions without coming up with much. Maybe there isn't, but if LT can
make the LT1215 I do hope someone made some good alternative to try.

[Jim Thompson]

What puzzled me is I couldn't get a match between DC open-loop gain
and the gain-bandwidth crossing point... I get about 11MHz GBW with
100dB at DC, so I generally don't trust the data sheet... which says
~4MHz. My 11MHz probably accounts for the "spikier" transient
behavior.

[Lostgallifreyan]

Jim Thompson <To-Email-Use-Th...@On-My-Web-Site.com> wrote in

news:kgh6i7lktgbqb90va...@4ax.com:

The negative-going overshoot is large, maybe 100 times what it would be in a
real one at 200 KHz. I deliberately slowed the input square wave slopes to
1盜 (not that much flat-time left after that, at 200 KHz), and it didn't help
much. In a context with very little parasitic inductance or capacitance no
op-amp should have this problem.

What DID help a lot was choosing the resistors in the first stage
differential amp of that laser driver circuit to be higher than those the
LT1215 wants for fast accuracy. Instead of 3K3 and 680R, I tried 33K and 6K8,
which removed the 'undershoot' but rounded off the wave far too much, so then
I tried 10K and 2K, (ratio close enough), and the result is very good. But as
far as I know, the CA3140 would not be that sensitive to these changes in
resistance.

What are the values of the zeners in that original schematic? Also, what are
the three or so most important spice parameters to be used in the internal
models for the BJT, MOS, and diode models?

Also, what other op-amp might work for that laser driver circuit I linked to?
(Single rail, fast slew, dual stage, pluggable replacement for CA3240,
LT1215...)

[Jim Thompson]

On Sat, 28 Jan 2012 08:11:33 -0600, Lostgallifreyan

The CA3140 datasheet has conflicting statements, low sink current, yet
18mA short to V+, so I scaled to that short current. Thus a
suggestion, in this line...

G_G2 OUT VN VALUE {(TANH(3.66*V(OUT, N_9)-1.83)+19/17)*8.5mA}

^^^^^
Reduce this value--------------------------------------^^^^^

Until peaking matches your measurements.

[josephkk]

On Tue, 24 Jan 2012 11:54:18 -0700, Jim Thompson
<To-Email-Use-Th...@On-My-Web-Site.com> wrote:

>On Mon, 23 Jan 2012 06:22:25 -0600, Lostgallifreyan
><no-...@nowhere.net> wrote:
>
>>Lostgallifreyan <no-...@nowhere.net> wrote in

>>news:Xns9FE1C0DDF59...@216.196.109.145:
>>
>[snip]
>
>Ran your schematic... behavior is extraordinarily weird, output hangs
>about 0.7V below ground when powered from +/-12V
>
>Please recheck your netlist. Thanks!
>
> ...Jim Thompson

Is your test circuit in LTSpice form? I would like to fiddle with the
model in LTSpice.

?-)

[Jim Thompson]

On Sat, 28 Jan 2012 15:40:54 -0800, josephkk <joseph_...@sbcglobal.net>
wrote:

I posted a model that Lostgallifreyan says is "peaky" in the negative
direction, but otherwise looks good. I posted I based it on data sheet,
choosing the largest of confusing "sink" terms. Suggested a tweak downward.
Haven't heard back yet.

...Jim Thompson
--
[On the Road, in New York]

[Lostgallifreyan]

Jim Thompson <To-Email-Use-Th...@On-My-Web-Site.com> wrote in

news:ej58i7pd9hpji15c7...@4ax.com:

Lowering it didn't help. Raising it to 12 mA did, but an oscilloscpe of the
real output shows a similar spike on the end of rising slopes where the model
has none. Both are of about quarter the duration of the spike in the model
output. (This in a differential amp circuit with 3K3 and 680R resistors for
gain reduction, input to inverting side, noninverting side fed by 5.1V zener
reference.)

With the real circuit and the model using 10K and 2K2 resistors the model's
spike proportions are better, roughly equal for rising and falling slopes,
with duration looking about right. The real circuit has larger spikes where
the model's spikes shrank. The scale might be to do with parasitcs in the
pindeck but I don't know why the change reverses, scaling upwards in reality,
and downwards in the model.

Ok, any chance of an answer to my earlier questions now? :)

[Lostgallifreyan]

Lostgallifreyan <no-...@nowhere.net> wrote in
news:Xns9FEB1384C8C...@216.196.109.145:

> Lowering it didn't help. Raising it to 12 mA did, but an oscilloscpe of
> the real output shows a similar spike on the end of rising slopes where
> the model has none. Both are of about quarter the duration of the spike
> in the model output. (This in a differential amp circuit with 3K3 and
> 680R resistors for gain reduction, input to inverting side, noninverting
> side fed by 5.1V zener reference.)
>
> With the real circuit and the model using 10K and 2K2 resistors the
> model's spike proportions are better, roughly equal for rising and
> falling slopes, with duration looking about right. The real circuit has
> larger spikes where the model's spikes shrank. The scale might be to do
> with parasitcs in the pindeck but I don't know why the change reverses,
> scaling upwards in reality, and downwards in the model.
>
> Ok, any chance of an answer to my earlier questions now? :)
>

More... Raising that value further, to 15mA, makes the model's output much
closer to the real one with both sets of resistor values in the diff amp, and
also the output for the 10K/2K2 pairing is slightly larger than that for the
3K3/680R pairing, which agrees with the scale change in reality much better
than using 12mA for that value.

Please let me know if you can answer my questions, I imagine that you likely
have some op-amp in mind that does better than CA3140 for fast slew, single
rail, and high resistance inputs. While I found LT1215 in my searches, there
might be something cheaper and far easier to find that I don't know about.

I'm also still interested in trying parts models in the original incomplete
model I made, if I ever find any BiMOS models with internal models to try.
Knowing the zener voltages used in those four zener diodes will help though,
I don't know what those are and I'm hoping you can tell me. Finally, assuming
I don't find actual BiMOS models for the BJT's and MOSFETs, I imagine from
what I see in other subcircuits, that maybe just three of four important
parameters may be enough to modify a standard model in LTspice. What
parameters might those be? Whther or not I can make a viable model this way
isn't so important as what I might lear from trying, so please let me know so
I have somethign to start with..

[Lostgallifreyan]

One other thing that model seems to need is an additional 6.8pF of internal
capacitance for compensation in its feedback loop. There's plenty I don't
understand about this but I do know that a real one wouldn't need this in
same context. Even if it is only real-world parasitic capacitance that tames
the beast, it is nice not to have to add parts to a modelled circuit that
don't need adding in the real one, and that extra 5.8pF does nothing to harm
the modelled waveforms.

If there are any other problems I haven't seen any.

[Lostgallifreyan]

Lostgallifreyan <no-...@nowhere.net> wrote in
news:Xns9FEB1AAA677...@216.196.109.145:

> If there are any other problems I haven't seen any.
>
>

Just found one... If I model a voltage follower and feed it with a negative
voltage while running with a single supply rail, the output is -1.14211V. Tt
should be impossible to sustain a negative voltage in this situation. I
imagine small spikes might go south of the negative rail due to any
inductance or capacitance present, but not DC.

[josephkk]

On Mon, 30 Jan 2012 06:27:50 -0700, Jim Thompson
<To-Email-Use-Th...@On-My-Web-Site.com> wrote:

>
>>>Ran your schematic... behavior is extraordinarily weird, output hangs
>>>about 0.7V below ground when powered from +/-12V
>>>
>>>Please recheck your netlist. Thanks!
>>>
>>> ...Jim Thompson
>>
>>Is your test circuit in LTSpice form? I would like to fiddle with the
>>model in LTSpice.
>>
>>?-)
>
>I posted a model that Lostgallifreyan says is "peaky" in the negative
>direction, but otherwise looks good. I posted I based it on data sheet,
>choosing the largest of confusing "sink" terms. Suggested a tweak downward.
>Haven't heard back yet.
>
> ...Jim Thompson

I saw a couple of models, i guess i don't know how to setup the test jig
file. A couple of pointers on how to connect it to a symbol and include
the subcircuit model should help.

?-)

[Lostgallifreyan]

josephkk <joseph_...@sbcglobal.net> wrote in
news:31ahi71eesh34so2i...@4ax.com:

> I saw a couple of models, i guess i don't know how to setup the test jig
> file. A couple of pointers on how to connect it to a symbol and include
> the subcircuit model should help.
>

Save model as CA3140.sub in the sub directory (if using LTspice).
Edit it to use just five pins, by replacing the line that begins .SUBCKT,
like this:
.SUBCKT CA3140 INP INN VP VN OUT
Put an asterisk at the start of the original in case you ever want to use the
offset null or strobe pins.


Then save the following as CA3140.asy in the op-amps subdirectory of the sym
directory. There are other ways to link symbols with subcircuits but this is
the most direct and easy to use. If you end up wanting a smaller symbol you
can copy the LINE statements from it to replace the ones here, then edit the
file in the graphic editor to move the pins. Just make sure if you do that,
that you keep the pin order correct, and always 1 through N, LTspice doesn't
accept gaps in pin count numbering.

Version 4
SymbolType CELL
LINE Normal 12 -16 20 -16
LINE Normal 16 -20 16 -12
LINE Normal 12 16 20 16
LINE Normal -12 16 -12 32
LINE Normal -20 24 -4 24
LINE Normal -20 -24 -4 -24
LINE Normal -28 -32 -48 -32
LINE Normal -28 32 -48 32
LINE Normal 60 0 80 0
LINE Normal 16 25 16 32
LINE Normal 16 -25 16 -32
LINE Normal 60 0 -28 -51
LINE Normal -28 51 60 0
LINE Normal -28 -51 -28 51
SYMATTR Value CA3140
SYMATTR Prefix X
SYMATTR ModelFile CA3140.sub
SYMATTR Value2 CA3140
SYMATTR Description CA3140 4.5MHz Op-Amp with MOSFET Input/Bipolar Output
PIN -48 32 NONE 0
PINATTR PinName In+
PINATTR SpiceOrder 1
PIN -48 -32 NONE 0
PINATTR PinName In-
PINATTR SpiceOrder 2
PIN 16 -32 NONE 0
PINATTR PinName V+
PINATTR SpiceOrder 3
PIN 16 32 NONE 0
PINATTR PinName V-
PINATTR SpiceOrder 4
PIN 80 0 NONE 0
PINATTR PinName OUT
PINATTR SpiceOrder 5

[Lostgallifreyan]

Lostgallifreyan <no-...@nowhere.net> wrote in
news:Xns9FEBA85A175...@216.196.109.145:

Hello Jim, did you see this one?
Also, the earlier one about unity gain stabilising capacitance..

[Jim Thompson]

Neither one. I've been busy with "real" work ;-)

Elaborate on the follower conditions... are you saying output is below
rail? What load did you have, if any? I'm thinking on a
generalized OpAmp model which definitely solves such issues, but am
embroiled in other mathematical niceties at the moment ;-)

What is the unity gain stabilizing capacitance issue?

[Lostgallifreyan]

Jim Thompson <To-Email-Use-Th...@On-My-Web-Site.com> wrote in

news:4pm7j79ijbdob79c6...@4ax.com:

> Elaborate on the follower conditions... are you saying output is below
> rail? What load did you have, if any? I'm thinking on a
> generalized OpAmp model which definitely solves such issues, but am
> embroiled in other mathematical niceties at the moment ;-)
>
> What is the unity gain stabilizing capacitance issue?
>

No hurry, I just nudged because I know that with time, it gets harder to
return to any specific problem. (I'm learning C and some API stuff so I have
the same problem here).

Anyway, it's no-load, -1.14V, 1K pad, -1.022V, 100R, -0.198.6V, so definitely
iffy, as no amp can provide a DC voltage below its negative with any actual
drive current. Inductive or capacitive spikes on pulses, sure, but not with
steady DC.

The stabilising needed is to prevent a small fast noisy oscillation. Same
reason it would usually be applied. The CA3140 is internally stabilised, so
needs something done to prevent us having to add it externally. We can do it,
but if we have to, it's safe to assume the model isn't accurate enough.

----

Remember I asked some other questions? Basically, what zener voltages for
those four zeners in that schematic. I haven't ruled out playing around with
that, and some minimum Spice parameters like Xti and suchlike to use to
modify default LTspice native models for diodes and BJT and MOSFET for this
NIMOS amp. I've seen many op-amp models that do this, using as little as
three or four specied parameters, which suggests that even an ignoramus like
me has a fighting chance of coming up with the goods purely by trial and
error if you can tell me which parameters are the most important ones to
modify for each internal part. I imagine there may be something specific to
the BIMOS contruction that can guide to a choice for those parameters.

In short, my insticts tell me that staying as close to the original
schematic, and using values common to each sub-modelled part, will get a
useable model. It's a different approach to yours, but I want to try it.

[Lostgallifreyan]

Lostgallifreyan <no-...@nowhere.net> wrote in
news:Xns9FF4A3F402F...@216.196.109.145:

> 1K pad

???
I'm fairly sure I typed 'load' but never mind.. :)

[Jim Thompson]

The CA3140 data sheet and _schematic_ are suspect. There are
conflicting specifications. As an I/C designer the schematic has an
"odor of mendacity" about it :-)

The model I'm pondering in my head takes my present basic model with
GDC, GBW, slew-rate, Rout, phase-margin, and positive and negative
swing limit specifiable... but modified as follows:

Rout => Rout-sourcing, Rout-sinking (separate values)
Current limit sourcing and sinking (separate values)
Power supply pins will reflect load _and_ quiescent currents
Output swing limits specifiable relative to rail potentials

It may even show recovery time from slamming into rails... not quite
sure yet, but I think so :-)

[Lostgallifreyan]

Jim Thompson <To-Email-Use-Th...@On-My-Web-Site.com> wrote in

news:tvr7j7lk7esh7cuae...@4ax.com:

> The CA3140 data sheet and _schematic_ are suspect. There are
> conflicting specifications. As an I/C designer the schematic has an
> "odor of mendacity" about it :-)
>

But you see my problem... On the one hand I am told I have a datasheet that
lies, on the other, a model that puts out negative DC in a way that might
have precluded any need for switchmode generators of nagtive rails had it
really worked that way in silicon.

Either way I'm at a loss.

[Jim Thompson]

I modeled the output with only a current limit... no swing bounds
except for the feedback. YOU violated the rules ;-)

[Lostgallifreyan]

Jim Thompson <To-Email-Use-Th...@On-My-Web-Site.com> wrote in

news:npv7j7d32rmu10oq7...@4ax.com:

> I modeled the output with only a current limit... no swing bounds
> except for the feedback. YOU violated the rules ;-)
>

How so? :) All I did was try to measure the thing according your
directions... It's looked extremely inconsistent so I understand that it can
be hard to model, but I don't think working from a basic model will work,
other than to create an idea of what it should do, especially if it ends up
outputing steady voltages below its nagative rail. What's needed is a model
of what it does.

[Jim Thompson]

Didn't you say you input a voltage below negative rail?

[Lostgallifreyan]

Jim Thompson <To-Email-Use-Th...@On-My-Web-Site.com> wrote in

news:h528j7pq8pc7kh34d...@4ax.com:

> On Thu, 09 Feb 2012 11:33:17 -0600, Lostgallifreyan
> <no-...@nowhere.net> wrote:
>
>>Jim Thompson <To-Email-Use-Th...@On-My-Web-Site.com> wrote
>>in news:npv7j7d32rmu10oq7...@4ax.com:
>>
>>> I modeled the output with only a current limit... no swing bounds
>>> except for the feedback. YOU violated the rules ;-)
>>>
>>
>>How so? :) All I did was try to measure the thing according your
>>directions... It's looked extremely inconsistent so I understand that it
>>can be hard to model, but I don't think working from a basic model will
>>work, other than to create an idea of what it should do, especially if
>>it ends up outputing steady voltages below its nagative rail. What's
>>needed is a model of what it does.
>
> Didn't you say you input a voltage below negative rail?
>
> ...Jim Thompson

It doesn't matter. I used a -2V modelled input, but it's a high resistance
input (several terohms probably) and I put a 1Meg resistor on it anyway just
to be sure. No real world amp will maintain a DC output voltage below its
negative supply rail, into a 1K load and still hold over a volt below that
rail. That takes a lot more energy than will ever leak though that input from
a -2V source. You can't get something for nothing in a real op-amp.

[Jim Thompson]

On Thu, 09 Feb 2012 12:50:57 -0600, Lostgallifreyan

You be not paying attention. Read every iota of what I've written
today.

[Lostgallifreyan]

Jim Thompson <To-Email-Use-Th...@On-My-Web-Site.com> wrote in

news:vn68j7hd5i7ldcjra...@4ax.com:

it really does not matter WHAT happens here. You're asking me to accept a
model that will output such that it holds -1V below its negative rail. I will
not do that. No-one should. Real amps don't do this.

You can take any 1Meg resitor, Spice or otherwise, it won't hold more than
200 mV across a 1K resistor. Your model is generating, it is not merely being
powered by a virtual supply, it IS one!

Browbeating me into appearing like a lazy noob is not going to distract
anyone from this issue, as the model you posted is out there now for anyone
to prove this.

[Jim Thompson]

On Thu, 09 Feb 2012 13:50:52 -0600, Lostgallifreyan

Gawd! You're so dense you've become a Slowman look-alike.

In... Message-ID: <npv7j7d32rmu10oq7...@4ax.com>

I said, "I modeled the output with only a current limit... no swing
bounds except for the feedback." [YOUR feedback loop]

In... Message-ID: <tvr7j7lk7esh7cuae...@4ax.com>

I said, "The model I'm pondering in my head takes my present basic
model..."

[My "present basic model" is not what I tried to use to fit the CAcrap
(because of its weirdness), look on my website or Google to see it.]

"with GDC, GBW, slew-rate, Rout, phase-margin, and positive and
negative swing limit specifiable... but modified as follows:

Rout => Rout-sourcing, Rout-sinking (separate values)
Current limit sourcing and sinking (separate values)
Power supply pins will reflect load _and_ quiescent currents
Output swing limits specifiable relative to rail potentials

It may even show recovery time from slamming into rails... not quite
sure yet, but I think so :-)"

So do what you want. If you think I give a rat's ass what you do or
think, you're sadly mistaken.

[Lostgallifreyan]

Jim Thompson <To-Email-Use-Th...@On-My-Web-Site.com> wrote in

news:st88j7p1nhamcf5ab...@4ax.com:

Well, I'm going to leave it there. I haven't time or inclination to argue. I
don't understand all that you have said, but I have tried to help my getting
measurements, and I do understand that a model that forever reason generates
impossible voltages is not usable. I asked you several times if you could
help with details I could use to explore the original schematic, and all you
did was give me a model that outputs more energy below its negative rail than
the input could ever feed it, and a claim that the datasheet is lying.

Now, I have no way to judge that last claim, but I do think this effort is on
a hiding to nothing, so I'm quite happy to abandon it now. Thanks for the
effort you put into it. It's good to see anyone have a go, regardless of
outcome.