http://www.analoginnovations.com/SED/ModFilterDesiredShape.pdf
when I input a square wave. Note the smooth start and stop.
Can this be realized with a filter or does it take something more
exotic?
...Jim Thompson

 James E.Thompson, P.E.  mens 
 Analog Innovations, Inc.  et 
 Analog/MixedSignal ASIC's and Discrete Systems  manus 
 Phoenix, Arizona Voice:(480)4602350  
 JimT@analog_innovations.com Fax:(480)4602142  Brass Rat 
 http://www.analoginnovations.com  1962 
For proper Email replies SWAP "" and "_"
I love to cook with wine. Sometimes I even put it in the food.
Does the output amplitude have to be the same as the input, or can it be
clamped first, then processed and output at a constant level?
Lukas Louw
Manchester / 50KHz / 100KHz
It can be clamped or I can provide fixed amplitude.
BTW, I have only 1.8V supply to work with ;)
Jim, multistage linearphase (Bessel) filters with four or more
poles have responses exactly like that. See AoE fig 5.15, p 272.
Thanks,
 Win
Realizability? If you take the ratio of the Fourier transform of the
output (graph) to the input (square wave) and there are more poles
than zeros, doesn't that mean it is realizable?
Ray
There are slight aberrations but the result is pretty close to what
you want.
Here is a 5pole bessel using standard values calculated for a
cutoff frequency of 1MHz (Sorry, this is the lowest frequency my
filter program will go. You can scale the values for 100KHz):
http://www3.sympatico.ca/add.automation/misc/5polesch.gif (4k)
Here's the transient response showing very little overshoot:
http://www3.sympatico.ca/add.automation/misc/5poletra.gif (10k)
Here's the amplitude, group delay and phase response from 100KHz to
10MHz:
http://www3.sympatico.ca/add.automation/misc/5polefre.gif (5k)
The scales are:
red = amplitude (db)
blue = group delay (ns)
black = phase
Cheers, Mike
>I want the following output...
>
>http://www.analoginnovations.com/SED/ModFilterDesiredShape.pdf
>
>when I input a square wave. Note the smooth start and stop.
>
>Can this be realized with a filter or does it take something more
>exotic?
>
> ...Jim Thompson
Agree with Win; this looks awfully Bessel to me.
A simple 2nd order lowpass, active or rlc, would come visually
pretty close. Higher order would look crisper.
Try simulating
in rlout


c

gnd
where c=1 r=1 l~~0.25 or so, tune for beauty.
John
>On Wed, 24 Jul 2002 00:59:37 GMT,
>"Lukas Louw" <luka...@comcast.net>,
>In Newsgroup: sci.electronics.cad,
>Article: <ZZm%8.292049$Im2.14...@bin2.nnrp.aus1.giganews.com>,
>Entitled: "Re: Physically Realizable Filter ??",
>Wrote the following:
>
>Fixed square wave amplitude and/or frequency, or what range, Jim?
>
>Does the output amplitude have to be the same as the input, or can it be
>clamped first, then processed and output at a constant level?
>
>Lukas Louw
>
>> I want the following output...
>>
>> http://www.analoginnovations.com/SED/ModFilterDesiredShape.pdf
>>
>> when I input a square wave. Note the smooth start and stop.
>>
>> Can this be realized with a filter or does it take something more
>> exotic?
>>
>> ...Jim Thompson
>
>
>
>Manchester / 50KHz / 100KHz
>
>It can be clamped or I can provide fixed amplitude.
>
>BTW, I have only 1.8V supply to work with ;)
Hi Jim,
The symmetrical step reponse (= derivative of step response) implies a
filter with a constant group delay. You can't do this exactly with a
finite number of linear analog components.
I guess this is just for improving the spectrum of a line driver used
for data transmission, so the waveform doesn't have to be exactly as
shown in your drawing.
You could try following a slew rate limiter with a single pole LPF.
The slew rate limiter would switch a current source (+/ I) into a
capacitive load. Then use a voltage follower before the RC LPF, and
then follow that with a line driver.
But since you are starting with a digital signal, you could use an FIR
filter which can easily give you a linear phase impulse response.
You don't need to use heavy DSP either.
If you can oversample the incoming data with an N x clock (say, >
1MHz) you can put the data into a serialin, parallelout shift
register. This will give you N data bits, which can be "summed" with
resistors. You can synthesise any impulse response you like by
adjusting the resistor weights. This is a DAC that just happens to
calculate your filter response for you. I guess a talented DAC
designer (not me!) could use weighted capacitors instead of resistors.
There'll be some high frequency noise, but this is easy to get rid of
with a simple analog LPF.
Yes, the LPF will introduce some phase nonlinearity, but you can
compensate for that by adjusting the impulse response of the FIR
filter in the other direction.
Regards,
Allan.
^^^^
Nnggah! That should read:
>The symmetrical impulse reponse (= derivative of step response) ...
Allan.
Umm, when I say things like "linear phase impulse response" I mean
"linear phase" and "symmetric impulse response".
It's too early in the morning for me.
>You don't need to use heavy DSP either.
>If you can oversample the incoming data with an N x clock (say, >
>1MHz) you can put the data into a serialin, parallelout shift
>register. This will give you N data bits, which can be "summed" with
>resistors. You can synthesise any impulse response you like by
>adjusting the resistor weights. This is a DAC that just happens to
>calculate your filter response for you. I guess a talented DAC
>designer (not me!) could use weighted capacitors instead of resistors.
A further clarification:
The "weight" of each resistor is actually its conductance, i.e. 1/R.
NxClk +++
  
v v v
++ ++ ++
 c   c   c 
datad q+>d q+> ... +>d q+
 FF    FF     FF  
++  ++   ++ 
   
R1 R2 RM1 RM
   
++++> out
'M' should be chosen to suit the length of the impulse reponse.
The circuit as described can only synthesise a positive impulse
response. If you want the impulse response to have a negative part
(i.e. if one of the resistors needs to have a negative value), just
invert that output of the shift register (i.e. use the /Q output of
the flip flop).
BTW, the filter in the PDF has an impulse reponse that's about 500us
long. This won't work too well with a 50kb/s Manchester signal.
Regards,
Allan.
> <JimT@analog_innovations.com> wrote:
>
> >On Wed, 24 Jul 2002 00:59:37 GMT,
> >"Lukas Louw" <luka...@comcast.net>,
> >In Newsgroup: sci.electronics.cad,
> >Article: <ZZm%8.292049$Im2.14...@bin2.nnrp.aus1.giganews.com>,
> >Entitled: "Re: Physically Realizable Filter ??",
> >Wrote the following:
> >
> >Fixed square wave amplitude and/or frequency, or what range, Jim?
> >
> >Does the output amplitude have to be the same as the input, or can it be
> >clamped first, then processed and output at a constant level?
> >
> >Lukas Louw
> >
> >> I want the following output...
> >>
> >> http://www.analoginnovations.com/SED/ModFilterDesiredShape.pdf
> >>
> >> when I input a square wave. Note the smooth start and stop.
> >>
> >> Can this be realized with a filter or does it take something more
> >> exotic?
> >>
> >> ...Jim Thompson
> >
> >
> >
> >Manchester / 50KHz / 100KHz
> >
> >It can be clamped or I can provide fixed amplitude.
> >
> >BTW, I have only 1.8V supply to work with ;)
>
> Hi Jim,
>
> The symmetrical step reponse (= derivative of step response) implies a
> filter with a constant group delay. You can't do this exactly with a
> finite number of linear analog components. snip
Hi Jim,
right, a symmetrical response requires a filter of infinite order, but of
course you could do with 6x 2nd order sections with 1/(1+1.82*S+S^2)scaled
to 8*pulse frequency. (Or just 3 sections with 4*pulse f)
looks pretty what you want.
I tried the slew rate limiter, but is assymetrical and makes nasty spikes.
another possibility is a 4th order bandpass(Q=1) followed by a schottky
diode ring limiter, but reqires neg supply.
ciao Ban
p.s. here in Italy finally the summer has come, the mediterranean is just
the right temperature(23°C) and air (29°) is not too hot. It is the flower
Riviera, Italian part of Côte D'Azur. At night you go out for a pizza,
sitting outside on the piazzetta of the old city. Wine is made and drunk(!)
here in the region as well.
Do you need this exact waveform, or are there some actual frequency/phase
specs you have to meet? That may be a more fruitful way of designing the
filter.
Regards,
George

It's to smooth data going into a BPSK/OOK (selectable) modulator to
minimize splatter. I'd like *all* derivatives to be finite ;)
I can visualize a scheme where the slew rate is a function of the
output voltage, but I can't quite seem to get it to work on paper ;)
Once I had pizza for breakfast in Napoli. There was a nice deep lake of
olive oil in the middle of it.
>
> I want the following output...
>
> http://www.analoginnovations.com/SED/ModFilterDesiredShape.pdf
>
> when I input a square wave. Note the smooth start and stop.
>
Is this waveform a digitized record, or do you actually have a
timedomain mathematical description?



>
The emulated waveform was simulated from a PSpice part I made up that
converts a ramp into a sine, so each edge is sineshaped.
Jim Thompson wrote:
>
> On Thu, 25 Jul 2002 15:42:16 GMT,
> Fred Bloggs <nos...@nospam.com>,
> In Newsgroup: sci.electronics.cad,
> Article: <3D401C68...@nospam.com>,
> Entitled: "Re: Physically Realizable Filter ??",
> Wrote the following:
>
> 
> 
> 
> >
> > I want the following output...
> >
> > http://www.analoginnovations.com/SED/ModFilterDesiredShape.pdf
> >
> > when I input a square wave. Note the smooth start and stop.
> >
> 
> 
> Is this waveform a digitized record, or do you actually have a
> timedomain mathematical description?
>
> The emulated waveform was simulated from a PSpice part I made up that
> converts a ramp into a sine, so each edge is sineshaped.
Okay, so the main thing with this "splatter" reduction is to put a
max/min bracket on slew rate through the zero crossing, and to provide a
"smooth" convergence to the peaks at the corners.


Jim Thompson wrote:
>
> On Thu, 25 Jul 2002 15:42:16 GMT,
> Fred Bloggs <nos...@nospam.com>,
> In Newsgroup: sci.electronics.cad,
> Article: <3D401C68...@nospam.com>,
> Entitled: "Re: Physically Realizable Filter ??",
> Wrote the following:
>
> 
> 
> 
> >
> > I want the following output...
> >
> > http://www.analoginnovations.com/SED/ModFilterDesiredShape.pdf
> >
> > when I input a square wave. Note the smooth start and stop.
> >
> 
> 
> Is this waveform a digitized record, or do you actually have a
> timedomain mathematical description?
>
> The emulated waveform was simulated from a PSpice part I made up that
> converts a ramp into a sine, so each edge is sineshaped.

Okay, so the main thing with this "splatter" reduction is to put a
max/min bracket on slew rate through the zero crossing, and to provide a
"smooth" convergence to the peaks at the corners.
Exactly.
Jim,
how much delay can you tolerate from your filter ? Is it an issue ?
I guess it's for integrating, but how far are you ready to go ? What is, if
you can tell, the hardware already present you can modify ? I think of opamp
gain stages or output stages....
What are the real timings ? (I guess the 500Hz freq is not the target, but
for immediate simul)
Fred.
[snip]

Jim,
how much delay can you tolerate from your filter ? Is it an issue ?
I guess it's for integrating, but how far are you ready to go ? What is, if
you can tell, the hardware already present you can modify ? I think of opamp
gain stages or output stages....
What are the real timings ? (I guess the 500Hz freq is not the target, but
for immediate simul)

Fred.

> ...Jim Thompson
The "real" data rate will be 10KHz to 100KHz. I don't think delay
would be an issue.
The real snag in this thing is that I have only a 1.8V supply to work
with. But it's a BiCMOS process... PMOS + NMOS + NPN's with *really*
high fT's... carrier frequency is 1GHz.
I don't understand your objection to a linearphase filter.
Probably a threepole filter would give you an acceptable
waveform and could be implemented with a single opamp.
Thanks,
 Win
Jim wrote ...
I have no objection to a linearphase filter. It's just not the
easiest thing to implement monolithically.... plus you know my disdain
for singleopamp implementations... component sensitivities suck ;)
Hey, they're not so bad for threepole Bessel filters, remember
the offaxis poles are low Q, so the sensitivities aren't bad
for a single VCVS stage (the third pole is on axis).
Furthermore, this is one application where filter precision
isn't important, right?
Thanks,
 Win
>On Thu, 25 Jul 2002 19:01:31 +0200,
>"fred bartoli" <to...@hotmail.toto>,
>In Newsgroup: sci.electronics.cad,
>Article: <3d402ebe$0$454$626a...@news.free.fr>,
>Entitled: "Re: Physically Realizable Filter ??",
>Wrote the following:
>
>[snip]
>
>Jim,
>how much delay can you tolerate from your filter ? Is it an issue ?
>I guess it's for integrating, but how far are you ready to go ? What is, if
>you can tell, the hardware already present you can modify ? I think of opamp
>gain stages or output stages....
>What are the real timings ? (I guess the 500Hz freq is not the target, but
>for immediate simul)
>
>Fred.
>
>> ...Jim Thompson
>
>
>The "real" data rate will be 10KHz to 100KHz. I don't think delay
>would be an issue.
Do you want the edges to have the same shape as the data rate varies,
or do you want them to scale?
Allan.
>On Wed, 24 Jul 2002 00:59:37 GMT,
>"Lukas Louw" <luka...@comcast.net>,
>In Newsgroup: sci.electronics.cad,
>Article: <ZZm%8.292049$Im2.14...@bin2.nnrp.aus1.giganews.com>,
>Entitled: "Re: Physically Realizable Filter ??",
>Wrote the following:
>
>Fixed square wave amplitude and/or frequency, or what range, Jim?
>
>Does the output amplitude have to be the same as the input, or can it be
>clamped first, then processed and output at a constant level?
>
>Lukas Louw
>
>> I want the following output...
>>
>> http://www.analoginnovations.com/SED/ModFilterDesiredShape.pdf
>>
>> when I input a square wave. Note the smooth start and stop.
>>
>> Can this be realized with a filter or does it take something more
>> exotic?
>>
>> ...Jim Thompson
>
>
>
>Manchester / 50KHz / 100KHz
>
>It can be clamped or I can provide fixed amplitude.
>
>BTW, I have only 1.8V supply to work with ;)
Is this to reduce EMI radiation? There are driver IC's available that
produce exactly the waveform you want (LVD drivers).

Bedrijven zoeken en snel vinden? Adresboekje.nl

Doug Dwyer
I want the following output...

http://www.analoginnovations.com/SED/ModFilterDesiredShape.pdf

when I input a square wave. Note the smooth start and stop.

Can this be realized with a filter or does it take something more
exotic?

 ...Jim Thompson
Here's a *very* nice solution that's easy to realize in my BiCMOS
process...
http://www.analoginnovations.com/SED/TransversalFilter4Modulation.pdf
...just a short shift register and some weighted resistors.
Thanks to all of you who mentioned FIR filters and especially to Al
Clark of Danville Signal Processing (http://www.danvillesignal.com)
who called and refreshed some memories from those classes of 40 years
ago ;)
Looks like just half the solution. :) Hmm, you have
a clock with a period ~ 1/16 of your desired risetime?
Also, 1M resistors are easy to realize in your process?
Thanks,
 Win
>Jim Thompson wrote ...
>>
>> Here's a *very* nice solution that's easy to realize in my BiCMOS
>> process...
>> http://www.analoginnovations.com/SED/TransversalFilter4Modulation.pdf
>> ...just a short shift register and some weighted resistors.
>
> Looks like just half the solution. :) Hmm, you have
> a clock with a period ~ 1/16 of your desired risetime?
Neat. The other "half of the solution" is the RC output filter.
(Yes, I know you knew that.)
> Also, 1M resistors are easy to realize in your process?
Since the resistors have a 2^n weighting, I imagine an R2R ladder
could be used, which would avoid the need for high value resistors.
Regards,
Allan.
On 31 Jul 2002 06:37:20 0700, wh...@picovolt.com (Win Hill) wrote:
Win, Allan is correct, although I do have a high resistivity poly
available.
As is my usual method, the first pass is simply a behavioral replica
that I twiddled until I got the generically desired result. Now I'll
go back and scale everything to fit my requirements. It is probable
that the capacitor will be external.
And, yes, I have clocks galore, this chip is a form of cell phone.
Ah. Well, in that case space is probably tight, and you could
eliminate the external cap.
With the current design, the cap performs two functions:
1. Low pass filtering, to remove clock noise.
2. Pulse shaping.
With clocks galore, you could perhaps use a faster one for the shift
register and
1. reduce the size of cap needed to remove the clock noise, and
2. do more of the pulse shaping in the DAC, which reduces the size of
cap needed, and also relaxes the required tolerance of the RC time
constant.
It might be possible to get the cap small enough to put on the die.
[I think the current solution is clever. It reminds me of the old
trick of running a (nonrealtime) signal through a sharp IIR low pass
filter twice  once forward, and once with time reversed, so that the
overall phase response is exactly linear. This is computationally
more efficient than an equivalently sharp FIR filter.]
Currently, the impulse response of the DAC/FIR filter is a truncated
exponential growth:
^
 _



 _

 _
__ ___________
+>t
and the impulse response of the RC filter at the output is a truncated
exponential decay:
^

 .



 .

 .
.. ...........
+>t
The overall response is the convolution of the two, which is nicely
symmetrical if the time constants are matched.
^

 .



 . .

 . .
.. ......
+>t
This is an extreme example of the compenstation mentioned in my first
post in this thread.
... but you could just select the resistors to give this response
directly. Of course, you'll lose the ability to use a regular binary
weighted DAC.
The additional die area needed for the extra resistors (since we have
a higher oversampling ratio) might cost more than the external cap
though.
Regards,
Allan.
Hey, Jim. How about that fred.bartoli.free.fr/SED/Jim_1.pdf ?
The double input stage, with ratioed LPT current will provide you with
current gain on the cap feedback, thus cap reduction. Ratioed current will
ensure consistant freq response versus process variations.
This will probably cost not much in silicon.
Fred.
[snip]
Hey, Jim. How about that fred.bartoli.free.fr/SED/Jim_1.pdf ?

The double input stage, with ratioed LPT current will provide you with
current gain on the cap feedback, thus cap reduction. Ratioed current will
ensure consistant freq response versus process variations.
This will probably cost not much in silicon.

Fred.


Thanks, Fred, I'll give it a study.