Start-up of D-type flip-flop
jonathan mark engel
a flip-flop that has the D input connected to logic 1 (high) and when the
first clock signal comes in will set the output Q high as well. My
problem is ensuring that Q will be low until the first clock pulse. The
time from power up to the first clock pulse is undetermined, and may be
infinite. Ideas? For once, Horowitz and Hill have not been able to help me.
For those interested, this circuit is part of an automotive ignition
system.
Thanks!
-Jonathan Engel
Keith R. Williams
jme...@students.uiuc.edu says...
> How can I ensure the start-up output state of a D-type flip-flop? I have
> a flip-flop that has the D input connected to logic 1 (high) and when the
> first clock signal comes in will set the output Q high as well. My
> problem is ensuring that Q will be low until the first clock pulse. The
> time from power up to the first clock pulse is undetermined, and may be
> infinite. Ideas?
If you can tolerate *some* glitching at the output you can hold the
RESET pin active until power is stable. This is not perfect though
because the output pin may move until the flip-flop is powered up
enough to feed back. In the mean time it's difficult to determine what
the outputs are going to do.
> For once, Horowitz and Hill have not been able to help me.
This isn't an easy thing to design and is very sensitive the particular
circuit in use. Your needs will dictate the care that must be taken.
> For those interested, this circuit is part of an automotive ignition
> system.
>
> Thanks!
Good luck.
--
Keith
ånønÿmøu§
<jme...@students.uiuc.edu> wrote:
>How can I ensure the start-up output state of a D-type flip-flop? I have
>a flip-flop that has the D input connected to logic 1 (high) and when the
>first clock signal comes in will set the output Q high as well. My
>problem is ensuring that Q will be low until the first clock pulse. The
>time from power up to the first clock pulse is undetermined, and may be
>infinite.
different ways to create them. If you want, I can post some examples
for you.
>Ideas? For once, Horowitz and Hill have not been able to help me.
>For those interested, this circuit is part of an automotive ignition
>system.
reset). This insures that they will come up in a known state.
jonathan mark engel
stand-alone POR IC's. Sometimes it is impossible to find what you want
when you don't know what to call it. I think this will work fine, I can
use the POR signal as the clear input to the D flip-flop.
Jon
Charles Jean
you know where you're starting from. Sometimes it's also nice to have
a manual reset button to reset the system if something goes awry.
That familiar beep you hear when you turn on the power switch to your
computer indicates that power has been good enough long enough to
generate a system reset pulse. Everything initializes, including the
microprocessor. Whenever it senses the reset pulse, it starts to
execute the program located at XXXX address, which resides on your
CMOS BIOS chip, which eventually loads in the operating system. If
your operating system is Windows and you later wind up with the Blue
Screen of Death, you can press your manual reset button to get things
started again!
_________
The reasonable man adapts himself to the world; the unreasonable one
persists in trying to adapt the world to himself. Therefore all progress depends on the
unreasonable.
- George Bernard Shaw (1856-1950)
John Fields
<jme...@students.uiuc.edu> wrote:
>How can I ensure the start-up output state of a D-type flip-flop? I have
>a flip-flop that has the D input connected to logic 1 (high) and when the
>first clock signal comes in will set the output Q high as well. My
>problem is ensuring that Q will be low until the first clock pulse. The
>time from power up to the first clock pulse is undetermined, and may be
>infinite. Ideas? For once, Horowitz and Hill have not been able to help me.
---
The easiest way is to connect one end of a resistor to Vcc and the other
end to the free terminal of a grounded capacitor, then connect the
junction of the RC to the low true RESET input of the Dflop. If you're
using a device with a high true RESET, like a 4013, reverse the Vcc and
ground connections to the RC.
You may get a glitch out of Q when power is first applied, but it will
go away and Q will remain low until you send your clock to the Dflop.
Skipp
all I need to ensure my cmos circuits restart properly. In some
applications, I also might include a diode to discharge the cap.
Use the circuit as he describes it. If you are using cmos chips, I can
provide the part values. Maxium has good stuff, but sometimes you can
replace a chip with two or three parts.
cheers
skipp
http://sonic.ucdavis.edu
: jonathan mark engel <jme...@students.uiuc.edu> wrote:
: How can I ensure the start-up output state of a D-type flip-flop? I have
jonathan mark engel
type flip flop, and when I power on the circuit the output Q always takes
the value D regardless of the clock. This is not desirable, since I need
the circuit to wait for the clock before setting the output to D.
I have an RC circuit (as described below) to hold the CLR pin low for the
few ms that the cap takes to charge but the output goes to D (high)
anyway. If I start the circuit up with D low, then Q stays low on power
up. Ideas? I ordered a POR IC but it has not arrived. The RC should
work, but what is the problem?
Thanks!
-Jon
John Fields
<jme...@students.uiuc.edu> wrote:
>I tried the below, and I am having trouble. I am using a 74LS74 dual D
>type flip flop, and when I power on the circuit the output Q always takes
>the value D regardless of the clock. This is not desirable, since I need
>the circuit to wait for the clock before setting the output to D.
>
>I have an RC circuit (as described below) to hold the CLR pin low for the
>few ms that the cap takes to charge but the output goes to D (high)
>anyway. If I start the circuit up with D low, then Q stays low on power
>up. Ideas? I ordered a POR IC but it has not arrived. The RC should
>work, but what is the problem?
---
I suspect a glitch on the clock line after CLEAR goes high. Also, make
sure that PRESET goes to Vcc and that the time constant of the RC is
substantially (10 times?) greater than the power supply rise time.