Serials World Portable V. 3.2.2.029 Download
Alesha Canant
This means that I in general can talk to the port that appears in /dev most often as /dev/ttyUSB1 but at times under different number, so the problem is different from just being unable to get serial port working.
I have created the "Base Zynq" project with Vivado, generated bitstream without any changes to it, exported (Export hardware, include bitstream) and opened SDK using Vivado menu commands under "File" group. In SDK, I asked to create a new application project, standalone platform, "Hello world". I have selected "Program device" in SDK and passed this step without any obvious errors, with progress bar gradually moving as device is programmed. Also, Vivado shows the device temperature correctly.
I noticed that when I do the device programming, the demo LEDs stop flashing in all colors. Only red LD13, green LD12 and green LD4 remain on. However when I attempt to run the project from SDK, multiple LEDs start flashing again, indicating that probably a reset has happened. At this point the "Zybo Z7-20 Rev B Demo Image" appears on the SDK terminal (115200 bauds) , so the terminal in general works. Looks like another "debug terminal" for two cores opens in SDK (TFC Debug Virtual Terminal cores 1 and 0) at this point but also remains empty. I have tried to change the stdout in BSP settings, but switching between "ps7_uart_1" and "ps7_coresight_com" results no changes in behavior.
I also tried to flash the bitstream from Vivado directly but this did not change anything. I have no problems in getting the output from KCU116 Microblaze after the similar sequence of actions but this is on another host (Window 7).
I attach SDK logs and synthesis logs. Board files I have downloaded from -boards/archive/master.zip. After installing as described in -vivado/start I was able to find and select the Zybo Z7 - 20 after restarting Vivado.
Last think I tried was connecting the pin aux_reset_in of the block rst_ps7_0_50M to constant value 1 in Vivado designer. It looks like reset signal with active low, so, thought, maybe not a good idea to left hanging as it is initially created. Yet was not helpful.
Summarizing, looks like the demo image boots, and the card can be accessed and programmed by Xilinx tools, also serial port works, but the "Hello world" from SDK does not run at all or crashes immediately after start.
Please run my verified hello world project here since you are able to get USB UART communication through the OOB Demo but not through your hello world project. Make sure that you have correctly installed the Digilent Board files as described here. Were you able to see information in the serial emulator when you press a button? Does the switches turn on the corresponding LED? I have attached some screen shot of my project and the tera term output. Once you have launched SDK with this Vivado 2018.3 Zybo-Z7-20 project program the fpga and then right click on the application and select run as->Launch on hardware(system debugger). Make sure the mode Jumper JP5 is set to JTAG.
We provide board files for our boards to assist with constraining some of the components like the USB UART bridge as well as the DDR. You need to use a xdc file to constrain the UART_O_0_rxd and the UART_O_0_txd signals to specific pins on your development board.
I have not worked with the SmartLynq Data Cable. With that being said I would suggest to make sure that ribbon cable is connected correctly on board and that you have the correct JTAG clock frequency. I would suggest reaching out to xilinx support. Hopefully one of the more experienced community members will have some input for you. Here is a xilinx forum thread that might be helpful.
and Generate succesful bitstream.
Then opened SDK and get problem in downloading code to fpga (clicked PROGRAM FPGA in SDK) - i show image.
SDK don't see FPGA (((
(I give rar of my project HLS + SDK )
What do you phink about connecting to FPGA?
Best regards
There is a few thing that must be done to send data through the UART with a ZYNQ processor. Unfortunately we do not have the bandwidth or your development board to create a completed UART project for this board.
1) You will need to correctly configure the ZYNQ processor. I would look at the Zynq-7000 SoC Technical Reference Manual. You can also look at our ZYNQ development board's board files and schematics as a reference.
I would suggest looking at the schematic here for the pins that you will need to use in your XDC. This here might be the E310 XDC. I would suggest reaching out to ettus about resources for their board.
I have ettus e310 board. I decided do not use the USRP, GNU Radio and start to program FPGA on board via Vivado - this decision is better for me. When i start to work with board, i could not create true file for write inside the chip((
Early i have worked with arty A7 board and programmed it via Vivado.
Now i have get another board with Zynq 7020 and i start to write code in vivado - it is not Digilent board (its is very bad(( and hard to start for me ) .
I choose my chip in vivado and combinated IP blocks. I want at first step to make transmitting "Hello world" to PC. But, after generating bitstream i have get errors, i don't understand hove to fix tham((
Digilent has board files that correctly configures the ZYNQ processor along with the DDR3. Here are the tutorials that we have available Getting Started with the Vivado IP Integrator, Getting Started with Vivado, Installing Vivado and Digilent Board Files and Getting Started with Digilent Pmod IPs. I will pass on your desire for more information on the Zynq core, AXI interconnect, GPIO, proc reset IP Cores to our content team although I believe that currently we do not have the bandwidth to create tutorials for how to edit properties of the Zynq core, AXI interconnect, GPIO and the process reset IP Cores.
I would suggest looking through the Zynq-7000 SoC Technical Reference Manual, AXI Interconnect v2.1 LogiCORE IP Product Guide, Processor System Reset Module v5.0 LogiCORE IP Product Guide and AXI GPIO v2.0 LogiCORE IP Product Guide. Xilinx does have a lot of documentation/examples on how to use their IP Cores available from the block design by right clicking on the IP.
I would also suggest looking here (if you used the default installation path): " C:\Xilinx\SDK\2018.3\data\embeddedsw\XilinxProcessorIPLib\drivers" for examples on how to uses their IP Cores in SDK. The ZYNQ book is also a good source of information as well.
Dir "jpeyron" there is a picture in your answer of block design for Zynq ("hello world" generate example). But you wrote, that you used vivado 2018.3.
I use vivado 2017.4, when i connect block like in your picture and start "implementation" - all be ok. When start "generate bit stream" - i get error.
Could you give more pictures that explain how to edit properties of each blocks of that (Zynq core, AXI interconnect, GPIO, proc reset) ???
I'm glad you were able to get the project working! I made the project based an older getting started with ZYNQ tutorial for the Zybo here. You should be able to create your own project following this tutorial as well. I would also suggest making sure you have the digilent board files installed correctly as shown in this tutorial here.
Well, initially the SDK was showing me the messages about some wrong executable selected for download (attached). However then I have removed the folder GSWZ_2018_3_ZYBO_Z7_20.sdk, repeated all steps of creating the bitstream in Vivado starting from synthesis and exported hardware again, it unexpectedly worked, showing "Hello world" on the tty output as if nothing. It even works with JP5 in the middle QSP1 position. I also was able to get the "Hello world" easily on TFC Debug virtual terminal.
I did not change anything in my board files or system configuration. Also, yesterday evening I brought Zybo Z7 to my Windows 7 workstation and repeated all steps there, reproducing essentially the same behavior. Probably Vivado 2018.3 cannot create a working "Base Zynq" project for Zybo Z7 from scratch, even with the board files provided. However now I can use your reference project as a starting point, by adding my AXI modules there.
Ok I have installed Adept 2, here is the output on the command you asked and also another that may be useful. I think I have already installed the drivers before but anyway I have verified everything again step by step, the log is attached. I have freshly exported hardware from Vivado to make sure the code in SDK has no any of my alterations.
In linux the cable drivers need to be installed manually. Here is an Xilinx AR that discusses this. Also install Adept 2 here and run djtgcfg enum in the command line. Please attach the terminal text response to the djtgcfg enum command.
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