Verification Engineer (Specman, System Verilog, OVM, RTL)

[brijen...@gmail.com]

Verification Engineer (Specman, System Verilog, OVM, RTL)

 

Requirements:

• Experience in RTL verification
• Expertise in Building scalable HVL based verification environment for processor based SoC from Scratch using System Verilog
• Good experience in System Verilog – OVM based verification environment development
• Sound understanding of Random and constrained random-verification concepts
• Experience with assertion based verification would be a plus

Job Description:

• Driving the verification environment architecture
• Creating test scenarios(System Verilog OVM)
• Work with RTL teams to debug verification failures
• Review and ensure that expected Code and functional coverage metrics are achieved

Desired Skills & Experience

• Verification experience in Specman or SV-OVM
• Experience in development of Verification environment / TB
• Working experience with ARM based processor for Image processing
• Must have work from Spec to Implemetation
• Must have worked through all the phases of verification including coverage and GLS

Hiring Prime: Brijendra Rao