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Important: If you have any questions or would like to report any issues with the DDR tools or supporting documents please create a support ticket in the i.MX community. Please note that any private messages or direct emails are not monitored and will not receive a response.

The i.MX6/7 DDR Stress Test Tool is a PC-based software to fine-tune DDR parameters and verify the DDR performance on a non-OS, single-task environment(it is a light-weight test tool to test DDR performance). It performs write leveling, DQS gating and read/write delay calibration features.

The purpose of the i.MX 6/7 series DDR Tools is to enable users to generate and test a custom DRAM initialization based on their device configuration (density, number of chip selects, etc.) and board layout (data bus bit swizzling, etc.). This process equips the user to then proceed with the bring-up of a boot loader and an OS. Once the OS is brought up, it is recommended to run an OS-based memory test (like Linux memtester) to further verify and test the DDR memory interface.

There are three options to run the DDR Stress test. Each of these options are provided in the attached zip files. The following is a high-level overview of each option along with the naming convention of the associated zip file:

A hardware debugger connected to the board via the JTAG interface is used to download an elf file into the i.MX SoC OCRAM (internal RAM) and then begin execution. Results are shown on the UART serial port (115200-8-n-1).

Newer versions on u-boot do not allow a direct loading of the DDR stress test code from the SD card (boot media) directly to the SoC internal OCRAM (aka IRAM). Hence, the procedure is updated to first load the DDR stress test code into DDR and then copy into OCRAM, as shown in the procedure below:

As u-boot initializes many peripherals that may conflict with the operation of the DDR stress test, it is necessary to clock gate these peripherals prior to running the DDR stress test. Hence, it is highly recommended to augment the procedure above as follows:

A. Sometimes, when using the register programming aid, there are registers writes that are not supported in the DCD range. Try looking for the following items and comment them out from the DDR initialization script:

A. The DDR Density pull-down menu gives the user the option of testing a DDR density smaller than what they actually have on their board. The advantage of doing this is to speed up test time to allow the user to perform a "quick test" of their system. IMPORTANT: it is imperative that the user not set this value higher than the supported density on their board, doing so will cause the stress test to fail and/or lock up.

A. Yes, calibration is not supported or needed when using MX7. The reason is, MX7 uses a different memory controller than the MX6 series. The MX6 series memory controller has built-in support for calibration where the MX7 memory controller does not.

A. This is due to the fact that MX7 uses a different memory controller than the MX6 series. In the MX6 series, it was possible to calculate the memory density from the memory controller register settings. The MX7 memory controller is different and does not lend itself to easily calculate the supported density based on the register settings. Instead, the user should verify the density on their board and selected this value in the DDR Density pull-down menu.

Q. I noticed that when I run write-leveling calibration I sometimes see a note that due to the write-leveling calibration value being greater than 1/8 clock cycle that WALAT must be set to 1. What does this mean?

Therefore, if the write-leveling calibration routine detects any write-leveling delay value greater than 0x1F, it will note to the user that WALAT must be set and the user should update their DDR3 init script to ensure WALAT is set. Sometimes, a user may find that the write-leveling delay value may fluctuate from one run to the next, which is quite normal. If it is found that this delay is "borderline" meaning sometimes it is greater than 0x1F and sometimes it might be slightly less, then it is ok to go ahead and set WALAT permanently in your init script as there is no harm in doing so and will ensure you will stay within JEDEC's tWPST.

A. Under the folder ddr_stress_tester_jtag_v2.52, there's a text file that describes how to add a different UART port by adding a few additional commands to your DDR init script. The following is an outline of these commands:

, but testing this script with u-boot needs script transformation to DCD and rebuilding. I takes too much time. We are wondering that can we able to test LPDDR script( output of i.Mx6DQSDL LPDDR2 Script Aid ) with i.MX6/7 DDR Stress Test Tool V2.00 tool?

There is no script file need if you are use u-boot, because u-boot can initial DDR controller itself. You can modify u-boot to initial DDR controller registers. If u-boot can access DDR memory correctly, we can assume the value you write to DDR controller is OK.

Did you use DDR stress tester tool V1.03 or earlier version with the same script? If you get good result by the older version, I think there are some bugs in V2.00. If not, I think you have a incorrect initial script and i.MX6DL hung up.

if the target chip is i.MX6UL, ARM speed options are 800MHz, 1GHz and 1.2GHz still. But, Cortex A7 ARM in i.MX6UL operates of speeds up to 528Mhz only. We cannot find the such option in V2.00 tool. I suggest all available options should be limited to target i.MX selection.

1. In our old version DDR Stress Test tools (V2.10 and V1.03 or other old version), there is DDR precharge command issue when switch DDR frequency. So you've found problem in frequency sweep from 360Mhz to 440Mhz.

3. About V2.10 freeze issue, I want to know the exact "freeze" meaning. It means the Software GUI show "Application is Not respond"? Or there is no message output and all the buttons ares disabled? If it is the latter, I think the board is hung, not the GUI application is freeze.

Is there any reason why a board that passes the V1.0.3 test would fail the V2.20 test? I have boards that have passed several hundred loops and several runs through the V1.0.3 tester fail the DQS Gating Calibration every time on V2.20. Is it more intensive and thus able to find problems better? For reference I tried using the same calibration file in both versions.

Thank you for your response and for the new version of the tool. I can confirm that we no longer have any issue when running v2.20 of the stress test tool. We have run frequency sweeps all day. There is no freeze when switching between frequencies anymore.

Regarding your question what a "freeze" really means; we run the over-night test and there is no way to stop that test in v2.10 other than closing the PC GUI application. The "freeze" that we reported means that the output in the terminal window stopped (at the point when the frequency should change). Since the PC GUI application is designed as it is in v2.10 it is not possible for us to determine if it is the PC application or CPU that has frozen, but if I understand you correctly we should have received a message "Application not responding" from Windows if the PC GUI application had frozen... so likely it was the CPU that was frozen then.

Stress Test tool V2.10 waits for test OK or test fail information and then enable all buttons. If i.MX cpus hangs and doesn't send back the response, GUI application will wait forever. It isn't program freeze, but some problem in board.

I got the same problem as Craig mentioned on Sep 22. My DRAM script is for i.MX6DL LPDDR2 single channel fixed mapping. It passed several hundred loops in stress test tool v1.0.3 but it can't even pass one loop in v.2.2 at the same DDR frequency.

I think that this tool now supports downloading the stress test via JTAG. Looks like there is a zip file called "ddr_stress_tester_jtag_v2.30.zip". I extracted that contents and found an elf file called "ddr-test-uboot-jtag-mx6dl.elf". Though it has "u-boot" in the name, I believe it can be used as a JTAGA downloadable elf. It also seems important to read the text file "add_uart_support_in_script.txt" - it seems to contain important information to configuring the JTAG DDR initialziation script to allow you to choose the desired UART port.

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