LimeSDR FPGA operation and fan testing. Formerly "The LimeSDR is over" [not really].
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David Fields
Dec 12, 2016, 6:17:00 PM12/12/16
to marioca...@gmail.com, oxl...@att.net, tony....@gmail.com, RA...@yahoogroups.com, sara...@googlegroups.com
HI Mario and everyone,
I'm really happy that you spoke up, since I remember your interest a few months ago in programming the LimeSDR FPGA. Did you hear more from Andrew, or perhaps contact Ian?
Anyway, you were looking into doing some of the FFT processing in the FPGA so that you could send the output to an RPi, rather than use a powerful back end computer as the RASDR approach usually entails. This could be very useful.
One of my desires is to have RASDR identify significant events and raise an alert flag that would initiate some very useful actions. Tony has been working on this.
So if your idea of making the FPGA work for a living then maybe a small radio head can be the radio observatory and let us distracted humans know when a significant event (pulse, or other signal detection) has occurred.
Please let us know how your FPGA work is progressing. Maybe you can help us on the FPGA programming.
Another topic I'd like to ask about (assuming that you have an early release LimeSDR) concerns the FPGA and fan contingencies: For safety, we designed in a fan option for our RASDR Enclosure, and Paul did temperature measurements with various configurations. The fan is auto-triggered by the LimeSDR board. But we have not heavily exercised the FPGA yet. Do you know of a procedure to exercise the FPGA under heavy use, so we can identify possible heating effects? Or, if you know the current LimeSDR use with and without heavy FPGA use, that's useful too
For that matter, do you know of a test function for the fan, just to verify automatic fan operation and software logic without heating the board?
Cheers,
David Fields
I'm really happy that you spoke up, since I remember your interest a few months ago in programming the LimeSDR FPGA. Did you hear more from Andrew, or perhaps contact Ian?
Anyway, you were looking into doing some of the FFT processing in the FPGA so that you could send the output to an RPi, rather than use a powerful back end computer as the RASDR approach usually entails. This could be very useful.
One of my desires is to have RASDR identify significant events and raise an alert flag that would initiate some very useful actions. Tony has been working on this.
So if your idea of making the FPGA work for a living then maybe a small radio head can be the radio observatory and let us distracted humans know when a significant event (pulse, or other signal detection) has occurred.
Please let us know how your FPGA work is progressing. Maybe you can help us on the FPGA programming.
Another topic I'd like to ask about (assuming that you have an early release LimeSDR) concerns the FPGA and fan contingencies: For safety, we designed in a fan option for our RASDR Enclosure, and Paul did temperature measurements with various configurations. The fan is auto-triggered by the LimeSDR board. But we have not heavily exercised the FPGA yet. Do you know of a procedure to exercise the FPGA under heavy use, so we can identify possible heating effects? Or, if you know the current LimeSDR use with and without heavy FPGA use, that's useful too
For that matter, do you know of a test function for the fan, just to verify automatic fan operation and software logic without heating the board?
Cheers,
David Fields
-----Original Message-----
From: Mario Cannistrà marioca...@gmail.com [RASDR] <RA...@yahoogroups.com>
To: sara-list <sara...@googlegroups.com>
Cc: rasdr <ra...@yahoogroups.com>; oxleys <oxl...@att.net>; tony.bigbee <tony....@gmail.com>
Sent: Mon, Dec 12, 2016 5:51 pm
Subject: [RASDR] Re: [SARA] Re: The LimeSDR is over.
From: Mario Cannistrà marioca...@gmail.com [RASDR] <RA...@yahoogroups.com>
To: sara-list <sara...@googlegroups.com>
Cc: rasdr <ra...@yahoogroups.com>; oxleys <oxl...@att.net>; tony.bigbee <tony....@gmail.com>
Sent: Mon, Dec 12, 2016 5:51 pm
Subject: [RASDR] Re: [SARA] Re: The LimeSDR is over.
Hello Dave, Paul, David, all.
I've just read this thread but I'm currently travelling.
Tomorrow I should have some time to reply with some thoughts and the notes I collected during last few months on the FPGA topic.
Kind regards,
Mario
On Sun, Dec 11, 2016 at 10:34 PM, 'David Fields' via Society of Amateur Radio Astronomers <sara...@googlegroups.com> wrote:
Hi Dave,
The RASDR team has been working with one of the older versions of the LimeSDR, but awaiting delivery of 4 new LimeSDR units (ver. 1.4). We've done preliminary things, made some software changes, evaluated operating temp under various conditions (different functionality and bareboard vs encased with convection vs forced air cooling. But nothing yet with the FPGA except 'standard' loads.
The temperature control turns out to be important, so we designed a well-shielded case with significant convection cooling, plus it accommodates an optional small fan. People who use RASDR4 (the LimeSDR and radio astronomy software) will not need a fan if they operate in a comfortable air conditioned room. But outside, or in the sun, I fan will be a good idea. Board temp is monitored and the fan is controlled by software. We'll make a kit of cases, the first ones available only to SARA members, and anyone who buys one is expected to be a member of SARA.
Back to the FPGA -- it's a really neat piece of hardware. We have board ver.1.2 but Lime will probably ship ver.1.4, so we'll have a lot of people with the same hardware. We need to find people who will work on new FPGA loads, work with us for new radio astronomy applications, etc.
I'll send in our report (tomorrow) for the SARA Journal. We're actually ready to announce our web site to describe what we have, except that it's not 'pretty' yet.
Oops -- where did that photo come from? All that stainless steel panel needs is a nice anodized Al case to go with. I expect that the back panel is also nice.
David Fields
RASDR team
-----Original Message-------
From: Dave <da...@dtaviation.com>
To: Society of Amateur Radio Astronomers <sara...@googlegroups.com>
Cc: mariocannistra <marioca...@gmail.com>; rasdr <ra...@yahoogroups.com>; oxleys <oxl...@att.net>
Sent: Sun, Dec 11, 2016 12:03 pm
Subject: [SARA] Re: The LimeSDR is over.
Is anyone here aware of open source FPGA code for the Cyclone for sophisticated RA applications such as PFB? An example would be CASPER, although they use Xilinx. I've found papers, but no code, with maybe one exception (I know nothing about FPGAs):--
- A Scalable Correlator Architecture Based on Modular FPGA Hardware and Data Packetization
- A FPGA BASED SPECTRAL LINE AND PULSAR OBSERVING SYSTEM FOR RADIO ASTRONOMY (thesis)
- Implementing super-efficient FFTs in Altera FPGAs, links to a download with Altera Quartus project files, maybe something there
- 16-point Discrete Fourier Transform based on the Radix-2 FFT algorithm implemented into Cyclone FPGA as the UHERC trigger for horizontal air showers
On Wednesday, June 22, 2016 at 10:43:50 AM UTC-4, Paul Oxley wrote:Mario
No, the FPGA load at present is what Lime provided. For the receive direction, I think that it just forwards the bits to the USB. The transmit direction requires a store and forward due to the need to align the clock.
The FFT is calculated in the software. It is very efficient in this application. Since some of the needs (i.e. continuum) don't require a FFT, the system needs to be able to use the raw samples.
The most pressing need for FPGA code is to be able to use the GPIO pins. If we had a FPGA load with the ability to set or read the 8 GPIO pins via a command, we could implement the GPIO feature by a modification to the GUI for user access. This would allow the user to do things such as switch antennas or Dickie Switching.
Paul
From: Mario Cannistrà <marioca...@gmail.com>
To: Society of Amateur Radio Astronomers <sara...@googlegroups.com>
Cc: ra...@yahoogroups.com; oxl...@att.net
Sent: Wednesday, June 22, 2016 2:52 AM
Subject: Re: The LimeSDR is over.
Hello Paul.About the Firmware (FPGA) topic, is the rasdr team already developing (or has already developed) FFT code to run onboard (inside the LimeSDR FPGA) so that just the power spectrum data can be transferred to a PC (or Raspberry-PI) instead of moving the whole IQ data to do that on a PC like we have been doing until now ?mario
On Wednesday, June 22, 2016 at 2:21:32 AM UTC+2, Paul Oxley wrote:Potential RASDR4 usersThe LimeSDR Crowd Funding campaign is over. They raised 122% of the goal of $500,000. Therefore, the boards will be in production.If you look at the Crowd Funding site now, you will see that you can still buy a board for $289.00 which is $10 less than expected. The CEO of Lime previously stated that they would offer the board for $299 for a year unless they could see a larger market. Apparently they saw a larger market and have reduced the price to $289.00We will be looking for help delivering the rest of RASDR4. This will include software (Windows and Linux), Firmware (FPGA), the enclosure, potential expansion boards, Documentation (Users Guide) and other tasks such as distribution. If anyone wants to be involved let any of the RASDR team know.Paul
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Paul Oxley
Dec 12, 2016, 7:09:30 PM12/12/16
to RA...@yahoogroups.com, marioca...@gmail.com, tony....@gmail.com, sara...@googlegroups.com
Mario & David
The following FPGA code modifications are needed for the RA application:
1. Add the capability of setting and reading the GPIO pins on the FPGA via a command on the USB control channel.
2. Make sure the raw I & Q samples are forwarded undisturbed by any LTE logic. Provide the commands to start and stop the sampling.
3. Provide the means to obtain the RSSI data for use as a total power data stream. The integration period of the RSSI should be settable by the software. It appears that most of this function is in the logic in the TSP on the Lime chip. This provides a valuable method of observing objects using the drift scan method. It will avoid the necessity of doing the integration in the software for the total power data.
4. A sample counter would be useful to determine and synchronize data. Accurate timing can be obtained from the counter for a known accurate sample rate.
Some of these requests may already be in the firmware. However, the documentation is lacking for developing the software interface to these capabilities.
I don't see the need to do the FFT on the FPGA. The software method works well and is fast. It even works on David's old computers with a USB2 interface.
Paul
From: "David Fields fiel...@aol.com [RASDR]" <RA...@yahoogroups.com>
To: marioca...@gmail.com
Cc: oxl...@att.net; tony....@gmail.com; RA...@yahoogroups.com; sara...@googlegroups.com
Sent: Monday, December 12, 2016 6:16 PM
Subject: [RASDR] LimeSDR FPGA operation and fan testing. Formerly "The LimeSDR is over" [not really].
Have you tried the highest rated email app?
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David Fields
Dec 12, 2016, 7:51:25 PM12/12/16
to oxl...@att.net, tony....@gmail.com, sara...@googlegroups.com, RA...@yahoogroups.com, marioca...@gmail.com, ia...@ionconcepts.com
Paul, Mario, and all,
It even works on David's old computers with a USB2 interface.
Yeah, I tried 3 upgrades to USB3 for my old XP laptop and they didn't work when installed. Something about those initial chipsets perhaps, or maybe it was more a speed issue. Anyway with the Win7 laptop, I could operate a long time taking data at USB2 speeds. We still had an averaging issue, and didn't use all our collected data.
Mario wasn't trying to do all the things that we want in RASDR4. He was thinking of a standalone radiohead (I think he called it way back in June) with the LimeSDR containing a hard-working FPGA connected to an RPi. This is different from the RASDR4 code mod #2 -- what we want to do with RASDR4 is easier for us (I think) since we dump the I and Q to the backend computer. But if he (or Ian) can help with the FPGA, then we can do a lot more.
Mario wasn't trying to do all the things that we want in RASDR4. He was thinking of a standalone radiohead (I think he called it way back in June) with the LimeSDR containing a hard-working FPGA connected to an RPi. This is different from the RASDR4 code mod #2 -- what we want to do with RASDR4 is easier for us (I think) since we dump the I and Q to the backend computer. But if he (or Ian) can help with the FPGA, then we can do a lot more.
I want to introduce our problem with the RASDR4 User Manual. We need one and can start to write it. The RASDR2 User Manual contained a lot of experience. The first RASDR4 User Manual will initially be hints and initial setup -- virtually no experience since our little group shares one ver. 1.2 board. Yes, we'll need an FPGA discussion and a TSP discussion -- a lot of things. We need more people writing.
David
[[adding Ian to the email chain, since perhaps this will be mutually enjoyable]]
David
[[adding Ian to the email chain, since perhaps this will be mutually enjoyable]]
-----Original Message-----
From: Paul Oxley <oxl...@att.net>
To: RASDR <RA...@yahoogroups.com>; mariocannistra <marioca...@gmail.com>
Cc: tony.bigbee <tony....@gmail.com>; sara-list <sara...@googlegroups.com>
Sent: Mon, Dec 12, 2016 7:09 pm
Subject: [SARA] Re: [RASDR] LimeSDR FPGA operation and fan testing. Formerly "The LimeSDR is over" [not really].
From: Paul Oxley <oxl...@att.net>
To: RASDR <RA...@yahoogroups.com>; mariocannistra <marioca...@gmail.com>
Cc: tony.bigbee <tony....@gmail.com>; sara-list <sara...@googlegroups.com>
Sent: Mon, Dec 12, 2016 7:09 pm
Subject: [SARA] Re: [RASDR] LimeSDR FPGA operation and fan testing. Formerly "The LimeSDR is over" [not really].
Mario & David
The following FPGA code modifications are needed for the RA application:
1. Add the capability of setting and reading the GPIO pins on the FPGA via a command on the USB control channel.
2. Make sure the raw I & Q samples are forwarded undisturbed by any LTE logic. Provide the commands to start and stop the sampling.
3. Provide the means to obtain the RSSI data for use as a total power data stream. The integration period of the RSSI should be settable by the software. It appears that most of this function is in the logic in the TSP on the Lime chip. This provides a valuable method of observing objects using the drift scan method. It will avoid the necessity of doing the integration in the software for the total power data.
4. A sample counter would be useful to determine and synchronize data. Accurate timing can be obtained from the counter for a known accurate sample rate.
Some of these requests may already be in the firmware. However, the documentation is lacking for developing the software interface to these capabilities.
I don't see the need to do the FFT on the FPGA. The software method works well and is fast. It even works on David's old computers with a USB2 interface.
Paul
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Paul Oxley
Dec 12, 2016, 8:02:51 PM12/12/16
to RA...@yahoogroups.com, tony....@gmail.com, sara...@googlegroups.com, marioca...@gmail.com, ia...@ionconcepts.com
DAvid
You mentioned fan testing in the subject line, but not in the text. There is a need for a FPGA command to turn on/off the fan for testing. The temperature sensor and driver for the fan all are on FPGA pins. The test is needed to avoid the need to elevate the board temperature to verify that the fan is operating.
Paul
To: oxl...@att.net
Cc: tony....@gmail.com; sara...@googlegroups.com; RA...@yahoogroups.com; marioca...@gmail.com; ia...@ionconcepts.com
Sent: Monday, December 12, 2016 7:51 PM
Subject: Re: [SARA] Re: [RASDR] LimeSDR FPGA operation and fan testing. Formerly "The LimeSDR is over" [not really].
Cc: tony....@gmail.com; sara...@googlegroups.com; RA...@yahoogroups.com; marioca...@gmail.com; ia...@ionconcepts.com
Sent: Monday, December 12, 2016 7:51 PM
Subject: Re: [SARA] Re: [RASDR] LimeSDR FPGA operation and fan testing. Formerly "The LimeSDR is over" [not really].
.
__,_._,___
David Fields
Dec 12, 2016, 9:26:09 PM12/12/16
to sara...@googlegroups.com, RA...@yahoogroups.com, tony....@gmail.com, marioca...@gmail.com, ia...@ionconcepts.com
Paul,
The subject line started today at 6:16 PM, about 3h ago, and we've kept it. Those subject lines have longevity! Anyway, that's where the fan was first mentioned.
You have a good idea: We could use the FPGA to do a startup test, which would cycle the fan. If anyone wonders what Paul and I are referring to, see the RASDR article in the coming SARA Journal.
David
The subject line started today at 6:16 PM, about 3h ago, and we've kept it. Those subject lines have longevity! Anyway, that's where the fan was first mentioned.
You have a good idea: We could use the FPGA to do a startup test, which would cycle the fan. If anyone wonders what Paul and I are referring to, see the RASDR article in the coming SARA Journal.
David
-----Original Message-----
From: Paul Oxley <oxl...@att.net>
To: RASDR <RA...@yahoogroups.com>
Cc: tony.bigbee <tony....@gmail.com>; sara-list <sara...@googlegroups.com>; mariocannistra <marioca...@gmail.com>; ianb <ia...@ionconcepts.com>
Sent: Mon, Dec 12, 2016 8:02 pm
Subject: Re: [SARA] Re: [RASDR] LimeSDR FPGA operation and fan testing. Formerly "The LimeSDR is over" [not really].
From: Paul Oxley <oxl...@att.net>
To: RASDR <RA...@yahoogroups.com>
Cc: tony.bigbee <tony....@gmail.com>; sara-list <sara...@googlegroups.com>; mariocannistra <marioca...@gmail.com>; ianb <ia...@ionconcepts.com>
Sent: Mon, Dec 12, 2016 8:02 pm
Subject: Re: [SARA] Re: [RASDR] LimeSDR FPGA operation and fan testing. Formerly "The LimeSDR is over" [not really].
DAvid
You mentioned fan testing in the subject line, but not in the text. There is a need for a FPGA command to turn on/off the fan for testing. The temperature sensor and driver for the fan all are on FPGA pins. The test is needed to avoid the need to elevate the board temperature to verify that the fan is operating.
Paul
Mario Cannistrà
Dec 13, 2016, 5:48:21 AM12/13/16
to sara...@googlegroups.com, RA...@yahoogroups.com, Tony Bigbee, ia...@ionconcepts.com
Hello Dave, Paul, David, all.
I will try to catch up with all the topics and questions in this thread.
During this second half of the year I've been very busy selling my house and lost contact with the various forums. I will enter my new home on december 23 and hope to setup my new lab and antennas within january. So I'm sorry if I will not reply in a timely manner still for some time.
Back in June I asked for info through the myriadrf forum comments.
Unfortunately, I completely missed Ian's proposal because I didn't get any email from the forum software despite I had set the option for that.
I have to thank Dave for bringing to my attention that comment by Ian and I replied to both of them that I'm still interested in all of this and would very welcome any info / knowledge sharing / sources related with the FFT on FPGA topic.
Thank you also to David for the quick recap about what I would like to build. That's correct and I would like to keep that approach both for my rlt-sdr setup and for the new LimeSDR one.
Laptops and computers can certainly do wonderful things leveraging USB 3 and fast CPUs. And I will also do that for some time or with a second LimeSDR in the future.
But now my main objective is to get something standalone, unattended and running 24/7 possibly with low power consumption.
As David pointed out, this is for me an additional way of using LimeSDR (not a replacement or a change in what RASDR4 is offering).
@David: I'm a backer of LimeSDR but I did not get an early version of the board. I'm waiting like the others for the shipment and following all their updates.
Months ago I exchanged some emails within the SUG group and Nathan Towne kindly shared info on his setup and how he was using his FPGA.
I think all of you have read the wonderful article by Nathan in latest SARA journal titled "Poly-phase filter banks in amateur radio astronomy". So you already know even more details and the different ways you can run PFBs.
I would like to improve my Jupiter spectrograms re-creating or mimicking Nathan's sw, but the FPGA used on the LimeSDR is a different one. This means that a different development environment should be used.
I'm approaching FPGAs for the first time, but I'm used to learn new things so I'm not so worried about this. I already have knowledge about programming Arduino, Teensy, STM32, Raspberry PI,..... hope to add FPGA to the list :-)
This is my current understanding of the FPGA landscape (someone will kill me for incorrect wording):
- We are all used to CPUs that can run programs... FPGA actually run something that is more close to a configuration than to a program. i think this is called a "design" since it's about designing hardware
- there's a lot of parallelism in how the FPGA works and your design runs on a "stream" of data with everything governed by the clock
- you can write FPGA sw using various tools that can simplify your job also in testing the design before deploying that to the FPGA and run it normally
- FPGAs internal "resources" (LUT, LE, memory, etc) vary a lot in number, offering you different degrees of capabilities and limitations between different FPGAs
- this is why a design used on one FPGA has to be "ported" in order to use it on another FPGA
- porting can be feasible or not depending also on the different "resources" available
- so the design used by Nathan on his Xilinx Spartan 3 should be "ported" in order to run on the LimeSDR ALTERA Cyclone IV
- a comparison of some FPGAs features: https://codingcipher.wordpress.com/2012/05/14/fpga-vendor-size-comparison/
- if you look at an example source code for an FPGA, written in Verilog or VHDL, you will immediately understand that writing an FFT implementation is not so trivial and actually reminded me of when I wrote programs in assembly... this should give you an idea...
- there are FFT implementations available as so called "IP cores" but those are expensive
- so I searched for open source designs and found http://opencores.org/ where you can find interesting things. I think some could be interesting for us but I need to setup a development environment in order to try and test something. Will see
- ever since I'm a Python fan ... I also searched "FPGA" between python packages and found https://pypi.python.org/pypi?%3Aaction=search&term=fpga&submit=search that there's a good number created to develop and test designs for FPGAs
- seems that interest for FPGA development keeps increasing month after month also because of new capabilities and increased usage by the industry. this is motivating lots of people that cannot afford expensive licenses for IP cores in creating free python based design tools. this happens also because of increased interest by Universities and shrinking budgets....
- i would be really happy if I could just run FFTs... adding all the other PFB code could be even more challenging.
Honestly, I think that good input from people already skilled on FPGA development is more than welcome.
I remember that the LimeSDR guys mentioned sw coming to the Ubuntu App Store but I don't know if and where we can get info on what is boiling down and if someone is actually writing sw interesting for us.
I will certainly start experimenting as soon as I can. Then I should be able to say if I can go on.
I already installed http://www.myhdl.org/ in 20 seconds with a simple pip install myhdl.
Hopefully one can get started designing and testing with similar speed :-)
please let me know your thoughts...
mario
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