Cache analysis timing seems to be off

[mclau...@gmail.com]

Hi

The timings Mark Seaborn report in http://lackingrhoticity.blogspot.com.es/2015/04/l3-cache-mapping-on-sandy-bridge-cpus.html 

in the 'Verifying the cache mapping' show that the spike in the chart is because of the transition from L3 to memory, but it seems to me to be more related to the spike from L2 to L3, here's why:

Intel documentation states that Sandy Bridge L2 latency is 12 cycles and L3 is 26-31. But in the charts the first 12 memory accesses have a 40 ns timing, which is consistent with a L2 cache access

40ns / 3.2 ghz[1] = 12.5 cycles

and the rest of the accesses have a timing consistent with L3:

110ns / 3.2 ghz[1] = 34 cycles

Could someone please explain why are the timings are like that?

Thank you

Regards

[1] In the spec sheets for the i5-2520M the max frequency is 3.2GHz: http://ark.intel.com/products/52229/Intel-Core-i5-2520M-Processor-3M-Cache-up-to-3_20-GHz