Zynq Book

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Tillie

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Jul 25, 2024, 1:22:29 AM7/25/24

to rojamechi

I have just started a project with the Zybo Z7-20 board and I am trying to build a simple system using Vivado IP Integrator. I have added the Zybo Z7-20 board files to the Vivado but the board still does not appear in the presets for Zynq Processing System. Also I was not able to find any presets tcl file for the board in the internet. Does any one know where can I find this presets tcl file for the board is there any reference Vivado project for the board to start with?

I tried to add the board_files for Zybo Z7-20 to Vivado 2017.4 using the instructions in this, but the Zybo Z7-20 board still does not appear while configuring the Zynq7 Processing System IP in Vivado IP Integrator.

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when trying to apply configuration, it just accepts .tcl files and not .xml files. Also importing the presets.xml file through the "Import XPS Settings" button seems to have no effect! I found that .tcl file for the Zybo board here but it was not available for Zybo Z7-20. Is it possible to use the ZYBO_C.tcl for the Zybo Z7-20 too? Or how can I fix the problem that Zybo Z7-20 does not appear in the Vivado presets list?

Make sure you have installed the board files. When you create a new project are you able to select boards and click on your board? Here is the zybo-z7 resource center. It has quite a few tutorials to help you install board files and get your projects going. Please be more specific about your issue. Could you attach a screen shot of your issue?

I have installed the board files and i am using Arty Z7-20. I am able to successfully run few projects on the board and got the output as expected. I want to run 2 bare metal applications on the ARM processor and following XAPP1079 example project. I am able to build the project but app_cpu0.elf file is not loading onto the hardware. Its popping the error message that "ERROR : Memory write error at 0x100000. APB AP transaction error, DAP status f0000021" and later on found that ZYNQ system has ZC702 board preset files. Now i want to change it into ARTY-z7 20 but its not showing under preset button. if i import preset.xml file using "Import XPS Settings" also the same error message (ERROR : Memory write error at 0x100000. APB AP transaction error, DAP status f0000021) is coming in SDK platform while loading .elf file.

As @jpeyron said in the post marked as accepted solution, the Zynq processing system will be configured with the board presets when you first add the Zynq processing system IP core to the block design and run the block automation task from the green message that appears! Just remember to keep the Apply Board Preset option checked as shown in he picture. So this means if you are using the pre-built block design from the example project, a possible solution can be to remove the existing Zynq processing system block and adding a new one!

Deleting the existing Zynq block and adding a new one will give you the possibility to apply the presets. However, any configuration change you did before (e.g. adding gpio, ddr ports etc.) will be lost. Even if there are connections created between blocks - these will be deleted then.

Actually I stored a preset from a design which is a bit more complex and use this for other designs. Not used things can be switched off later. As long as my understanding of the Zynq block isn't that good, I prefer starting with something validated instead of searching to much in the settings.

I think Digilent provides these presets in an XML file. When I compared the .xml file for my board to a .tcl file for another zynq board they look like the same properties in a different format. I think you can manually import them using the Import XMS settings button to the right of the Presets button. I imagine the comments above also apply in that these preset will automatically get applied if you use the Digilent supplied board file.

I am currently having the exact same problems, with Vivado 2020.2, running on a LINUX (like Mohammadhgh) and the ZYBO Z7. I don't remember such thing with 2020.2 on Windows (going to give it a try). No such problem with an other Digilent board like the Cora Z7.

I tested today on Windows. I can confirm that the problem is only with 2020.2 Linux, ZyboZ7 (no problem with Zybo) It looks like something in the presets files of the Z7 prevents the automation to use it properly. Therefore, it just presets nothing.

If I open a project generated with windows version, or if I apply a TCL preset script (see attached .tcl file) made with the windows version, there is still a problem on the Linux version, which may be a hint for that problem: the ENET0 clock is in error state. See screenshot:

I don't have a Linux machine to test this (I only have Windows 10), but I would be interested to know if this same issue occurs with the Arty Z7-20 board files where you get the red text and errors for setting Ethernet0 to 1000 Mbps using an IO PLL only on the Linux installation, and if the Arty Z7-10 and the Zybo Z7-10 (since you mentioned you saw this on the Zybo Z7-20 specifically) seem to have their presets applied as intended just like the Cora Z7-10 does.

I gave a try with Arty Z7-20 and Vivado 2020.2 Linux. Seems to work properly: with just the Zynq IP, no strange things after running automation, generation of BD, synthesis and implementation are running flawless. See screenshot of the clocks: no error with ENET0. I couldn't test it for real: I don't have any Arty.

OK, Problem solved, thanks to a colleague at Grenoble-Alpes university. This issue is related to separators in files, which can cause problem with regional settings of Linux. Changing my settings from fr_FR to en_US solves the problem.

I'm having trouble establishing an Ethernet connection in u-boot from my Zynq Ultrascale+ (XCZU28DR) MAC to the DP83867E via SGMII out to copper to an RJ45 connection so: (Zynq)MAC->DP(PHY)->copper->RJ45. I cannot ping, I cannot dhcp, and I cannot get any activity on wireshark. I've tried almost everything I can think of and after doing all of it, I think there is an issue with the SGMII link. With everything below considered, I believe this to be the case because I'm able to have a successful loopback test right before the GTR transceiver in the Zynq sends out the signal via SGMII and the most shallow loopback in the TI phy fails (MII loopback).

So how is it that the link status for the zynq and ti chip for SGMII are up, and SGMII auto-neg is successful, then how is there no transfer of data, indicated by the MII loopback test within the TI chip failing?

Thank you for reaching out and sharing your question. I will need to investigate this issue further with my team as it seems like you do have the correct setup for SGMII which is why it's peculiar that you are not seeing any data transfer.

Actually some good news is that I managed to get my Ethernet link all working through sgmii, but I had to bump the sgmii speed down to 100Mb/s. which is odd because the TI chip is set-up for 1000Mb/s sgmii, any thoughts on why this is doing that? Could it be a problem with the sgmii lines?

Oh interesting about 0x11? because if you look in my original post my output for 0x11 is 7F02 which is a speed of 100M and this is the cable speed out to the RJ45? I wonder what would cause that to bump down since its trying to configure the speed for 1000M per register 0x0.

I'm bumping the speed of the SGMII output from my zynq ultrascale processor, there is a physical coding sublayer (PCS) that goes to a GTR transceiver that outputs the SGMII, I'm changing the speed of the PCS from 1000M to 100M and that works.

"For more than 10 years we have been discussing exactly this symbiosis possibility of processor and FPGA on one die to reduce cost and PCB space. Over time several companies have tried such an approach, but none of them offered a tight integration that allowed us to meet our targets. Finally, our long time wish becomes reality with the Xilinx Zynq-7000 family," said Ralf Schaffer, project lead at Agilent Life Science Group. "This means Agilent can now create many different product variants on a common code base from low-end, mid-range, to high-end, with minimal cost and engineering overhead."

Each Zynq-7000 EPP device is built with an ARM dual-core Cortex-A9 MPCore processing system with NEON and Double Precision Floating Point engines that is fully integrated and hardwired, and includes L1 and L2 caches, memory controllers, and commonly used peripherals. The processing system boots at power-up and can run a variety of operating systems independent of the programmable logic. The processing system then configures the programmable logic on an as needed basis. With this approach, the software programming model is exactly the same as standard, fully featured ARM processor-based SoCs.

In parallel, the Zynq-7000 family's programmable fabric can be tailored to maximize system level performance and application specific requirements, leveraging Xilinx's award winning ISE Design Suite, which provides a comprehensive hardware development environment that includes development tools and AMBA4 AXI4 Plug-and-Play intellectual property (IP) and Bus Functional Models (BFM) to accelerate design and verification. Following Xilinx's acquisition of high level synthesis leader AutoESL Design Technologies, Inc., further tool enhancements are underway to provide C, C++ and SystemC synthesis optimized for the Zynq-7000 device architecture. Future releases will also enable a more seamless movement of key algorithms between the processors and the programmable logic of the Zynq-7000 family.