XBitmanip 0.34 draft spec

[Clifford Wolf]

Hi,

I just tagged the xbitmanip draft revision 0.34. In a way it is a meaningless gesture

of course, but I feel like I'm now past a certain milestone with the document where it's

(hopefully) incremental improvements from here on instead of massive rewrites and

restructuring.

Please give it a read and reply with your feedback:

https://raw.githubusercontent.com/cliffordwolf/xbitmanip/master/xbitmanip-draft.pdf

regards,

 - clifford

[Neel Gala]

Hi Clifford,

I have gone through the draft-0.35 and had a few questions:

1. One of the evaluation strategies mentioned in the draft says that only instructions found in the real-world applications will be accepted. I wanted to know if you do have some benchmarks or some applications available which I can test out to see where the proposed instructions can be useful? this just for my own curiosity.
2. Is it possible to encode some instructions in the 16-bit space or is it mandatory to encode them in 32-bit space only?
3. How is SROW/SRO different from the the base spec instructions SRAW/SRA?

I'll probably leave the rest of my questions for later.

thanks,

[Clifford Wolf]

Hi,

On Thursday, April 26, 2018 at 6:24:46 PM UTC+2, Neel Gala wrote:

One of the evaluation strategies mentioned in the draft says that only instructions found in the real-world applications will be accepted. I wanted to know if you do have some benchmarks or some applications available which I can test out to see where the proposed instructions can be useful? this just for my own curiosity.

 

Most of this work is still outstanding. (I've done some preliminary stuff, but nothing serious.) As it says in the introduction chapter, this is the next step.

Is it possible to encode some instructions in the 16-bit space or is it mandatory to encode them in 32-bit space only?

 

I'm not sure what you are asking here. RISC-V does have compressed 16-bit instructions (the "C" extension) and for processors that support the "C" extension XBitmanip mandates three compressed instructions: c.not, c.neg, and c.brev.

 

How is SROW/SRO different from the the base spec instructions SRAW/SRA?

 

SRA shifts in 1s when the MSB of the argument is one. SRO and SLO shift in 1s always.

regards,

 - clifford

[Neel Gala]

Thanks for the info.

I missed out on reviewing the C.neg, c.not and c.brev before posting. 

I see in the latest draft you have added some area numbers. I am assuming you have built these in verilog? Can you provide access to the verilog files?

I am interested in porting the current draft to one of our processors (SHAKTI processors) and would like to see the prelimnary numbers on area, performance and power.

Also are you aware of any riscv profiling tool which can analyze a trace dump (something similar to the log-file of spike) and provide stats like instruction histogram, RAW dependencies, top-most common sequences. I ask this since I would like to profile a few codes/benchmarks and see if some of the sequences can actually be directly mapped to the ISA proposed here.

[Clifford Wolf]

Hi,

On Mon, Apr 30, 2018 at 6:49 PM, Neel Gala <neel...@gmail.com> wrote:

I see in the latest draft you have added some area numbers. I am assuming you have built these in verilog? Can you provide access to the verilog files?

They are in the same github repository as the XBitmanip document:

https://github.com/cliffordwolf/xbitmanip/tree/master/verilog

I've now also added that link to the XBitmanip PDF.

I am interested in porting the current draft to one of our processors (SHAKTI processors) and would like to see the prelimnary numbers on area, performance and power.

Support for XBitmanip in SHAKTI would be great!

Also are you aware of any riscv profiling tool which can analyze a trace dump (something similar to the log-file of spike) and provide stats like instruction histogram, RAW dependencies, top-most common sequences. I ask this since I would like to profile a few codes/benchmarks and see if some of the sequences can actually be directly mapped to the ISA proposed here.

I'm not aware of any such tool. But that might simply be because I'm not very familiar with the tool ecosystem surrounding spike.

regards,

 - Clifford

[Neel Gala]

On Tue, May 1, 2018 at 5:35 PM, Clifford Wolf <cliffor...@gmail.com> wrote:

Hi,

On Mon, Apr 30, 2018 at 6:49 PM, Neel Gala <neel...@gmail.com> wrote:

I see in the latest draft you have added some area numbers. I am assuming you have built these in verilog? Can you provide access to the verilog files?

They are in the same github repository as the XBitmanip document:

https://github.com/cliffordwolf/xbitmanip/tree/master/verilog

Great will get started and keep you posted! 

I've now also added that link to the XBitmanip PDF.

I am interested in porting the current draft to one of our processors (SHAKTI processors) and would like to see the prelimnary numbers on area, performance and power.

Support for XBitmanip in SHAKTI would be great!

Also are you aware of any riscv profiling tool which can analyze a trace dump (something similar to the log-file of spike) and provide stats like instruction histogram, RAW dependencies, top-most common sequences. I ask this since I would like to profile a few codes/benchmarks and see if some of the sequences can actually be directly mapped to the ISA proposed here.

I'm not aware of any such tool. But that might simply be because I'm not very familiar with the tool ecosystem surrounding spike.

Yea searched as well.. no luck! Was hoping to use such a tool to find particular sequences within an application.  

regards,

 - Clifford

--

Neel Gala

Senior Project Officer

RISE LAB, IIT-Madras