Instruction encoding

[M Farkas-Dyck]

The document proposes to encode grev(i) as sla(i), and shfli as roli, but how shall we encode shfl? I have 3 alternative ideas:

1.
rol can be encoded as sub+ror, so scrub rol and encode shfl as rol.

2.
Use another bit of funct7 (maybe bit 29) to mean permutation — it is far more space than we need, but most of it remains free for future brownfield encoding.
Encode grev and shfl as minor (funct3) opcodes in this space.
Encode rol and ror as before, in the shift space — they are permutations, but rather similar to shifts, so it would be easier to decode.
Leave sla undefined.

3.
Use the MSB of the instruction to mean permutation, with 2 minor opcodes (TBD) other than shift.

Thoughts? If we reach a consensus i'll modify the doc to specify the encoding.
Of course, if we ultimately reject sro/slo we can encode grev and shfl there.

[Clifford Wolf]

Hi,

On Sat, Oct 6, 2018 at 12:03 AM M Farkas-Dyck <stra...@gmail.com> wrote:

The document proposes to encode grev(i) as sla(i), and shfli as roli, but how shall we encode shfl? I have 3 alternative ideas:

Its far too early to discuss concrete encodings imo. The grev(i)/sla(i) thing is just in there because it already was part of the

original B-extension draft proposal that I based XBitmanip on.

regards,

 - Clifford