Cache coherence system

[Rafael B. Tonetto]

Hi, Mr. Celio.

I have some doubts:

1) What's the BOOM's cache coherency system? Is it parameterizable? 

2) If so, should I change just the 'cache.scala' file? I can see that in that file there's something like "val logic = new RandomReplacement(n_ways)" about line 70.

3) Is there any way to force the dcache to flush it's data through the C++ emulator?

 

Thanks a lot!

[Christopher Celio]

1. The cache coherence system is covered by the rocket-chip TileLink protocol (https://github.com/ucb-bar/rocket-chip). Some possibly outdated documentation is linked to here (http://bar.eecs.berkeley.edu/projects/2014-tilelink.html). 

2. You can try, but something like "randomreplacement" is handling how to replace which way gets evicted; nothing to do with cache coherence.

3. No, there is no way to force a D$ flush.