Update to BOOM

[Christopher Celio]

Hey all,

I just made a new push to BOOM's master branch and I'm excited to provide an update on the past few months of work.

1) I have tried to move to a more 'stable' method of development. There is now a "devel" branch to complement the "master" branch. Specifically:

rocket-chip repo -> boom branch is stable, boom-devel is unstable

boom repo -> master is stable, devel is unstable

I will try to keep work-in-progress stuff on a "feature" branch separate from devel.

2) I have updated to a ~February version of rocket-chip that implements the TileLink version2 protocol.  Unfortunately, this means there is no L2 cache (for now), but on the plus side, the TL network has had much more development and verification put into it.

3) I have addressed some breakages to 4-wide BOOM that crept in. Please continue to report any issues on github so I can track any problems as they arise! Thanks to everyone who have reported issues and helped out on this front.

4) BOOM once again works with the fpga-zynq repo. By default, BOOM is built using the Debug Transport Module to tether BOOM to riscv-fesvr, but there is also support for a Tether Serial Interface, which is less interference and more useful for benchmarking BOOM (in simulation and on the FPGA).

5) BOOM now uses a new "config" project for providing parameterization throughout the rocket-chip system (local within rocket-chip). I have renamed MediumBOOMConfig/MegaBOOMConfig to MediumBoomConfig/MegaBoomConfig as part of a general re-organization of the configs.scala/parameters.scala setup.

6) BOOM continues to support the v1.9(.1?) version of the Privileged Architecture. There is a WIP-draft of v1.10 being used by Rocket, but I expect I will hold off for the next two months on this.

7) BOOM now has a synthesizable TAGE branch predictor (or at least, the FPGA loves it). Its ASIC synthesis/timing QoR is still a WIP, so it is not the default predictor for any BOOM configuration. TAGE is a state-of-the-art predictor that can allow the processor to remember and make predictions based on the last thousand branch outcomes!

8) BOOM's gshare predictor (and TAGE) uses synthesis-friendly SeqMems which can be black-boxed and replaced with SRAMs (SRAM library files not included). In particular, the "tall, skinny" two-bit counter arrays are automatically turned into rectangular, single-ported memories in Chisel. 

Going forward, I hope to see more changes to BOOM that will improve synthesis QoR and IPC performance.

Enjoy!

Chris