RISCV-BOOM RTL simulation from checkpoint

[Monir Zaman]

Hello,
I am trying to find if there is a way to run checkpoints of benchmarks on the BOOM RTL using VCS simulator and generate some activity numbers (such as number of Load instruction, ALU operations etc)? Is there any tool available to create such checkpoints based on SIMPOINTs? How are the benchmark files generated for RTL simulation in RISC V and then loaded into the BOOM processor memory for simulation?

I have the RISCV tools installed and have access to the toolset. (I am not too familiar with the whole design flow of the RISC V toolset, so my question can sound incomplete/vague)

Sincerely
Monir

[Christopher Celio]

Hi Monir,

Unfortunately, there is not a general checkpoint mechanism that I know of within the RISC-V ecosystem. There is this (closed) pull request from NCSU to add simpoint support to Spike (https://github.com/riscv/riscv-isa-sim/pull/19), but unfortunately, I believe that only told you WHERE the simpoint is, but did not otherwise generate the checkpoint file itself.

You may try poking around the RISC-V/gem5 community to see if they know of any RISC-V checkpoint tools. However, BOOM/rocket-chip does not have any mechanism to load an architectural/micro-architectural checkpoint. You could hypothetically have a checkpoint that is stored as a regular program though.

For my own testing, I run BOOM on an FPGA and use the HPM counters to read perf events from BOOM.

-Chris