Generating Chisel for sub-modules

[Amund Kvalsvik]

Hello BOOM mailing list,

I am wondering if anyone has a concrete guide for generating just verilog for a specific BOOM submodule? Specifically, I want to create verilog for the rename-stage with dangling inputs/outputs in order to use an ASIC tool to estimate timing limitations of the stage. I believe this should be possible, but the guides I read for chipyard/BOOM seem more concerned with how to synthesize full projects (understandably enough), but I only need the submodule, and it does not have to be functional (inputs/outputs can be macroed if desired).

Any advice is very much welcome

Kind regards,

Amund