BOOM Processor- Chicken Bits

[v.a...@mobiveil.co.in]

HI all
   For post silicon debugging purpose i want to able/disable different logic blocks in the BOOM processor by setting so called "Chicken Bits". The primary inspection suggest i can able/disable Branch Prediction, Cache etc. Can you please specify which logic units in BOOM can be configured by setting bits for post silicon testing and how?
Please suggest a direction in which i shall look at.

BR

[Christopher Celio]

Hi BR,

Thanks for your interest in BOOM! Although BOOM has a number of build-time/synthesis-time parameters that affect things like "which branch predictor would you like to build?" or "synthesis a FDiv/FSqrt unit?" [1], there are currently no post-silicon chicken bits in BOOM.  They are on my TODO list, but that list is very long and chicken bits keep getting pushed down in priority. :(

For enabling/disabling some things though, it wouldn't be too hard to add them in yourself.  You could add non-standard Control/Status Registers [2] to the CSRFile, allowing software (or the debugger) to write to CSRs that will enable/disable silicon features.  You can then widen the CSRFileIO interface [2], and string your chicken bit into the module you want to disable. For something like the backing branch predictor, you could gate off its prediction here [3].  

-Chris

[1] boom-chip/boom/src/main/scala/configs.scala

[2] boom-chip/src/main/scala/rocket/csr.scala

[3] https://github.com/ucb-bar/riscv-boom/blob/master/src/main/scala/bpd_pipeline.scala#L150

[v.a...@mobiveil.co.in]

Thanks for a quick response  dear Christopher Celio.

"    For enabling/disabling some things though, it wouldn't be too hard to add them in yourself.  You could add non-standard Control/Status Registers [2] to the CSRFile, allowing software (or the debugger) to write to CSRs that will enable/disable silicon features.  You can then widen the CSRFileIO interface [2], and string your chicken bit into the module you want to disable." 
 

       Well, that's exactly what i am doing. I am planning to string the modules with a new CSR Register. Now there are two questions : "Which Modules" and "How".

1. Well, i think we can able/disable features like Cache, BP, Load/Store unit, at the time of debugging without stopping complete execution. Can you please specify a quick list of the modules which i may try to provide this able/disable functionality?

2. As i am very new to Out of Order Processor/ BOOM architecture (3 days old to be precise.. lol), can you please specify in which chapter or BOOM Spec, i can get more information about how exactly to control these modules?

Any info/suggestion will be highly appreciated.


Thanks & Regards

 

[Christopher Celio]

1. It's not entirely clear what list of modules would be useful to disable.  As an example, what does it mean to disable the cache, but leave the rest of the processor enabled? What kinds of programs are you still hoping work?  Even if you want all loads to execute as uncached operations, that still requires communicating and exercising a lot of the cache logic.

2. The BOOM documentation gives a high-level view of the processor design, but it's not going to give enough low-level detail on specific signals to target-- it would be too difficult to keep the documentation in lock-step with the code.

If there is a particular behavior you want to disable, or a particular module that you want to disable during validation, I'm happy to provide some more directed guidance into the code.  

-Chris 

[AKV]

Well, instead of controlling signals on the code of boom, we can control the control registers and manipulates them to disable few modules in the design.
What are the control registers provided in BOOM other than for time/counter and instructions?  Which modules can be controlled directly by their control registers?

[Christopher Celio]

There are no control registers beyond what is specified in the RISC-V Privileged Architecture specification.  So nothing micro-architecturally specific to BOOM.