Can the registerfile be implemented using a synchronous read SRAM?

[Øyvind Harboe]

Currently the registerfile is implemented using an asynchronous read SRAM (no clock for read operation).

Is there a reason why the registerfile has to be implemented using an asynchronous read SRAM?

I tried switching to a synchronous read SRAM and it seems to pass the tests:

https://github.com/riscv-boom/riscv-boom/pull/656

[Jerry Zhao]

We typically don’t have access to synchronous multi ported memory primitives, so the instantiation of the register files as Mem rather than SyncReadMem hasn’t mattered. 

I believe now, the design should support instantiating them as SyncReadMems, as you’ve noticed. There should be a flag to select this. 

-Jerry

--
You received this message because you are subscribed to the Google Groups "riscv-boom" group.
To unsubscribe from this group and stop receiving emails from it, send an email to riscv-boom+...@googlegroups.com.
To view this discussion on the web visit https://groups.google.com/d/msgid/riscv-boom/acffb370-f059-471b-86dd-95918293d29dn%40googlegroups.com.

[Øyvind Harboe]

I see. I'm afraid I don't know enough about Chipyard to introduce a flag...