Welcome to the RISC-V BOOM Processor Google group!

[Christopher Celio]

Feel free to ask any questions you have about BOOM here!

The BOOM source code can be found here:

https://ucb-bar.github.io/riscv-boom

And the design specification can be found here:

https://ccelio.github.io/riscv-boom-doc

[Sean Halle]

Hi, thanks for starting this group.  I read the EECS brief that you put out about BOOM.  Kinda cool :-)

I mean, an out of order core is an amazing amount of work.  It looks like you pretty much did the whole thing yourself!  That's kinda crazy, when you think about it.  How long did it take you to do all that?

The result is pretty amazing.  From the performance numbers, it looks like pushing the pipeline deeper could get you to the 3GHz range.  Especially if you go to 2 stages for cache access (and make up for the IPC loss with larger ROB and more reg file entries for renaming).  Do you think the synthesis toolflow could actually deliver that fast of a chip, especially if you shoot for the SS corner, to get the yield up?  

Are you planning on doing anything commercial with the core?

Thanks  :-)

Sean

[Christopher Celio]

Hi, thanks for starting this group.  I read the EECS brief that you put out about BOOM.  Kinda cool :-)

I mean, an out of order core is an amazing amount of work.  It looks like you pretty much did the whole thing yourself!  That's kinda crazy, when you think about it.  How long did it take you to do all that?

Thanks! I started three or four years ago, but as a grad student, there's lots of other jobs I have to take on (like teaching), so it's not been a full four man-year effort.  While I've been able to focus on the core, there are lots of other people working on all the other parts of a processor system who get a lot of credit too (caches, uncore, test harnesses, ISA tools, Chisel language work...).

 

The result is pretty amazing.  From the performance numbers, it looks like pushing the pipeline deeper could get you to the 3GHz range.  Especially if you go to 2 stages for cache access (and make up for the IPC loss with larger ROB and more reg file entries for renaming).  Do you think the synthesis toolflow could actually deliver that fast of a chip, especially if you shoot for the SS corner, to get the yield up?  

For my lab's tape-outs, we've not really been in a position to play with the SRAMs - we use what we're given. So the critical path has always been the cache access, which limits us to 1.5-2 GHz. Of course, there's games we could play there (I think the actual solution would be to bank the cache so you can still get multiple requests in flight), but we've not pulled the trigger on going down that rabbit hole.  There's enough risk on the tapeout as it is.  I also can't say with any knowledge how the other stuff will behave, like the clocks or power rails.  

 

Are you planning on doing anything commercial with the core?

I have no idea what comes next. I just like building processors.

-Chris

[AKV]

This is a huge amount of effort you have put upon to come up with entire BOOM. Quite Inspiring.
 I saw your profile and came to know that you enrolled in Phd from a long time and devoting your efforts for BOOM. 

I appreciate your activeness on discussion forum and your timely replies.

Keep the good work alive. May the force be with you !

Warm Regards
AKV

[Christopher Celio]

Thank you AKV!