riscv-boom

Thank you AKV!

Hello BOOM mailing list, I am wondering if anyone has a concrete guide for generating just verilog

Hi, I would like to understand how the physical memory protection is implemented on Boom. I compiled

Thank you, Jerry. Is there a timeline for when you plan to release the documentation of Boom V4? On

Hi Jerry, I got the CMO instruction to work. I see issue in case of a store. it is not waiting for

I should add that the re-read of the tags, while wasteful in most cases, is at least not on the

Thank you Tom! That was my thought but I did not manage to follow the code to see if it was actually

I was wondering at what stage of the processor (using the WithNMegaTapeoutBooms configuration) could

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The chipyard documentation provides sufficiently thorough instruction for installing and setting up a

That is just initializing the state after reset. The predictor behavior immediately after reset wasn

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If you could not find the exact driver for your hardware device or you aren't sure which driver

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Update: We've confirmed this issue exists when executing on both vanilla 1.6.2 BOOM and vanilla

The explanation below is taken from the https://docs.boom-core.org/en/latest/sections/reorder-buffer.

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I see. I'm afraid I don't know enough about Chipyard to introduce a flag... On Friday,

Hello, I'm using https://github.com/eugene-tarassov/vivado-risc-v to run a Linux system with on a

You have to modify the CIRCT verilog emitter options to disallow generating the unsupported

You are right, that code does appear to be vestigial. Note that the "bypass" parameter of

This is configurable through Chipyard. The L2/LLC caches are external to the core. -Jerry On Mon, Jul