That's pretty amazing:
"For the Z84013/015, together with /BUSREQ, the RV signal puts the IPC into the evaluation mode. When this signal ecomes actve, the status of /M1, /HALT and /RFSH change to input. When using Z84013/015 as an evaluator chip, the CPU is electrically disconnected after one machine cycle is executed with the EV signal "1" and the /BUSREQ signal "0". It follows the instruction from the other CPU (of ICE ???). Upon receiving /BUSREQ: A15-A0, /MREQ, /IORQ, /RD and /WR are changed to input ad D7-D0 changes its direction, /BUSACK is NOT 3-stated so it should be disconnece by an externally connected circuit"