Beating a dead horse here I guess.
GALs/PALs/CPLDs
Reduce logic if possible
Hide passives under IC sockets and/or place from the back
SMT :)
Other than that stretch the board upwards like you have shown.
Possibly use a second board with ribbon cable depending on signaling requirements.
I'm developing a Microchip/Microsemi Igloo2 FPGA card and will have to address these concerns with the I/O I'm putting on the board. Probably will be all SMT but will grow board vertical if need be.
Greg