Regarding suitable access time of RAM/ROM

[Marten Feldtmann]

I've always trouble calculating the minimum access time for suitable RAM/ROM ICs for the MC68000 ... but regarding the Z180 would this simple calculation be a suitable way to calculate the minimum access time needed for a specific system clock ?

So I assume sc = system clock in mhz, ic_at = read access time for the IC.

I take  the well known AS6C4008 with its 55ns (read cycle time, write cycle time), so ic_at = 55 * 10^(-9) s.

The Z180 is running at 18 MHz => sc = 18.000.000 => 5.5*10^(-8)s => 55*10^(-9)s, the duration of a simple read cycle is 3 cycles => 165*10^(-9)s.

So, the AS6C4008 is well known working with the 18MHz Z180.

(all numbers without any additional buffers and address decoding time).

We could add a ATF22V10C-7 for address decoding and this device seems to be able to calculate the output signals in 7ns (unsure if I used the correct number from the datasheet).

What about the 33 MHz version ? The cycle time is for 33MHz sc = 30,3*10^(-9), so even here for a simple read cycle we only need 91*10^(-9)s.

Now, we look at the ROm part, the well known SST39SF040-70. The read-cycle time is 70ns ... and even here the usage in a 33MHz system would be possible. The 91ns is more than 70ns + 7ns.

So, is this a possible calculation or is this simply wrong ?

[Derek Cooper]

It's not the case that the memory has to mach the system clock speed. Generally memory access takes 3 or 4 clock cycles (depends on the instruction) It's made a little more confusing by Zilog referring to M cycles and T cycles. As I understand it an M cycle is a full sequence of hardware operations in the CPU and it has several T cycles in it. T cycles are CPU clock cycles (no Idea why T). You will often see in Zilog sheets things like M1/T3 - all it means is that it has one machine cycle consisting of 3 clock cycles.

M cycles come in different types (main ones being)
Opcode Fetch (aka M1 cycle): this is always the first (and sometimes only) machine cycle in an instruction and takes 4 clock cycles
Memory Read: read a byte from memory (3 clock cycles)
Memory Write: write a byte to memory (3 clock cycles)
IO Read: read a byte from an IO port (4 clock cycles)
IO Write: write a byte to an IO port (4 clock cycles)

Each one takes 3/4 clock cycles, so I always assumed that you need to divide the system clock by at least 3 then do your ram access times. I maybe wrong of course, see what others say.

Derek

[Tom Storey]

55ns is about 18MHz, but this is not in relation to the CPU clock.

As mentioned, if the CPU is clocked at 18MHz and takes a few clock cycles to complete a memory access, then the CPU can likely be run at 2-3 times that frequency while still maintaining the 55ns access time.

Use the timing diagrams of the CPUs read/write cycles to figure out how long it is taking to complete each cycle and then you can figure out the maximum clock speed that it could operate at.

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[Douglas Miller]

It's actually neither T cycles nor M cycles, but rather /MREQ and /RD,/WR durations, setup and hold times. If you're trying to be exact, you have to look at the timing diagrams for the various CPU cycles and see if you can meet the requirements of the memory. Making matters worse, the memory chips advertise a single "access time" but it really isn't that simple in the details if you look at the datasheets. All that being said, you can generally compare the memory access time and assume a single clock (T) cycle time, as you have done, and be close. With the Z180 you can fine-tune the WAIT states. I've seen Z180 ROM code that runs with 3 WAIT states (for slow ROM) until it can copy everything into RAM, then drop down to 1 or 0 WAIT states.

[Bill McMullen]

The tightest memory timing on the Z180 is an op-code read which is 1 T state versus 1.5 T for data reads.  At higher frequencies you also have to take into account the delay of any memory decoder and also signal rise/fall times.  Thus the minimum memory time becomes Tcyc+Trise/fall+Tdecode or the maximum frequency with a 55ns memory is roughly 1/(55n+5n+7n) or about 15 MHz over the full temperature range.  Note that some decoders like 74LS138 or HCT138 can be up to a 40ns delay.

While those are the theoretical numbers, I've scoped several Z180's and found their memory timing is MUCH more conservative than the data sheets imply and thus 18.432 MHz is quite possible with 55ns RAM.

For the 33MHz Z8S180, or overclocked to 36.864 MHz, I tend to use commonly available 10ns memories although I've also used 20ns ones along with a fast memory decoder.  As to the SST39SF040's in these systems: The now obsolete 45ns variety work well with one wait state whereas the 55 and 70ns versions should have 2 wait states to be within datasheet specifications.

[Bill Shen]

If you ground the chip select of RAM, the access time from output enable and write enable is shorter than 55nS.  Also bear in mind AS6C4008 is rated 55nS from 2.7V to 5.5V; it is slowest at 2.7V yet still capable of 55nS access so it is significantly faster at 5V.  Almost all my Z80 designs run at 22Mhz with AS6Cx008–a clear violation of timing spec, but work every time, RAM access time is the least of my problem.

  Bill