Fun with an ATF1508 and a 6809

[Warren Toomey]

All, I have a project which involves a 6809 CPU and an ATF1508 CPLD (5V device). It's still early days, but I thought I'd mention it as some of the ideas might be useful to others.

The project, in its infancy, is at https://github.com/DoctorWkt/MMU09. Essentially, a 6809 with an MMU that provides 8K pages. What I think is interesting is my CPLD workflow and my use of an Arduino as data logger.

To program the CPLD I'm using the (nearly) open source workflow from https://github.com/hoglet67/atf15xx_yosys to synthesize Verilog down to a JED file, then util.fuseconf from https://github.com/whitequark/prjbureau/tree/main/util to convert this to SVF, which I then send to the ATF1508 using openocd and an FT232H breakout board. It's all command-line and scriptable; I'm using make to do most of the work.

Most of the CPLD lines, and other interesting signals, are brought out the back of the PCB to pin headers which fit neatly in to an Arduino Mega 2560.

This allows me to do several things. I can insert a single component, e.g. the ROM, and prod the component with the 2560 to confirm that it's working as expected. And with a slow enough clock, like the 555 circuit you can see in the first image, I can log a few thousand samples of e.g. the address bus based on a trigger set in the Arduino's software (e.g. the reset line going high).

So far all I can do is output stuff on the UART - no actual MMU functionality as yet. I do have a full cycle-accurate Verilog model of the system and a simulator in C as well, so I can cross-compare them. But I think the CPLD gives the SBC a lot of design flexibility and the Arduino will help a lot with the debugging. Yes I do have a 16-bit logic analyser as well, just fiddly to wire up!

Cheers, Warren

[Bill Shen]

As a long-time user of CPLD, I applaud your new tool chain for Atmel CPLD (ATF150x).  While they are current replacements for the obsoleted Altera EPM7xxxS parts and available from Mouser and DigiKey, Atmel CPLD logic design tool has been a nightmare and its programmer is much too expensive.  While I’m at it, the parts are scarce and their cost are increasing rapidly.  Collectively these issues have turned into a tall wall discouraging hobbyists from using Atmel CPLD.  By providing a better design path and reducing the programmer cost, you have provided a more reasonable path for Atmel CPLD users.  I myself have purchased the expensive Atmel programmer, turned my back to the atrocious WinCUPL tool, tried designing in Quartus and used POF2JED to convert and program ATF150x, but that process has serious bugs resulting in many non-operational designs.  So I have quit using ATF150x parts and concentrated my efforts on acquiring large stock of working EPM7xxxS parts and designed in Quartus.  I’m successful in the part acquisition, yet the barriers were too numerous for most so I’m just one of a handful of CPLD designers in the retro community.  That’s unfortunate because CPLD is so powerful, we can all benefit from sharing interesting designs from a large user base.  So I welcome you as another CPLD designer successfully breaking through the technology barrier and I’m looking forward to read about your interesting designs.

  Bill

[7alken]

Thanks, very interesting. As I am only jumping into (C)PLD and FPGA, wanted also to try verilog on even tiniest Atmel ATF parts, found also the Quartus/pof2jed, but till now, had success only with very simple java "Digital" simulator (https://github.com/hneemann/Digital) which generates JED from schematic. Of course it cant synthesize verilog, but some possibility to integrate toolchain is possible. Even PLDs are totally new to me... this will be investigated, probably my very first real verilog to read deeply... ))


for @Bill:
I like your simplest riz180 and micro80/simple80 designs, have collected parts to build something soon, but probably with redesigned PCB slightly, also trying my own custom cards using 2mm pitch connectors (found and ordered just this night) using dual 30pin (2x15) for cards and even triple 30pin for cpu+mem to backplane connection ... just experiments here;
(till now I have built John's Z80Retro! only, wish to try at least simplest Atmel PLD too)

[Andrew Lynch]

Hi

You can use Digital to export Verilog (or VHDL) and import into Quartus II to synthesize a CPLD.  I haven't tried it with an FPGA but the CPLD portion seems to work fine.  Digital and Quartus is a good tool pairing.  I am hoping Yosys is a good synthesis tool but I haven't tried it yet.  Looks like the learning curve is quite steep.

Good luck!  Thanks, Andrew Lynch

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[Warren Toomey]

On Saturday, 30 September 2023 at 23:21:36 UTC+10 lyn...@yahoo.com wrote:

  I am hoping Yosys is a good synthesis tool but I haven't tried it yet.  Looks like the learning curve is quite steep.

 Probably getting yosys installed is the hardest part. The quick start guide at https://github.com/hoglet67/atf15xx_yosys is what I used to get my Verilog -> yosys -> ATF1508 JED file workflow set up, although I took his two scripts run_yosys and run_fitter and moved them to be on my executable $PATH.

Update on the CPLD on my 6809 board

The 6809 doesn't have the concept of pages or user mode/kernel mode (i.e. unprivileged and privileged modes). But it does raise the BS line when it loads the vector to deal with interrupts, reset and software interrupts (SWI). When the CPLD sees BS go high, it changes an internal register to mark the CPU entering kernel mode.

Actually, the CPLD keeps a stack of the last four transitions into kernel mode. Just before we RTI (return from interrupt), we access a memory address that tells the CPLD to go back to the previous mode:

      sta prevmode

      rti

We need this in case a usermode program does an SWI (system call) that goes into kernel mode. While the operating system is dealing with this, an interrupt comes in, keeping us in kernel mode. We use the above two instructions to leave the interrupt handler, going back to the system call code and we stay in kernel mode. And the syscall handler also uses these two instructions to return to the user code, this time transitioning back to user mode.

The CPLD also has eight page table entries for pages that are size 8K. This covers all of the 6809's 64K address space. Each page can be mapped to one of 64 page frames, which allows the system to have 51K of RAM.

In user mode 63.75K of address space is RAM (eight pages) except for the top 256 bytes which is ROM ($FFxx). We need this to hold the vectors for the reset and interrupt handlers. When we move to kernel mode, an I/O area at $FExx gets mapped in as well as nearly 32K of ROM from $8000 - $FDFF. These get mapped out when the CPLD takes us back to kernel mode.

We still need to be able to see all of the user's RAM in kernel mode, e.g. to copy data to/from the program and the filesystem. So there's a CPLD toggle mapped into the I/O area which allows the 32K ROM to be mapped in or out in kernel mode. Luckily the top 256 bytes of ROM stay mapped in :-)

All of this is working at 14.75MHz on my 6809 + ATF1508 board. I can start in kernel mode with the 32K ROM mapped, copy machine code to low RAM and switch to user mode (mapping out the I/O area and 32K ROM). The user code does an SWI to get back into kernel mode, which busy loops waiting for a flag to be raised that indicates keyboard data. The UART interrupt handler, when started, reads the UART, saves the character and raises this flag. Thus, we have a stack of user mode -> SWI handler in kernel mode -> UART interrupt handler in kernel mode.

What I did stuff up in my design is the wiring to the DS12C887 RTC device. I'll fix that on the next hardware revision. For now, I can get the CPLD to send a regular clock tick interrupt to the CPU, the whole purpose of the RTC device.

The fun continues! Cheers, Warren

[7alken]

totally cool ...thanks

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[Warren Toomey]

Status update: After fighting a mysterious RAM bug on the 6809 SBC this past week, I finally realised that I had the Verilog code for the RAM chip select wrong! With this fixed, I can now run the filesystem code from xv6 on the board. There is no multitasking yet, but each program has a usable address space of $0000 to $FDFF; the only constraint is that user addresses from $0000 to $1FFF can only contain code, no data. The operating system lives in 32K of hidden RAM from $8000 up; it gets invoked on a hardware or software interrupt, and keeps its data on a shadow page at $0000 to $1FFF.

The system call API is very Unix-like: exit, spawn (like exec), chdir, close, dup, link, lseek, mkdir, open, read, unlink, write, tcattr (en/disables terminal echo).

Next up will be to try and bring some multitasking. The system has 8K pages and 512K of RAM, so I should be able to support a dozen or so processes.

Cheers, Warren

[Tom Storey]

You might like to see my current 68k design which uses a EPM7128S to do a whole range of things like DRAM refresh, bus arbitration for multiple masters, interrupt prioritisation, and more. I'm quite amazed that everything fits in really, there's a lot going on. It's 100% written in Verilog.

I haven't tried it on an Atmel equivalent part yet because I don't have any in a PQFP100 package. I was originally looking to use a PLCC84 of which I have both, but they don't have enough pins for my design.

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[Bill Shen]

I love to see your EPM7xxx designs.  I have used verilog for FPGA designs but not CPLD designs because I am concerned about synthesis efficiency.  I designed in schematic and mega functions.  Only place I used verilog in CPLD designs is for lookup tables like small ROM and hex-to-7-segment-display.  It is amazing how much functions can squeeze into a 64 or 128-macrocell CPLD.  I’m on a quest of 3-chip retro computers+mass storage consists of CPU, RAM, and CPLD plus CF disk for mass storage.  For retro computers I have about 50 CPLD designs most of them are documented in https://www.retrobrewcomputers.org/doku.php?id=builderpages:plasmo:start

[Tom Storey]

I am blown away by how good Quartus 13 is at synthesising designs into as minimal logic as possible. Maybe more modern tools are better, but it does a very good job for it's age I think.

As much as I have going on in my CPLD I'm only using about 100-110 MCs. With a little shuffling of some pins and some minor changes I could probably reduce this a little bit and fit more in..! But I think I'm down to my last two IO pins so there isn't much more that I can (out want/need to) do really.

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[Dave White]

" You might like to see my current 68k design"

Do you have a link to your design? I'd love to see it.

[Tom Storey]

I haven't released my design files yet (hoping to get that done in the next week or two around work and travel), but I've started doing some writeups using Hackaday.io as a blog to go into more lower level details.

https://hackaday.io/project/192539-comet68k/

There's a photo of the board and a couple of posts to get started with.

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[7alken]

hi, this Comet68k is huge and profi work - I never had chance to touch 68k system yet, but was recently fascinated by wiki read about VME history and usage, so I finally got something physical, the force/plessey sys68k/cpu-1c with THICK hardware manual...  couldn't resist simply; ))

your  Introducting and System architecture articles are great, tnx