ZZRCC, Z280 SBC replacing ZZ80RC and ZZ80CF

[Bill Shen]

The discovery of Z280 UART bug made existing ZZ80RC and its cousin ZZ80CF obsolete.  As corrective measures, I can change out the free-running 1.84MHz baud clock and replace with a 74193 divider, but the two designs are really crowded and I really want to get rid of the battery- or supercapacitor-backed logic.  EPM7032S CPLD is so cheap that it makes sense use the small internal CPLD bootstrap ROM to simplify everything.  I also use the spare pins to add an I2C bus.  So this is ZZRCC which stands for Z280+RAM+CPLD+CFdisk.  It normally boots out of CF disk but in order to prepare the CF disk for booting, it has a serial bootstrap mode to load the CF initialization files.
https://www.retrobrewcomputers.org/doku.php?id=builderpages:plasmo:zzrcc
  Bill

[Greg Holdren]

Obsolete is a strong word Bill. :) :)

I haven't noticed any char issues with mine but depending on the frequency I may not have noticed it. How often does it occur?

Greg

[Bill Shen]

Greg,

OK, It is a bit obscure.  It is not observable in the monitor, but once you are in CP/M type 'dir' command 20 times.  You may notice once in a while the directory entries are not lined up in regular columns.  This is because  an output characters is repeated and throw out the column alignment.  The software is not aware of this repetition of character, it is a problem with Z280's internal UART transmitter that intermittently transmitted its content twice.  It is perfectly usable, if you can ignore the occasional double character output.

  Bill

PS, OK, I admit it may well be a personal problem of mine.  I remember laying a long brick raised bed by the front door of my old house.  One of the brick was out of alignment and every time I came home I can see that misaligned brick (nobody else can see it).  I was happy when I moved to another home because I can't stand that misaligned brick anymore!

[rwd...@gmail.com]

I have just been testing my zz80cf at 115200 no handshake with a continuous set of dir commands and am not seeing any dropped characters , tested from teraterm and g95 (kermit). Using CPM3.

However if I use cpm2 I do see occasional repeated characters from dir command.

Does this mean the bug might be in the cp/m bios  io handling rather than a bug in the z280?

Richard

[Bill Shen]

I tried the same 'dir' test on my ZZ80CF and observed repeated characters in both CP/M2.2 and CP/M3.  My set up is 115200 O-8-1, 24MHz clock.  Monitor is ZZ80CF v0.4 2/8/19,  CP/M2 is dated 11/7/18,  CP/M3 is dated 11/12/18.  I recall there were some issues with CP/M3 and you may have a newer version of CP/M3.
  Bill

[Bill Shen]

Here is a file for you to try in CP/M2 and CP/M3.  It is a text file where every line is the same.  upload to your CP/M drive and use 'type filename' command to display the file.  Every line should be the same length, but once in a while you'll see lines that are longer.  Looking closer at the faulty lines you should see a random character has repeated.  This should happen in both CP/M2 and CP/M 3.
  Bill

[Greg Holdren]

Have you tried no parity? (8N1) That is what I run when not xfering the pre-boot code. I will try the file you provided tonight on both OS'es and see what I get with O and N parity.

Greg

[Bill Shen]

Yes, I tried with both no parity and odd parity.  Both settings give the same result of intermittent, random repetition of characters.
  Bill

[Bill Shen]

I made some design compromises in CF bootstrap circuit to fit the smaller EPM7032SLC44 CPLD.   Of course the design compromises were never tested so I struggled with CF bootstrap software a good deal in last couple days.  It is finally running.  CP/M is booted and running.  This is the asciiart mandelbrot running with MBASIC80 under CP/M2.  I also verify it fixed the extra character problem of ZZ80RC and ZZ80CF.

[Bill Shen]

All right, this is why I made the design compromises for ZZRCC; I want to free up enough pins and logic so I can have an I2C interface.   If you've asked me a couple months ago about having an internal ROM for CF bootstrap, mode select for serial bootstrap, compact flash interface, address decode, and I2C on a 32 macrocell CPLD, I'd have said "no way!", but here it is.  The CPLD is 100% utilized in logic and pins.

Now I'm going to redesign it to fit the acrylic Arduino mega case and change out the I2C interface to handle the 320x240 QVGA display as a shield
  Bill

[Terry Fox]

I noticed that BG Micro has these CPLDs on sale for $3.95 each.  EPM7160ELC84-20:

https://www.bgmicro.com/ICS1040.aspx

I wonder if it is bigger than the one you are using, the price seems nice.

I've played with Pals & Gals & FPGAs some, but not CPLDs.  Would this be a good CPLD to learn with?

Thanks, Terry, N4TLF

[Bill Shen]

Do not buy EPM7xxxE! it requires a specialized programmer that's almost impossible to find.  The EPM7160E is a monster in term of macrocells: 160, but unfortunately it need the special programmer.  The one I used in ZZRCC is EPM7032S which only has 32 macrocells, it is about the smallest (and cheapest) CPLD you can find.  It is equivalent to ATF1502AS which is about $2 at Mouser.  EPM7xxxS CPLD can be programmed with an inexpensive (under $5) programmer that is readily available.
  Bill

[Terry Fox]

Thank you Bill!

Terry

[Bill Shen]

I bought few 1.5" I2C 128x128 OLED grey scale display to experiment with, https://www.ebay.com/itm/3pcs-1-5inch-I2C-OLED-Display-Module-SSD1327-Driver-Chip-Support-for-UNO/153696175425

The I2C pin assignments are not the same as 128x64; the VCC and GND pins are swapped.  It also need 8 times as many data because the screen size doubled and each pixel is represented by a nibble rather than a bit, so a 128x128 grey scale image requires 8K bytes of storage.

Here is the iconic Marilyn Monroe B&W resized to 128x128 and saved as a .bmp file.  The .bmp file was converted to Intel Hex and uploaded to ZZRCC which re-formated the data and displayed it in 16 grey levels.
  Bill

[Eric Matecki]

The VCC and GND pins on 128x64 OLEDs aren't "standardized"...
Some have GND/VCC/SCL/SDA, others VCC/GND/SCL/SDA.
I got bitten by that...

[Bill Shen]

A couple persons had asked me whether it is possible to run ZZRCC without CF disk.  The answer is yes and the following is the procedure for booting ZZRCC without a CF disk:

1.  Download and unzip ZZRCC serial loader and ZZRCC monitor from software section of ZZRCC homepage, https://www.retrobrewcomputers.org/doku.php?id=builderpages:plasmo:zzrcc
2.  Remove the jumper across T10-T11 (T10 and T11 are right next to the 2.1mm X 5.5mm power jack)
3.  Power up ZZRCC, the current draw should be 180mA nominally without CF disk.
4.  Set serial port to 115200, odd parity, 8 data bit and 1 stop bit
5.  Check the "Binary" box of TeraTerm Send file menu and send ZRSERLDR.BIN to ZZRCC.  You should see the sign on message:
ZZRCC Loader v0.1
Change serial port to 115200 N81
Auto start at 0xB400

6.  Change serial port setting to 115200, no parity, 8 data bit, 1 parity bit
7.  Un-check the "Binary" box of TeraTerm Send file menu and send ZZRMon.hex to ZZRCC, you should see the message:
...............................................................................................................................................................................................................................UX
 ZZRCC Monitor v0.5 4/16/21

8.  ZZRCC monitor is now running. 'h' will list the monitor commands.  't' will test RAM.  Do not run commands associated with CF disk (R,X,B,C) because it will hang.
 
  Bill