Having briefly looked at the rcbus issues, I fully agree with Alan's comments. After designing and successfully building several eZ80 systems, I see a LOT of problems trying to put a 50 MHz eZ80 onto the rcbus. In fact I believe you'd basically end up with an eZ80 SBC with CPU + memory + fast peripherals and a bus interface that would simply be I2C + SPI + some peripherals that MAY work with a lot of wait states or via GPIO pins.
While you may be able to interface a TMS99181A directly to an AgonLite's GPIO with it's eZ80F92 at 18.432 MHz, there are plenty of specification violations if you were to consider connecting it directly to a 50 MHz eZ80F91 or eZ80L92. For example:
tPVX - data float from CSR going inactive = 100ns whereas eZ80 could put outputs on the data bus in 4ns after CSx\ going inactive.
tW(WL) - CSW pulse width of 200ns is greater than the maximum eZ80 CSx\ wait states (9 + 7*20) = 149 ns at 50 MHz.
tA(CSR) - Data access time from CRS low at 150 ns pushes the boundary and likely exceeds maximum CSx\ from eZ80.
Any tristate buffers would only add further delays, although FET's might also work. Regardless, the eZ80 and TMS9918A bus architectures are generations apart in their timing requirements.
There would also be software constraints such as trying to accomodate tW(CS-H1) pulse width chip select high, which is 8 us or up to 400 eZ80 instructions at 50 MHz.