Fitting a QUART into a pint pot

[Alan Cox]

Another day another board.

The 16C550 UART card is nice but you only get one port and all the baud rate control etc on a card as it is designed, and maybe two if you used some of the dual variants. And then for Fuzix you need a timer card.

I figured I could do better as the 82C684 has two timers, four serial ports and a few extras. Another nice feature is that it supports Z80 IM2 interrupts and IEI/IEO. Even better it is a very close relative of the 68692 used on Tiny68K so I've already written drivers for it.

I have it basically working. Some checks left to do on the interrupt side. This board uses the full 16bit address bus rather than hog 32 low ports. Instead it takes a single low 8bit I/O port for everything.

Alan

[Steve Cousins]

Hi Alan,

That's a very capable serial module. Very nice.

You are now a proper PCB design addict :)

Steve

[Jay Cotton]

And an add bonus, the parts are still available at digi-key.

Are you going to kit this or publish the board ?

jc

[Alan Cox]

On Saturday, 21 September 2019 01:05:39 UTC+1, Jay Cotton wrote:

And an add bonus, the parts are still available at digi-key.

And mouser

 

Are you going to kit this or publish the board ?

Kits I don't have time to do (If someone else wants to then ask but wait until it's got some software and more testing!).

I've put the current bits on Hackaday

https://hackaday.io/project/167720-rc2014-quad-uart

Alan

[Alan Cox]

IM2 does indeed appear to be broken on this version because

M1 is checked on U4

P=R stays high for an interrupt cycle

so IACK has no effect as CS is high

Not hard to fix for a rev2 if I ever bother.

The other problem is that it requires your CLK is <= 8MHz because whilst you can use counter mode internally for non convenient clockrates (ie not the RC2014 one or half or quarter of it), the device is not rated for CLK > 8MHz so won't work with the faster Z180 boards. That one is harder as there is no room for a can oscillator.

Alan

[Mark T]

I didn’t look at the datasheet for u1, but does rd and wr to u1 really need to be gated by iocs?

If not you could possibly remove the 74hct32. Address decoding doesn’t need to include M1 as you are qualifying io with rd and wr.

If iack is only effective with cs active, M1 could be connected direct to iack.

Remaining question would be what if anything the z80 places on address bus during an intack cycle? Could it be made to match the address decoding or does there need to be some additional logic to enable cs during intack?

Another possibility might be to connect iorq direct to cs, M1 direct to iack, then gate rd and wr with the io address excluding M1 and iorq.

Mark

[Alan Cox]

On Saturday, 21 September 2019 19:31:51 UTC+1, Mark T wrote:

I didn’t look at the datasheet for u1, but does rd and wr to u1 really need to be gated by iocs?

Write at least does, otherwise it can flip into 68000 compatibility mode - so I did both.

The rest I am no longer sure about having played some more. The data sheet is not terribly clear on how the vectors are supposed to work so I may have another bug. I will have to double check my code and also stick the logic analyzer on it and see what is actually happening.

Alan

[Alan Cox]

The rest I am no longer sure about having played some more. The data sheet is not terribly clear on how the vectors are supposed to work so I may have another bug. I will have to double check my code and also stick the logic analyzer on it and see what is actually happening.

It works better if your IEI/IEO chain is correct 8)

Alan

[Colin MacArthur]

Please find attached a Small Computer Monitor v10 driver source & ROM for Alan Cox's QUAD-UART.

THX

CM

[Tadeusz Pycio]

IM2 does indeed appear to be broken on this version because...

Hi, Alan

Your information about the required CS during INTA for IM2 turned out to be the best doping for a job that I could not start for 2 weeks. :)))) 

Have you solved this puzzle yet? I made a similar two-port module...