Anybody used the Z80 SIO in synchronous mode with external sync?

[Mark Durham]

I may be on a road to nowhere with this but I've been trying to coax an SIO channel in my Z80 KIO into becoming an SPI master device (mode 0) with a little help from an ATTINY85.

For testing I'm talking to an SPI EEPROM (25LC256).

I've managed to get the SIO to clock out the correct stream of bits so that the 25LC526 responds, but I'm having trouble getting the SIO RX side to behave.

Below is an LA trace showing the various signals. TxD = MOSI and RxD = MISO.

The TINY85 is generating the KIO TX & RX clocks (KIO_CLK) and the SPI CLK to the 25LC256 as well as the SYNC signal to the SIO. The KIO is generating nCS on the DTR pin. The KIO sets RTS low to cause the TINY85 to generate sets of 8 clocks. nRTS goes high before the last byte of the packet as I'm using the TX Buffer Empty bit in RR0 to detect when the last byte has been transmitted. I've had to add in a short delay before setting nCS high. 

The message going out is: 03 00 00 00 00 00 00 00 00 00 00 - which is a READ command (03) starting at address 0x0000.

What I get back is: 3F FC FC 00 00 00 DA 30 F1 30 F5 30. I've tried flushing the receiver by reading the RX register until the RX char available bit in RR0 isn't set, but I can't figure out where the initial 3F FC FC is coming from. Also I can't get the SIO to give me the last 2 bytes either.

It's as though there is some RX FIFO mechanism that's got stuck.

Looking through the Z80 SIO technical manual, I can't see anything that may trigger a complete reset of just the RX queue.

[Alan Cox]

I played with the idea a bit a long time ago but I could not work out how to get the device to behave because in async it wants start/stop bits, in HDLC sync mode it bit stuffs series of 1 bits and so on. In the end it seemed easier to just use shift registers.

[Mark Durham]

I'm having a similar issue in figuring out how the SIO behaves. I'm jumping between the Zilog SIO technical manual, SIO product spec, KIO product spec and the SGS databook looking to see if there are any clues I've missed. The rest I've discovered by using an Arduino UNO to generate the clock and external sync signal by trial and error.

I will persist a while longer just in case something occurs. Shame really as it would be nice to get an SIO channel - with a little external help - to behave as an SPI master.

[Mark Durham]

Well I finally figured it out.

The initial 3 bytes I was getting - 3F FC FC - were phantom bytes because I made an assumption about how the Z80 SIO operates! When the SIO clocks out 1 byte, it does not automatically have 1 received byte available like a normal SPI transfer would give you. The received byte has been captured by the SIO, but seems to be inside some sort of Rx FIFO queue.

Once I figured that out, I found I had to generate additional RxC clocks after the data had been sent in order to extract the remaining bytes from the Rx FIFO.

Here's the LA traces of what's occurring for the 1st message:

And the output from the SIO SPI code:

As this is my proof of concept, the SPI clock is currently quite slow at around 500Hz.

Next step is to increase the clock and check that the theory still works.

Hopefully, if it still hangs together, I've got one of Steve Cousins SC104 SIO/2 modules to butcher to graft in an AVR type micro to handle the clock generation etc.