Another question: regarding clocks for Z80 serial devices ...

[Marten Feldtmann]

When one assumes, that we have either a KIO or a SIO marked as 12 MHZ version (so it is capable of running at that speed) and we drive this device with 4 MHz PHI/CPU clock - but the serial clock input is driven with 7.xx MHz. Would this work ? Or must the serial input clock (if used) always be smaller than then PHI clock of the CPU connected to the device ???

[Mark Durham]

I'm not sure as I'm also looking for some details on the KIO XTALI and XTALO pins. As it's presumably a simple clock oscillator/driver with a divide by 2, I would be guessing that it is completely separate from the rest of the chip timing. However, there must be some limitations!

My KIO datasheet (PS011804-0612 - Jun 2013 Rev 04) make very little reference to these pins. It has a paragraph about using a crystal and that the two capacitors should be around 33pF each. And there is a description of the CLKOUT pin which simply says it's the XTAL frequency / 2. I can't find any technical details beyond that.

My interest is that I've got a 20MHz Z80 (PLCC device) and I'm wondering if I run it at 14.7456MHz, and feed that clock into XTALI of my KIO (spec'd at 10MHz), would I get 7.3728MHz on CLKOUT? 

[Bill Shen]

 KIO xtal input is nominally 3.6864mhz and independent from the CPU clock.  You are right the datasheet is very vague about that.  It may very well run with 14.7 Mhz input.  Both KIO and PLCC Z80 can be aggressively overclocked.  They are likely operational at 29.49mhz.

Bill

[Douglas Miller]

I know that the original Z80A-SIO chips may have been able to work at 4MHz (PHI), but their serial engines (RxCA/RxCB) were not capable of exceeding 500KHz (reliably). In that case, the PHI was used to snoop instruction cycles and react to RETI instructions (I'm not sure if it had other purposes - I think the RD/WR cycles are not tied to PHI, from the Z80-SIO perspective). A more-modern Z80-SIO datasheet ties the serial clock maximum to the CPU frequency, at least for certain serial modes (i.e. the serial protocol engine probably runs off the PHI and must be fast enough to handle the serial data processing required - requiring that the serial clock to be slower than PHI).

The KIO datasheet is rather terse, but it does say "two separate serial I/O channels that are completely compatible with the Z84C4x SIO" and so it is reasonable to defer to the Z80-SIO datasheet for more detail. Quoting that:

Data Rates in Synchronous or Isosynchronous Modes:
–0-800K Bits/Second with 4 MHz System Clock Rate
–0-1.2M Bits/Second with 6 MHz System Clock Rate
–0-2.5M Bits/Second with 10 MHz System Clock Rate

[Bill Shen]

 In the RC2014 world, SIO serial clock is driven with 7.37Mhz CPU clock.  I’ve successfully overclocked CMOS SIO (Z84C4x) to 14.7Mhz or even 29.5Mhz, so KIO is likely OK with 14.7Mhz for xtal input, or even 29.5Mhz.  I have a few designs with KIO, I should try that sometime.

Bill

[Douglas Miller]

I'm assuming that is for running async RS-232, where the data rate is at least 1/16 the clock input frequency?

[Marten Feldtmann]

Ok, perhaps a more specific question. I have an old Z80 NMO-Z80 computer running at 4 MHz and I want to connect a KIO to it (I have lots of 12 MHz version of that) and I wanted to connect to the clock input of the serial devices something like 7.xx  Mhz to get 115 KBaud ...transfer speed. Would that be possible ?

[Bill Shen]

My experiences with KIO are async x16 serial communication either with my own CP/M implementation or with RomWBW which does support KIO.  I’ll build up another KIO-based SBC tonight and try different ways of driving the xtal input as discussed here.

[Bill Shen]

Built up a RomWBW-capable SBC with KIO and replaced the 3.68MHz crystal with either 3.68MHz oscillator or 7.37MHz oscillator.  While KIO appeared to work with 7.37MHz oscillator driving the XTAL1, the CPU clock must be higher than 2x7.37MHz (e.g. 18.4MHz) for RomWBW to boot normally.  This is also true with 3.68MHz oscillator that CPU clock must be higher than 2x3.68MHz (such as 11MHz) for RomWBW to work.  It turned out this is also true using the original 3.68MHz crystal where CPU clock needs to be higher than 7.37MHz to run RomWBW.  I normally run the KIO SBC at 22MHz or at least 14.7MHz, so I've not noticed the problem at lower CPU frequency.  My board that ran RomWBW OK at 14.7MHz and at 11MHz actually won't run at 7.37MHz or lower CPU frequency.  This is surprising and needs more investigation.
  Bill

[Mark Durham]

That's an interesting observation. I kinda hoped that the crystal oscillator subsystem within the KIO would be separate from the workings of the SIO, PIO & CTC subsystems. I've got some 14.7456MHz 4-pin oscillators coming soon and am keen to experiment with my little KIO board. In my configuration, I'm hoping that the CPU clock would also be the XTALI clock, but perhaps that's not possible.

[Douglas Miller]

Interesting. The does seem to suggest that the serial engine needs some amount of PHI advantage over the serial clock, although I would want details about how RomWBW is failing. The Z80-SIO datasheet does imply such a dependency by specifying a 5x ratio of PHI to serial clock. It sounds like you are finding, at least for async RS-232 operation, that the ratio can go as low as 2x. At least for modern fabrication parts.

My experience (40 years ago) was that trying to run a Z80A-SIO in SDLC mode on a 4MHz system using a 1MHz serial clock was not reliable, but unfortunately I don't remember the exact nature of the problem. As I recall, it was not as obvious as simple data corruption (i.e. it was some sort of operational failure).

[Bill Shen]

I've made some progress toward characterizing KIO serial clock vs CPU clock.  KIO appears to run when its 3.68MHz crystal is replaced with 7.37MHz oscillator or even 14.7MHz oscillator.  The CPU clock does not need to be more than 2X serial clock if interrupt is not enabled.  The board will run fine with CPU clock slower than serial port clock (e.g. serial clock=14.7MHz, CPU clock=3.68MHz) if I run a simpler version of CP/M that does not use interrupt for serial port.  Similarly, it will run fine with a version of RomWBW generated with INTMODE=0 (no interrupt).  So the next step is to understand why enabling interrupt requires CPU clock more than 2X faster than serial clock.

[Mark Durham]

I have a limited selection of crystals to play with on my small KIO design. My default setup is a KIO (10MHz version) with a 3.6864MHz crystal and a Z80 (20MHz version) with a 7.3727MHz oscillator.

If I swap out the 7.3728MHz oscillator for a 1.8432MHz oscillator (keeping the 3.6864MHz crystal on the KIO), I can correctly run Grant Searles Z80 monitor (which uses interrupts) and boot into CP/M.

I'm not sure how useful this information will be but it does suggest that the KIO UART clock can be higher than the CPU clock - in this case twice as high.

[Bill Shen]

So far my hardware will crash whenever the interrupt is enabled while CPU clock is lesser than 2X IO clock, but run OK when CPU clock is more than 2X IO clock.  Test case is IO clock=7.37Mhz, it crashes if CPU clock = 8Mhz, but runs OK if CPU clock = 22Mhz.  I’ll look up Grant Searles’ monitor and port it to my hardware.

[Mark Durham]

Just in case it helps, I've attached the schematic of my little Z80+KIO board along with the assembler source of Grant Searles monitor that I modified to suit my KIO board. It assembles using the online Z80 assembler at ASM80.COM.

[Mark Durham]

I got around to modifying my Z80+KIO board so I could easily swap crystals and did a few quick tests with the few crystals that I have to hand. I used Grant Searle's CP/M monitor but modified for my setup.

With a 3.6864MHz crystal across the KIO XTALI & XTALO pins, SIO interrupts seem to work correctly with a Z80 crystal oscillator at 1.8432MHz, 7.3728MHz, 10MHz and 18.432MHz.

If I change the KIO crystal to a 7.3728MHz one (simply doubling the baud rate for the same code), and repeat, then the SIO interrupts seem to work correctly with a Z80 clock of 7.3728MHz, 10MHz and 18.432MHz.

The interrupts don't appear to work with the 1.8432MHz crystal oscillator on the Z80 and the 7.3728MHz crystal on the KIO.

[Bill Shen]

The observation that CPU clock needs to be greater than 2X IO clock is a red herring!  An user of K80W observed that 2nd serial port receive input is floating thus generated lots of interrupts that RomWBW needs to handle.  This is why CPU clock needs to be faster, otherwise it will crash due to many interrupts generated by the floating RX input.  Once the serial receive inputs are pulled up, the problem went away.  K80 will now run RomWBW with CPU clock as slow as 1.84MHz.  Thank you, Paul, for solving this nagging problem.
  Bill