Who said PCB design was addictive.. 8)

[Alan Cox]

Started building the next batch of board designs, then hopefully will do the fixes to these and some of the previous bits in time to get them back for Christmas when I'll have time to work on all the software bits. I have the 65C02 monitor basically done, the 1802 has IDIOT and some other stuff that is usable. The 6303 will require something as will the 80C188. The Z8 I am hoping I can make run the image of the Z8 BASIC to start with as there seems to be a lack of usable open source Z8 tools.

CPU boards

- 1802 (and optional 1861)

- 65C02 with I/O moved to FExx

- 6803/6303

- 80C188

- Z8

Plus

- Wiznet 830MJ adapter (not as powerful as the SPI based ones but hopefully much easier to build)

- Arduino shield adapter using a Z80PIO and optional PCF I2C

Alan

[Steve Cousins]

You probably still think you can stop any time you want to... you just don't want to :-)

[Greg Holdren]

Alan,

Cool, so the 6502 board HW is behaving as expected?

I still have some 80C188 boards I got back from the 90s. A lot of serial ports on it with a plugin floppy controller board.  (not IBM compatible at all) Wrote programs using Microsoft MSC 6.0 (16 bit binaries) on a PC and did the final build with Paradigm Linker Locator to make and burn ROMs. I had Forth going for that board and on a Multitech 33.6kbps modem too. That particular modem used a 80C188EB which is an embedded versions of the '188. Just have to disable the watchdog timer HW, cut and jumper does wonders.  ;)

Greg

[TonyD]

Glad to see some love for the 1802 and Z8. I've got tentative plans to follow up my 8052-basic board with a Z8 basic so I'll be interested to hear how you get on.

Yes, designing PCB's can get out of hand :-) I did a quick tally for PCB designs I've done in the last 5-years for Arduino, Raspberry Pi, my music stuff and RC2014 and I was amazed to find out was over 80 boards !

At one time I would breadboard an circuit idea and when happy with the design build it on vero board. Now I just go straight to PCB, wait until I've a few other designs complete, then send them all off to be manufactured. Then spend the time I'm waiting for them to start building the previous batch of projects.

So I share your passion / addiction :-)

Tony

[Alan Cox]

On Friday, 11 October 2019 06:51:45 UTC+1, Greg Holdren wrote:

Alan,

Cool, so the 6502 board HW is behaving as expected?

I will find out once the other bits I need arrive next week 8) Right now I don't have any slow enough oscillators to hand. Because the 65C02 wants to complete the entire bus cycle in half a clock I need a 2MHz oscillator for now as 2MHz gives 250ns which is still pushing it with 200ns eprom plus the R/W gating and the time the CPU needs the signal stable.

Alan

[Alan Cox]

Cool, so the 6502 board HW is behaving as expected?

I will find out once the other bits I need arrive next week 8) Right now I don't have any slow enough oscillators to hand. Because the 65C02 wants to complete the entire bus cycle in half a clock I need a 2MHz oscillator for now as 2MHz gives 250ns which is still pushing it with 200ns eprom plus the R/W gating and the time the CPU needs the signal stable.

Alan

It is working at 1.832MHz at least. With a WDC 65C02 CPU I get some oddities I don't understand - but the timings are different and there are other differences (much sharper edges I believe) so it may be something silly. With a 'classic' Rockwell CPU life seems better including the CF adapter and banked RAM/ROM. The CF seems to work best with the Rotten Snow CF adapter and it set to gate the R/W lines but I've been fiddling with enough other things I need to go back and confirm that further.

I'm sitting in Fuzix with the following configuration

6502 CPU card with Rockwell 4MHz part at 1.8MHz

512K RAM/ROM (I tried two one works, one doesn't - both work on Z80. I suspect dodgy soldering on my part somewhere so will need to investigate)

Rotten Snow CF adapter at 0x10 jumpered to gate the I/O read/write

Ancient computing 6522 VIA at 0x60

Ancient computing 16x50 with a 16550A at 0xC0

SC129 at 0x80 (as a debug port)

It should also be possible to run with EHbasic/monitor setups and a flat 32K/32K RAM/ROM card if you adjust the I/O address assumptions in Ben's code and rebuild it but I've not tried that

My current plan to investigate further is twofold: see how the 6303 behaves given it has similar bus cycles, also build another MMU card and test with that and linear RAM.

If you want a PCB let me know - and if we have any 6502 experts who have ideas why the WDC part is being a pain that would be helpful too.

Alan

[Alan Cox]

So I think I understand one possible WDC problem but I'm really not sure the right way to deal with it.

On the falling edge of the clock at the end of a write cycle the CPU holds the write data for tWH (the write hold time). At the same point the dropping of the clock causes a two NAND gate sequence to raise \WR on the bus. On a 'classic' 65C02 tWH is >=30ns so the \WR signal drops before the write data starts to go invalid. On the WDC part it's 10ns so with a 74HCT part it is quite possible that \WR drops shortly after the data has begun to change. I don't unfortunately see a way to verify this without some rather fancy scopes.

Other than that the timings look ok. At 4MHz the 512/512K MMU configuration setup is theoretically marginal with the SN74HCT138/9 but that could be swapped with AHC but except for worst cases is in spec. The memory side seems to have a fair bit of headroom because the address is stable long before r/w go low.

Alan

[Mark T]

Maybe take a look over at 6502.org. I think i read somewhere that it was recommended to use the input clock instead of output clock on the wdc 6502.

Mark

[Alan Cox]

On Wednesday, 16 October 2019 02:09:46 UTC+1, Mark T wrote:

Maybe take a look over at 6502.org. I think i read somewhere that it was recommended to use the input clock instead of output clock on the wdc 6502.

Mark

That makes sense as it gives you some extra time, although on the WDC part the documentation quite pointedly tells you that delay is no longer quantified or measured. Looks fairly easy to test however so I shall have to try that as well as a 74AHC part. I really want to get to the bottom of it so I can get on with trying to do a 65C816 at silly speeds (which looks doable as you can get preassembled 10nS 4MB SRAM modules with 2.54mm spaced connectors.

Alan

[Alan Cox]

Some progress. Not yet tackled the 65C02 but that's on the list to look into because it's easy enough to switch to AHC or to add a jumper to use ø0 not ø2.

The Z8 I screwed up sufficiently that it needs a second revision before even trying. But all is not lost - because it has a clock on it I've already repurposed one of the failed boards by simply soldering the 7.3MHz can oscillator and a 40pin connector onto it. Bingo instant clock board!

The 6303 is working much to my amazement. Not quite first time because I had a bad connection somewhere but with that fixed it boots, it loads a sector from CF card and pronounces it not bootable - which is reasonable because at this point it isn't. The onboard serial dividers are a bit awkward but if you have a 2MHz part then running with the classic RC2014 clock gets you 115,200 baud - a bit fast for a 2MHz CPU but it will do to get going. For the 1.5 and 1MHz parts the internal serial port is a bit of a pain to use at near the CPU speed if using 'normal' baud rates.

Not sure what I am going to run on it yet. Eventually I want to run Fuzix on it but that involves porting a C compiler and toolchain to it instead of the rather basic 6801/3 assembler. At least it's a nice instruction set.

And of course there's an emulator for it (and the 1802 although I've not started on that one yet so have no test code).

Alan