My SBC or Old MacDonald had an interrupt: IEI -> IEO

[Richard Lewis]

I'm in the process of ripping up my first design of a Z80 SBC and having rethink. Originally I what I came up with is a SBC on a single RC2014 form factor card; taking a few liberties with the original layout by "un-cutting corners" for extra space. The Gerbers are now in the hands of JLPCB and I'm waiting patiently by the post box. With the exception of the headers it's an all SMD design (in case you are wondering all the passives are on the backside). The goal is to use discrete Z80 peripherals and a Max7000 CPLD for the glue logic as opposed to cheating with a Z180. To answer your question: Yes, the ROM is a socketed PLCC; I couldn't find a 3D model for a 32 pin PLCC socket. 

I tested this on a breadboard with the equivalent TH parts (except the CPLD) going insane debugging the rat's nest of wires. So in principle it should work... The KiCad 5.1.4 files are here: THS-80 Model I . The THS-80 acronym stands for: Thru-Hole Sucks. 

But then after I had sent off the Gerbers I realized that: 

1. The CPLD I chose didn't have enough I/O pins for my design. This necessitated having throw down a couple of extra discrete IC's to handle the additional glue thus defeating the purpose of having a CPLD in the first place. School boy error...
2. Lots of sharp pins pointing in all four directions almost guaranteeing a punctured finger or two
3. There was no particular reason why I had to stick with such a small (2"x4") form factor. As a consequence, I ended up with a 4 layer board because of the routing nightmare caused by the space constraints. 
4. I wanted a Diligent PMOD interface that would be used to support either SPI, I2C or another TLL serial. It didn't fit because of points #1 and #3
5. The bypass caps probably should have gone on the front side of the board. Since JLPCB doesn't support blind or buried via's (the 5V power plane is on layer 3) by placing the bypass caps on the back-side I violated the cardinal rule that the power trace should go to the bypass cap first and not directly to the IC VCC pin. But I suppose at the frequencies I'm working at it probably doesn't matter. 
6. I totally forgot about including a mode-2 IEI/IEO daisy chain. I guess not strictly necessary but should be available none the less.  
7. The wild-fire success of Steve's SC126 motherboard made me realize that horizontal is superior to vertical.

So the new design will look (more or less) like this:

With regard to wiring up the interrupt daisy chain; reading the Zilog application note: THE Z80 FAMILY PROGRAM INTERRUPT STRUCTURE I came up with the following daisy-chain. The SIO has priority (first in the chain) with IEO wired to the successive IEI

 (hence the old MacDonald reference in the post subject): 5V -> IEI -> SIO -> CTC -> PIO -> IEO. From my understanding the Z80 can handle up to 4 devices in a chain without having resort to external logic to handle ripple or injecting additional waits. 

I'm assuming that: 

1. I should include look-ahead logic for additional devices and possibly add wait states to the CPU. This can be done in the CPLD.

2. I've wired this up correctly? That is the SIO should get #1 priority or do I have this wrong?

 

The KiCad 5.1.4 files are here: THS-80 Model II 

Disclaimer: I just started this rewrite so the schematic doesn't pass the DRC yet and I haven't routed the traces. 

-Richard

[Steve Cousins]

Hi Richard

I see you are having fun. Best way to learn is to make mistakes and boy do I learn a lot :)

I find the 'horizontal' motherboard style to be very practical. Nice on the bench, Fewer connectors, and less soldering. The horizontal bus connector allows expansion. Once you have a horizontal bus connector, it only takes a little extra space to add one vertical connector (as you have done). 

I've also suffered physical damage from header pins sticking out. I currently like vertical header pins. They work well on a horizontal motherboard and are less dangerous. My own SC126 has vertical sockets for direct connection of FTDI serial adapters. This also helps keep everything within the PCB footprint. Of course, having things stick up may not work so well if you want to put the system in a case.

The IEI/IEO chain does seem to have a general limit of four devices without look-ahead but I assume it depends on the CPU clock speed and the rated speed of the peripheral chips. Running the processor slower should give more time for the chain to settle.

I think for a general-purpose design your priority order makes sense but I can envisage applications where the PIO might be considered a higher priority than the CTC.

Personally, I don't see the Z180 as any more cheating than using surface mount chips. To me the look of early 80s tech is important. That is why I used discrete resistors for the LEDs on SC126. You can't beat a row of pretty resistors as tech eye candy. Even filmmakers like their 23rd century (etc) space ships to have nice rack-mounted PCBs with clearly visible resistors - how quaint :) I still want an unnecessarily large computer with tape reels and banks of flashing lights that serve no purpose and no-one ever looks at. That appears to be how 1960s sci-fi films portrayed computers and it's a great look. 

Steve

On Thursday, 22 August 2019 08:46:02 UTC+1, Richard Lewis wrote:

I'm in the process of ripping up my first design of a Z80 SBC and having rethink. Originally I what I came up with is a SBC on a single RC2014 form factor card; taking a few liberties with the original layout by "un-cutting corners" for extra space. The Gerbers are now in the hands of JLPCB and I'm waiting patiently by the post box. With the exception of the headers it's an all SMD design (in case you are wondering all the passives are on the backside). The goal is to use discrete Z80 peripherals and a Max7000 CPLD for the glue logic as opposed to cheating with a Z180. To answer your question: Yes, the ROM is a socketed PLCC; I couldn't find a 3D model for a 32 pin PLCC socket. 

I tested this on a breadboard with the equivalent TH parts (except the CPLD) going insane debugging the rat's nest of wires. So in principle it should work... The KiCad 5.1.4 files are here: THS-80 Model I . The THS-80 acronym stands for: Thru-Hole Sucks. 

But then after I had sent off the Gerbers I realized that: 

1. The CPLD I chose didn't have enough I/O pins for my design. This necessitated having throw down a couple of extra discrete IC's to handle the additional glue thus defeating the purpose of having a CPLD in the first place. School boy error...
2. Lots of sharp pins pointing in all four directions almost guaranteeing a punctured finger or two
3. There was no particular reason why I had to stick with such a small (2"x4") form factor. As a consequence, I ended up with a 4 layer board because of the routing nightmare caused by the space constraints. 
4. I wanted a Diligent PMOD interface that would be used to support either SPI, I2C or another TLL serial. It didn't fit because of points #1 and #3

1. The bypass caps probably should have gone on the front side of the board since JLPCB doesn't support blind or buried via's (the 5V power plane is on layer 3). So I violated the cardinal rule that the power trace should go to the bypass cap first and not directly to the IC VCC pin. But I suppose at the frequencies I'm working at it probably doesn't matter. 

1. I totally forgot about including a mode-2 IEI/IEO daisy chain. I guess not strictly necessary but should be available none the less.  
2. The wild-fire success of Steve's SC126 motherboard made me realize that horizontal is superior to vertical.

So the new design will look (more or less) like this:

With regard to wiring up the interrupt daisy chain; reading the Zilog application note: THE Z80 FAMILY PROGRAM INTERRUPT STRUCTURE I came up with the following daisy-chain. The SIO has priority (first in the chain) with IEO wired to the successive IEI

 (hence the old MacDonald reference in the post subject): 5V -> IEI -> SIO -> CTC -> PIO -> IEO. From my understanding the Z80 can handle up to 4 devices in a chain without having resort to external logic. 

[Richard Lewis]

Hi Steve,

With regard to the Z180, well that's the next iteration which I will call the THS-80 Model III. Next is a eZ80 and probably finish up the series with a single FPGA in the center of the board looking very lonely. Somehow I'm thinking of Edwin Abbott's "Flatland" whilst typing this... 

-Richard

[Steve Cousins]

:)

[Mark T]

Hi Richard,
Any chance of a pdf version of the schematic?

Used plcc smt sockets for eproms many years ago. Very tricky to solder by hand due to pins inside. Not very reliable connections to device after only a few changes.

For PMOD you might want a bit more space to adjacent connectors. Or maybe use a pin header and short ribbon cable to the PMOD, this might mean mirror image of the connections.

Mark

[Richard Lewis]

Hi Mark,

1. I'll post schematic PDFs later once I get to the office and the coffee starts to work. 
2. Good thing about solder paste and a reflow oven is that I don't need to worry about tricky pins any more. For hand work (like cleaning up bridges or fixing tombstones), I do own a Hakko iron with some specialty SMD tips that can allow me to work in some very tight spots. 
3. Thanks for the advice about the PMOD! I tried fitting one of my PMOD modules on a stipboard mockup and yep... need more space around it. 

-Richard

[Sergey Kiselev]

Hi Richard,

It is a pretty cool board! I actually like the small form factor version :-)

To that extent, you could have used Z84C15, which includes Z80 CPU, CTC, SIO, and PIO on one package. That would save some PCB real estate, simplify the board design, and reduce the components cost.

The only drawback is that the I/O addresses and the interrupts priority is fixed in Z84C15.

Thanks,

Sergey

[Richard Lewis]

Hi Sergey,

I have 2 Z84C14s that I picked up on eBay so that's next on the list. When I was totally new to digital electronics (early this year) I went on a buying spree with Mouser Electronics. Now I have quite a large inventory of unused SMD parts. I'm using discrete components for the first board since I think building your own SBC with a Z80 is right-of-passage of sorts. I suppose if I really wanted to be authentic I should use NOS NMOS parts and 1-bit DRAM.  

Looks like my boards have been fabricated and are on their way from China. Will post an update once it's built. 

-Richard

[Bill Shen]

I'm working on a Z84C1516-based SBC for Arduino Mega enclosure (2.1"x3.7").  It is basically the Micro80 ( https://groups.google.com/forum/#!topic/retro-comp/9d9695-l0Sk ) with only one RC2014 expansion bus and bunch of LEDs driven by the PIO.  Z84C15 provides the necessary address decode so I can have paged ROM, banked RAM and compact flash interface with the addition of 2 common TTL logic.  The design is simple enough to fit in the standard size RC2014 board.  My experience with Z84C1516 on Micro80 is that it can reliably overclocked to 24MHz & higher.  The limiting factor is likely the memory subsystem rather than CPU.

Once you have sufficient memory and I/O on board, the external bus interface simplifies rapidly so 80-pin expansion becomes unnecessary which, in turn, save board space and simplify signal routing and reduce the board size further
  Bill

[Richard Lewis]

Schematic's attached as well as gerbers for the first board. Any advice or corrections are appreciated. Again I don't intend to sell these boards so I'm of the attitude: "as long as it works..."

On Thursday, August 22, 2019 at 7:11:48 AM UTC-7, Mark T wrote:

[Bill Shen]

Richard,
I think you can free up the M1 and Page pins on the CPLD. Use one of the freed pin to drive the two ROM_CS LEDs, use other freed pin to drive bank_A15 pin to A15 of RAM and ROM. This way you can get rid of the two TTL logic and have 16 usable 32K banks for RAM and for ROM.

Your IEI and IEO connections seem 'weird'.

The IDE/CF interface logic may be troublesome--the CF chip select can't assert until IORQ is asserted, but by then WR or RD is also asserted, so you don't have sufficient setup time from CF chip select to WR or RD. Some CF disks might work, but many will fail.
Bill

[Mark T]

I only took a quick look so far but i think you have the IEI IEO chain running in the opposite direction to Steve’s.

Mark

[Mark T]

Hi Richard,
Did you test mode 2 interrupts on the breadboard version, your first version has the IEO and IEO of J1, SIO and PIO in parallel instead of as a daisy chain.

IEO feedback from output of U2B to U2A input doesn’t make sense.

In version II IEI and IEO are in parallel between J3 and J4 rather than daisy chain, also IEI and IEO swapped compared to Steve’s. It looks like you need to connect PIO IEO to the cpld to complete the look ahead chain.

PMOD is 3v3 Vcc, so are you running 3v3 Vcc for the whole board?

Mark

[Richard Lewis]

Thanks Mark,

1. After I had sent the first version boards off I realized that the mode 2 interrupt wiring was completely wrong (i.e. I didn't know what I was doing). I did not test it on the breadboard since I did not intend to have them at all on my first board in the first place and added them later as an afterthought. Yes there is a 100% chance they are wrong. When I get the boards I'll probably just cut the traces and disable it completely
2.  As for the PMOD it will indeed have to run at 3v3 and I intend to level shift it to/from 3.3V CMOS <-> 5V TTL using this chip: TI TXB0108 8-Bit Bidirectional Voltage Level Translator I haven't added that to the schematic yet. 
3.  Yes, as Steve pointed out, I have to swap the PIO and CTC in the chain

Richard

[Richard Lewis]

Thanks Bill, 

The page pin I don't need but I was intending to use M1 for a single step circuit.

The IEI and IEO are not 'weird" they are "wrong". I intend to correct it this weekend. 

Anyway for my version 2 board I've switched to a larger QFP-100 so I have plenty of I/O pins to play with. All of the chip select functions are in VHDL. 

-Richard