High Low, or Low High

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Interocitor Steve

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May 16, 2023, 11:50:01 PMMay 16
to retro-comp
I should know this.  My attempts to look this up have been fruitless.

I will be manually loading a JP nn instruction at address 0x0000.  This instruction will not be built with as assembler, but with the Interocitor front Panel, one byte at a time, at addresses  0x0000,  0x0001, and  0x0002

The JP opcode is 0xA3.

The desried jump address is 0x8055.

So, do the first three memory locations contain (1)

0000 A3
0001 80
0002 55

or should they contain (2)

0000 A3
0001 55
0002 80

I know 16 bit values are usually stored Low Byte followed by High Byte, option (2), when using index registers.  I would ASSUME that the same is true for PC registers.  But, I cannot find a definitave answer for PC register loads.

Can you guys set me straight? 
I assume the SP register will work the same way as the PC register.

=Steve.


Douglas Miller

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May 17, 2023, 1:44:29 AMMay 17
to retro-comp
What CPU is this?

Mark T

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May 17, 2023, 9:23:45 AMMay 17
to retro-comp

If its a z80 then unconditional jump is C3.

Lowest byte at the lowest address.

On Wednesday, May 17, 2023 at 1:44:29 AM UTC-4 Douglas Miller wrote:
What CPU is this?

Tom Storey

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May 19, 2023, 7:02:07 PMMay 19
to Interocitor Steve, retro-comp
Z80 is little endian, therefore #2 - there's never a situation where it will be stored as #1.

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Interocitor Steve

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May 29, 2023, 9:59:23 AMMay 29
to retro-comp
It is a Front Panel Z80 with a challenge.
FPM all.pdf
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