I should know this. My attempts to look this up have been fruitless.
I will be manually loading a JP nn instruction at address 0x0000. This instruction will not be built with as assembler, but with the Interocitor front Panel, one byte at a time, at addresses 0x0000, 0x0001, and 0x0002
The JP opcode is 0xA3.
The desried jump address is 0x8055.
So, do the first three memory locations contain (1)
or should they contain (2)
I know 16 bit values are usually stored Low Byte followed by High Byte, option (2), when using index registers. I would ASSUME that the same is true for PC registers. But, I cannot find a definitave answer for PC register loads.
Can you guys set me straight?
I assume the SP register will work the same way as the PC register.