I decided not to go the RC2014 route in the end given all the fun some of the peripherals turn up with non Z80 like busses.
The basic concept is pretty simple. Nail 512K of RAM to the address and data bus plus some GPIO pins for banking - completely ignoring any requirement to match the bits up (because only the CPU access the RAM and it's the only memory device..so who cares how it is wired ?) and take the onboard SPI, GPIO and serial out so I can hang SD card and the like off it.
I was going to stripboard it so used Fritzing but with a bit of very gentle persuasion and an oversized PCB Fritzing autorouted it and JLCPCB wanted peanuts to fab it. So far I've fixed a couple of errors where the power rails were not all connected together and cooked an econoreset because I missed the magic words 'viewed from below' but all the power now seems to be correct, the reset line works and all the other rails I've checked seem reasonable.
Next adventure is adding the CPU, which at least in the 68HC11 case can be its own step because the CPU can run with onboard UART and without external RAM attached as it can be set to download into the 256 bytes of RAM and run the result. Enough to test and run test programs for the RAM etc I hope.
The final goal is 512K RAM, SD card and maybe some other SPI devices as I've got a couple of chip select lines so room for a bit more than just an SD interface.
From the software side the CPU has 256 bytes of internal RAM which are thus not banked and should be enough to get by. If it works out then I may get a 68HC811 so I can put the bootstrap into EEPROM and boot off SD card nicely.
Alan