Z80 IM2 vector table memory alignment

[Douglas Miller]

I was recently looking (again) at the interrupt timing/response in the datasheet for the Z80. I ran across this statement:

"The lower eight bits of the pointer must be supplied by the interrupting device. Only seven
bits are required from the interrupting device, because the least-significant bit must be a 0.
This process is required, because the pointer must receive two adjacent bytes to form a
complete 16-bit service routine starting address; addresses must always start in even locations."

This struct me as wrong, as I distinctly recalled using odd vector addresses and even placing a vector at xxFF in the table. I checked a vintage 1979 Mostek datasheet, and found the same wording as above.

I dug up the old code I had, and sure enough the vector table is set at 20E1H and the "tick" interrupt vector is stored in locations 20FFH and 2100H. The hardware required the tick interrupt use a vector of 0FFH for simplicity (on a very crowded PCB).

I vaguely recall getting confirmation from some reliable source about what the Z80 actually did in the case of odd vectors, and a vector at xxFF, but am not sure where that information came from.

Anyone else have experience in this space? Since I know this code works on real vintage Z80s, I have to just assume the datasheet has been wrong/misleading since the beginning.

[Alan Cox]

> I vaguely recall getting confirmation from some reliable source about what the Z80 actually did in the case of odd vectors, and a vector at xxFF, but am not sure where that information came from.
>
> Anyone else have experience in this space? Since I know this code works on real vintage Z80s, I have to just assume the datasheet has been wrong/misleading since the beginning.

The data sheet is wrong, all the books are wrong because they copied
it without checking.
The CPU just forms an address using I as the high byte and the vector
as the low, then fetches 2 sequential bytes

[Phil G]

I think its to avoid page wrap if say a vector was to start at 0xFF - ie to ensure high and low bytes of the vector are on the same page, the I register being pre-set.

[Douglas Miller]

Except that this code/hardware actually places the vector at 0xFF - and it works. It seems that the Z80 actually increments (carry into) the value from the I register to get the second byte of the routine address. I'm guessing Zilog either intended the hardware to work as described (but it ended up not), or just didn't want to deal with the questions that arise from odd alignment. I'm not sure about other peripherals, but the Z80-SIO at least works with odd vectors (allows bit 0 to be "1").