Memory read cycle.

[Tadeusz Pycio]

I am designing a memory module and would like to add memory shadow functionality, but I am missing one gate. Is it possible to "cheat the system" like this? Theoretically the MREQ and RD signals end up similar in the memory read cycle. This requires faster memory, but the W27C512s are mostly 45ns, so for a 7.38 MHz clock they should easily suffice. Has anyone encountered a similar solution?

[Tadeusz Pycio]

The schematic has an error, the gate output should control /CE ROM and CE2 RAM

[Tadeusz Pycio]

Eventually I can do something like this, I will stop having such a dilemma :)

[Steve Cousins]

It looks like it will work to me. 

I use a similar circuit for some of my designs (eg. SC114). Not quite the same, but similar. 

Given that RD and MREQ have very similar timings then the overall result of my circuit should be about the same as yours with regards to the RDROM signal and the RAM chip. 

I connect the RAM CE2 signal to the ROM CE so that is slightly different to your circuit. Given MREQ and RD have similar timings it amounts to much the same timings for the ROM to get both OE and CE low. Actually, your circuit better meets the timings for typical ROM chips which allow more time for the ROM CE than for the ROM RD.

I think there is one issue. Not sure if it is a bug or a feature. When the ROM is paged in and you try to write to the ROM area, the RAM will be written to. At this instant the RDROM signal will be high as RD is high. When RDROM is high the RAM is enabled at CE2.

Steve

[Tadeusz Pycio]

The function of writing to RAM while ROM is active is an intended action. This will enable the ROM BIOS to be tested after switching to all RAM. Two 32kB memory banks are also a bonus. Preliminary PCB render below.

[Derek Cooper]

Looks interesting, I think maybe you have missed a de-coupling cap for U2

Derek

[Tadeusz Pycio]

I've finished the work on this module, now it would be necessary to test the concept in reality, but that's some time away as the other projects are not finished.

[Tadeusz Pycio]

Module assembled, time for testing.

[Steve Cousins]

Good luck

[Tadeusz Pycio]

The module passed all tests. My concerns that the delays introduced by the logic and the way the memories are controlled could cause problems proved unfounded at typical RCBus frequencies. The banks switch as intended, the RAM shadow makes it easy to test new BIOS versions. I will try to make the project available on GitHub in the near future.

[Tadeusz Pycio]

The project has been made public - https://github.com/tpycio/RAM-128kB

[Tadeusz Pycio]

Processor module with 128kB memory based on the same bank switching scheme.