RCBus 3V3 test experiment project, progress...

[7alken]

hi all, reading 2 days ago Spencer's note about loss of his friend Ken, I picked-up my goodies prepared for RCBus 3V3 to get wet by Sn60Pb40 ... although all the boards were carefully selected as the minimal possible and tweakable setup for 3V3 mods, it was quite vaguely imagined at that time ... thanks to "something", I am more lucky than wise that I didn't soldered bus connectors to sc726 clock (planned to be abused on back-side) too early "bad way", or rather as sc702 P1 extension connector IS NOT the same as all other slots K1-K6 and right side S1 (noticed only when studying schematics !!) - it went in fact ideal way ... so sc726 can have mounted required accessible jumpers and swappable xtal on back side and partial bus right-angles (I had here some 16pin to use for this partial connection, just for mechanical support) too  ... also ... 2 months ago I accidentally deleted  my 40 items mouser cart (only pdf print survived in critical state of mind, ufff) so some missing parts are not still here ... but nevermind, I also properly  tweaked sc145 cf-card connector to adapter to be twice right-angled over the Sergeys Z80-512K, having the adapter board "face-down" (LEDs will be probably bright as hell, so, also good...)) ... sc726 clock will have 4x bus freq xtal so 29.4912, divided by 2 or 4 for standard but prepared for some crazines on the bus later... this will also provide clk for uarts, while both sc139 acia (cmos hitachi HD63B50) have also pierce on them AND totally unnoticed initially, Sergeys Z80-512K ALSO generates uart clock from PLD ... nevermind ... okay )) ... on the sc726 I will run processor clock with some series damping resistor also, for HF experiments ... Sergeys Z80-512K has also already mounted the bourne resistor networks on BACK-side, buth, although only the data one needs to make room for my "DIP32+16" faster (sub 20ns) SRAM memory module, as that extra 16 machined pins will lay there unconnected (this forces module to have smd pullups there, ya, okay - but as I checked, DIP32+16 thing fits on many existing memory boards with DIP32, including Dino 2MB passive linear SRAM carrier - 4x DIP32... this is originally meant for his eZ80 3V3 system. but I will try to abuse even this one, just testing )) ... as close as possible to CPU/MEM combo will be that ugly simple unbuffered sc145 cf-card and I have also sc137 I2C bus-master (+some Spencer I2C toys and that nice 8button(led front panel ... - holy grail is extending sc726 clock by Si5351A controlled from I2C for in-system clock updates, AND cheeky as hell, I2C controlled sc142 power, modded by mcp1827-adj now - for start there will be wired close (250k pot +  150k)/30k for 2V-5V manual steering during board experiments ...) .... that all :-)

so recent setup is here:

and some "scripted arrangement" of retro-comp/rc2014-z80 goodies and current soldering progress is here ))

for the ending ... as this is quite "research/experimental project", part of it is that consulting, yes, also with Lyra ... I know that many of you are afraid of AI-slop, sure, but really, all the design comes from thinking human, but some consulting round-trips were and are useful also with machine ... she, knows only things statistically gathered from outside world (as we all too...), which may be (and is) often corrupted ... but it may help you too, and YOU may be one of those who FIX the flaws, in fact, ... you may be the teacher ... you, the expert with decades of experience ... trying to slightly fix the world weirdness )) .. I am not, I am learning and enjoying it :-)

we discussed here some things regarding max speed achievable on that backplane, some potential pitfalls of early cmos chips etc ... I am not pushing this as some kind of butt-saving silver bullet, no (actually, myself, already found some guy designing some "embedded micropython miracle" for picocalc, advertising it as almost "next generation fusion reactor, or so", ... but quite funny, and probably claude-assisted at 80% ... it is up to thinking humans to decide ...... no doubt).

https://chatgpt.com/share/697dae8a-9e14-8000-b139-a99fc93ee540
https://chatgpt.com/share/697daea1-5a6c-8000-bb9e-ac2fc114b3b7
https://chatgpt.com/share/697daeb4-10e4-8000-b013-9fc04ef5a32c

peace,
Petr

[Mark T]

Did you know that you can have more than one sentence in a paragraph?

You might reach 29.5MHz at 5v or a little higher voltage and cool it down, but maybe not at 3.3v. Using 74LVC or 74AHC might improve your chances. ROM speed and address decoding are probably going to be the main bottleneck.

[7alken]

Excuse me Mark for that mess, sure. This was wild ...

It is not only for Z80, yes, while Bill Shen was pushing it to limits also. And exactly those LVC and AHC are in mind, I have here some in DIP, if available. I tend to use machined sockets also because of possible crazy adapters for drastically cheaper TSSOP variants. Just have on order the cheapest ones from Toshiba (limited set, nice simple datasheets, cool) 74LCXxxxFT and 74VHCxxxFT, as far as I checked they are equivalents and when I ordered bunch of those flat vertical 1.27mm smd connectors, I had in mind panels of some "adapters/interposers" even to DIP, such panels can be populated also in factory (or easily baked at home) and reused, although it again enlarges paths, sure. For now that jlcpcb prototyping limit is enough, on thin 1mm/0.8mm breakable by via guides ... that was the goal. Fact is that every logic on board, including nonexisting 74lv688 can be squeezed into single tqfp44 epm3064 cpld ... and those RCBus interrupt/dma chaining jumpers on passive backplane can be abused also for JTAG TDO/TDI chaining between "just one "decode/glue" cpld per board" ... True about that NOR flash, ya - but again, Bill Shen's another cpld for tiny fast boot only. I was reading/learning here a lot :-)

So here some drafts of my latest weirdos ... 25x8 or 17x8 to fit 51x51mm panel, only 2x10pin sockets (serialisable for >20pins) and breakable headers;
(this is only something for experiments with new discrete logic, they are really cheaper and more available, sometimes - sure this makes it more expensive, but reusable again)

(this single sided are cheaper to do in factory, but natural double side layout is with shorter paths and solderable at home too, only loud thinking, as always)

    

  

will see...

I also found some more missing parts here, so ... back to soldering (that backplane grid wants far more heat ))

tnx,

Petr

[7alken]

first idea with those connectors was vertical, using that Bill Shen's trick to place thin dual-side PCB between the pins... lot more space on board, but considering boards spacing... but this is only hand-made possible; such flat horizontal thigs fitting into DIP footprints can be ordered ready-made and in volume;

P.

[Mark T]

You might also consider 74LVC1G series in SOT23, these are not difficult to solder.

I made a set of 14pin DIL adapters for 4 off 74LVC1G SOT23 to replace 7400 style, i also considered similar for 7402 format and 7404 style using 74LVC2G in SOT23-6, but didn’t get those manufactured. JLCPCB add quite a large engineering fee if the sub pcb size it less than 15mm for vscore. I used desktop cnc to vscore the panels myself but it does take some time to set up the alignment. It might be possible to avoid this fee by combining vscore and routing.

[7alken]

thanks Mark, ya, those discrete sot23 are interesitng too, but I wanted to do some single universal adapter throught b2b connector, just try it; ... so I was here busy during night shifts, several hours and may be 50 roundtrips to JLCPCB DFM check, had idea to abuse drilling instead of "vscore" on small prototype panels, and got info that its in fact USED thing, the "mouse-bites" and in fact, for primitive 2-layer the cheap panel is 100x100 mm so I initially squeezed max there (adapter for TSSOP20 footprint is finally 13.4 x 9.6 mm only, that simple primitive dual-side version, on top is TSSOP and on bottom my "7x74" 100mil pitch 2x10 FLAT socket (2mm height) ... after fighting with proper NPTH footprints for those "mouse-bites" and easy copy/paste filling th apnel I did some edge room on panel also for my simple "fiducials" for stencil, as this adapter both sides are SMD ... those TSSOP (50mil) are still solderable without stencil, only with "wick" to clean shorts, but I never did anything with stencil, so on this simple panel, I tried to learn how to do it (will use it for other tiny panels... one of them will be  9x7 plcc32 dumb carrier for yamaha ymu765 smaf midi synth). that 2 layer panel is for $2 but with 2 stencils $17, ... I wanted to try them -  next tiny panel is "7x74 DIP interposer", which is all THT in fact ... tiny breakable headers for that 2x10 100mil connector (the sockets ARE NOT breakable, so I plan to use even more 2x10 for larger chips - it ALL started 3 months back when quickly arrived HD63B50 cmos acia in soic24 and DIP24 were expected very late...)  and machined headers for DIP - all the TSSOP 14/16/18/20 will have single 2x10 connector on shared adapter and "interposer for DIP will be "breakable (again "mouse-bites") to fit inside footprint of DIP socket with some headroom (even vhen existing sockets are glued together on PCB) ; whole this connectors madness is not ideal and damaging the real purpose of tiny cases and short paths for fast signal integrity, little-bit, but at least something - I had this in mind for months and now with mouser order I decided to do it and learn that paneling - so the "DIP interposer" modules on panel will be for $2 only--- will see how much to fit there - this panel has no stencil, so probably no border with fiducials/keys, so probably 4x8 on panel, or so ... as the 2x10 100mil header is really tiny, I modified footprint to have rounded rectangle instead of circle, at least ...  will see, want to finish and sent both orders today ...



      

here, modules were too small, just barelly fit the 2x10 connector case (13.1mm) - so they were widened to 13.335 and height is under 10mm (socket), as 9.6mm ...
    

   

possibility to fit 100n on module, having GND ALWAYS also on pin 10 (and shortened to actual chip on board only, not good for DIP interposer though)
 

final panel for stencil with keys ...

  

that "DIP interposer" breakable madness ))
 

... umm, ya, wanted to experiment ALSO with fastest alternatives in soic or TSSOP, they are cheapest, tiny and fit inside DIP14 when used withthat narrow 2x10 conn ....

(but, all this can be out when CPLD mastered ...)))

ufff, thats all for now
Petr

[7alken]

Mark, I have the 7x74 panel order already in cart, but I see now I forgot to make there thicker traces for grounds at least, so will return to this. I want to do ALL  traces thicker, although not sure how width say equal to pad affects solder surface tension to leak out from pads, umm ... they are also quite long - and I had in mind also that "center gnd", so better to make little bit more space there for thicker trace also (vias only connect to bottom connector pads, they are also quite long, probably it will be moded, its nothin industriial )) and 100n on module ... possible to prepare this also. Those vias on long edges are only scope probe test points, just what fits there - regular THT pads don't for narrow DIP directly, so there is that bottom connector. Flat low height headers are not so fragile as those longer, but I decided to put female sockets on modules instead, module is only SMD and "DIP interposer" is only THT then. WIll put there also some revision letter at least too. Interposer is also almost okay over DFM, only few tight gaps around the "mouse-bites" (these mine are quite dense and it probably can be even simplified, ya).  Just found also that 100mil is legs spacing on PLCC32 9x7 which is exact match to YMU765 weird japanese QFN32, so those slong straight headers will allow to mimic PLCC32 carrier for this QFN. So far so good.

If you find anything weird, let me know, pls ... when the boards arrive, no problem to send to you the panel too :-) ... that big stencil is questionable though )) ... as whole panel will not be probably processed at once, tiny single module stencil but more of them looks better, will see ... ideas are baked slowly in background threads ))
P.

[Mark T]

Solder resist should stop any solder from being pulled away from pads. JLCPCB and most other board manufacturers use LPI solder mask, so you don’t need to increase the size of the solder resist opening as much as with older processes. JLCPCB capabilities page says you can use 1 to 1 size between copper pad and solder resist, I’ve started using 0.5mil, 0.0005 inch between copper and solder resist. 8 or 10 mil traces for signals and 12 or 16 mil traces for power should be OK.

It might be better to use combination of routing and drilled holes to separate the boards, I think recomendation is only 5mm with drilled holes.

Are you using Kicad? I hope you only need to design one board and then use some software for step and repeat for the whole panel.

I’m still using Eagle, and using python script merge.py to panelize boards.

[7alken]

thank,s ahhh, solder mask, ...I always forget  this, ya, thanks; yes Kicad, but I improvised till now, it is scriptable but for now, it is far better it is slower, when I realize later its incomplete ))
P.

[7alken]

hi Mark, and entire interested crowd )), so this is now ordered - those green caps was not seeon on DFM tool nor KiCad so, will see how it returns but no big deal...
(already can imagine sexy tweak with 4 (spectrum) slashes there ...))

that D-IP has moved 7x74 conn to the right edge of smallest DIP14 (its about aligning the connectors properly, and it allowed routing)
the module itself has 0603 pads for 100n fixed to pin10 (with these 4 exposed vias 4 to short gnd there)

     

is possible I forgot something around these vias (yellow/green here), as 3D preview in KiCad and DFM check tool showed holes through...

so, will see .. it is not confirmed yet ... I tried to chat with them, but the gnd shorting will be possibe anyway
7x74 module will be 3mm above D-IP because of combined conn heights - but I addedd also possibility to reverse the header/socket combo; this was initial idea, to have headers on module and use the legs as "heatpipes" from MHP30 ... flat conn is not fragile as that higher one, but for that 3mm gap (at least 2, because of THT machined pins soldered on D-IP) must be used the long headers AND some support for gap, in case of direct soldering into D-IP (not much practical - but flat socket for flat header can be used now too)

P.

[7alken]

surprisingly, DFM checker had lot of issues with those exposed "etched pixels" )) - treating them as SMD pads too close to THT, so I finally accepted silkscreen and welcomed smaller size;
P.